JPH02163943A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02163943A JPH02163943A JP63318967A JP31896788A JPH02163943A JP H02163943 A JPH02163943 A JP H02163943A JP 63318967 A JP63318967 A JP 63318967A JP 31896788 A JP31896788 A JP 31896788A JP H02163943 A JPH02163943 A JP H02163943A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- semiconductor integrated
- island
- high heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000011888 foil Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910000679 solder Inorganic materials 0.000 claims abstract description 9
- 230000008646 thermal stress Effects 0.000 abstract description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 239000007788 liquid Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関して、特に半導体集積回路
チップとリードフレームのアイランドとの熱膨張率の違
いによる熱応力を緩和するとともに、高い放熱性を確保
するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, in particular, alleviates thermal stress caused by the difference in coefficient of thermal expansion between a semiconductor integrated circuit chip and an island of a lead frame, and also provides high heat dissipation. This is to ensure that
第２図は従来の半導体装置を示す側面断面図であり、図
において、１は半導体集積回路チップ、２はこの半導体
集積回路チップ１を搭載するアイランド、３は前記半導
体ｓ積回路チップ１をアイランド２に固定させるための
接合材である。FIG. 2 is a side sectional view showing a conventional semiconductor device. In the figure, 1 is a semiconductor integrated circuit chip, 2 is an island on which this semiconductor integrated circuit chip 1 is mounted, and 3 is an island on which the semiconductor integrated circuit chip 1 is mounted. This is a bonding material for fixing to 2.
次に動作について説明する。従来の半導体装置は、上記
の様に構成され、アイランド２上に接合材３を介して半
導体集積回路チップ１を接合する。Next, the operation will be explained. A conventional semiconductor device is constructed as described above, and a semiconductor integrated circuit chip 1 is bonded onto an island 2 via a bonding material 3.
上記の様な従来の半導体装置では、半導体集積回路チッ
プ１をアイランド２に接合する場合、その接合材３が半
田等の場合は、半田が液体となり半導体集積回路チップ
１とアイランド２の全面にわたって広がりそれらを接合
する。In the conventional semiconductor device as described above, when the semiconductor integrated circuit chip 1 is bonded to the island 2, if the bonding material 3 is solder or the like, the solder becomes liquid and spreads over the entire surface of the semiconductor integrated circuit chip 1 and the island 2. Join them.
さらに、高温で接合するため、接合後に半導体集積回路
チップ１とアイランド２の材質の熱ｌｉｊ張率の違いに
よる熱応力が発生し、最悪の場合は、半導体集積回路チ
ップ１が割れるという問題点があった。Furthermore, since bonding is carried out at high temperatures, thermal stress occurs after bonding due to the difference in thermal elongation between the materials of the semiconductor integrated circuit chip 1 and the island 2, and in the worst case, there is a problem that the semiconductor integrated circuit chip 1 may crack. there were.
また、特にアイランド２（すなわちリードフレーム材）
の材質が高い放熱性を有するものは、半導体集積回路チ
ップ１との熱膨張率の違いがより大きくなるので、この
種の材質のアイランドの使用が制限されていた。Also, especially island 2 (i.e. lead frame material)
If the material has high heat dissipation properties, the difference in coefficient of thermal expansion from that of the semiconductor integrated circuit chip 1 will be greater, so the use of islands made of this type of material has been restricted.
この発明は上記のような問題を解消するためになされた
もので、半導体集積回路チップとアイランド部の熱膨張
率の違いによる熱応力を緩和させると同時に高い放熱性
が確保できる半導体装置を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to obtain a semiconductor device that can alleviate thermal stress due to the difference in thermal expansion coefficient between a semiconductor integrated circuit chip and an island part, and at the same time ensure high heat dissipation. With the goal.
この発明に係る半導体装置は、半導体集積回路チップと
アイランド部を接続するための接合材を、中心部分は高
い熱伝導性の薄い金属箔で、その外側を半田とし、更に
接合材の大きさは半導体集積回路チップおよびアイラン
ド部の接する面積よりも小さくして、半導体集積回路チ
ップとアイランドの一部のみが接続する様にしたもので
ある。In the semiconductor device according to the present invention, the bonding material for connecting the semiconductor integrated circuit chip and the island portion is a thin metal foil with high thermal conductivity in the center portion and solder on the outside, and the size of the bonding material is The area is smaller than the contact area between the semiconductor integrated circuit chip and the island portion, so that only a portion of the semiconductor integrated circuit chip and the island are connected.
この発明においては、半導体集積回路チップとアイラン
ドの一部の面積のみしか接続していないため、熱膨張率
の違いによる部材の伸縮があっても、その発生する応力
は小さくなる。さらに高い熱伝導性を持つが半導体集積
回路チップとの熱膨張率が大きく違うアイランドを使用
する事ができ、高い放熱性をもつ半導体装置が得られる
。In this invention, since only a part of the area of the semiconductor integrated circuit chip and the island are connected, even if the members expand and contract due to differences in thermal expansion coefficients, the stress generated is small. Furthermore, it is possible to use an island which has high thermal conductivity but whose coefficient of thermal expansion is significantly different from that of the semiconductor integrated circuit chip, and a semiconductor device with high heat dissipation performance can be obtained.
第１図はこの発明の一実施例による半導体装置を示す断
面図であり、１は半導体集積回路チップ、２は半導体集
積回路チップ１を搭載するアイランド、４は前記半導体
集積回路チップ１をアイランド２上に固定するための接
合材であり、その中心部分を高い熱伝導性を有する薄い
金属箔４ａとし、その両側を半田４ｈとした接合材であ
る。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, in which 1 is a semiconductor integrated circuit chip, 2 is an island on which the semiconductor integrated circuit chip 1 is mounted, and 4 is an island 2 on which the semiconductor integrated circuit chip 1 is mounted. This is a bonding material for fixing to the top, with a thin metal foil 4a having high thermal conductivity in the center and solder 4h on both sides.
上記のように構成された半導体装置において、接合材４
は半導体集積回路チップ１とアイランド２を接合する場
合、外側の半田４ｂが液体となって流れて接合されるが
、この中心部の金属箔が半導体集積回路チップ１の裏面
に比べその面積が十分に小さいため、結果的に半導体集
積回路チップ１とアイランド２は一部のみ接続されるこ
とになる。In the semiconductor device configured as described above, the bonding material 4
When bonding the semiconductor integrated circuit chip 1 and the island 2, the outer solder 4b becomes a liquid and flows to bond them, but the area of this central metal foil is sufficient compared to the back surface of the semiconductor integrated circuit chip 1. As a result, the semiconductor integrated circuit chip 1 and the island 2 are only partially connected.
その結果、接続後の温度下降時半導体集積回路チップ１
とアイランド２の熱膨張率の違いにより、部材が伸縮す
るが、一部の接合面でのみ接続されているため、応力が
ほとんど加わらない。As a result, when the temperature drops after connection, the semiconductor integrated circuit chip 1
The member expands and contracts due to the difference in thermal expansion coefficient between the island 2 and the island 2, but since they are connected only at some joint surfaces, almost no stress is applied.
以上の様にこの発明によれば、半導体１４８回路チップ
とアイランド部の熱膨張率の違いにより発生する熱応力
を最小にすることができ、かつ、この効果により高い熱
伝導性を有するが熱膨張率が半導体集積回路チップと大
きく異なるアイランド（すなわちリードフレーム材）を
使用することができて、高い放熱性が得られるという効
果がある。As described above, according to the present invention, it is possible to minimize the thermal stress generated due to the difference in thermal expansion coefficient between the semiconductor 148 circuit chip and the island part, and due to this effect, although the semiconductor 148 circuit chip has high thermal conductivity, the thermal expansion It is possible to use an island (that is, a lead frame material) whose rate is significantly different from that of a semiconductor integrated circuit chip, and there is an effect that high heat dissipation performance can be obtained.
第１図はこの発明の一実施例による半導体装置を示す側
面断面図、第２図は従来の半導体装置を示す側面断面図
である。
図において、■は半導体集積回路チップ、２はアイラン
ド、４は接合材、４ａは金属箔、４ｂは半田である。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a side sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a side sectional view showing a conventional semiconductor device. In the figure, ■ is a semiconductor integrated circuit chip, 2 is an island, 4 is a bonding material, 4a is a metal foil, and 4b is a solder. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
とを接合固定する半導体装置において、その接合材を中
央部が高熱伝導性の金属箔に、又その金属箔の両外側部
を半田で構成し、前記半導体集積回路チップと前記アイ
ランド部の一部分のみを接合したことを特徴とする半導
体装置。In a semiconductor device in which a semiconductor integrated circuit chip and an island portion of a lead frame are bonded and fixed, the bonding material is made of a highly thermally conductive metal foil in the center and solder on both outer sides of the metal foil, and the semiconductor A semiconductor device characterized in that an integrated circuit chip and only a portion of the island portion are bonded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63318967A JPH02163943A (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63318967A JPH02163943A (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02163943A true JPH02163943A (en) | 1990-06-25 |
Family
ID=18104994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63318967A Pending JPH02163943A (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02163943A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017045528A (en) * | 2015-08-24 | 2017-03-02 | ウシオ電機株式会社 | Light source device and fluorescent plate assembly |
-
1988
- 1988-12-16 JP JP63318967A patent/JPH02163943A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017045528A (en) * | 2015-08-24 | 2017-03-02 | ウシオ電機株式会社 | Light source device and fluorescent plate assembly |
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