JPS6281047A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6281047A JPS6281047A JP60220099A JP22009985A JPS6281047A JP S6281047 A JPS6281047 A JP S6281047A JP 60220099 A JP60220099 A JP 60220099A JP 22009985 A JP22009985 A JP 22009985A JP S6281047 A JPS6281047 A JP S6281047A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- thermal stress
- fixed
- insulating plate
- molybdenum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り、特に熱伝導に優れた高電力
半導体の放熱構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a heat dissipation structure for a high power semiconductor with excellent heat conduction.
従来、自動車用電装品に採用されている大電流のスイッ
チング手段はリレーを多用しているのが現状であるが、
スイッチングスピード、耐久性の点で問題があり順次半
導体式(トランジスタ)に置き替える傾向にある。しか
しスイッチングトランジスタのコレクタ損失は用途によ
って50〜100 (W)と大きく、かなり大きな放熱
構造を持つヒートシンク及び高熱伝導の絶縁板が必要と
なる。Conventionally, relays have been frequently used as high-current switching means used in automotive electrical components.
There are problems with switching speed and durability, so there is a tendency to gradually replace them with semiconductor types (transistors). However, the collector loss of a switching transistor is as large as 50 to 100 (W) depending on the application, and a heat sink with a considerably large heat dissipation structure and an insulating plate with high thermal conductivity are required.
この種対策を施した半導体装置は特開昭55−1186
41号公報にて知られている。即ち、該公報ベース(1
0)に半導体素子用絶縁板(3)、モリブデンシート(
31)、トランジスタチップ(32)と積み重ね、各々
半田を用いて接合する技術が開示されている。しかし絶
縁板として熱伝導率の小さいアルミナを使用しているた
め、その部分の熱伝導率が29 (W/ m−K)と極
めて悪いため5例えば自動車のエンジンルーム等の周囲
温度の高い雰囲気では、半導体チップの熱損失が小さい
(約10W以下)ものでないと実用性がなく、装置の大
形化は避けられず、又半導体チップに熱応力が加わりや
すく、半導体チップの耐久性を落し、信頼性の点で問題
があった。A semiconductor device with this type of countermeasure was published in Japanese Patent Application Laid-Open No. 55-1186.
It is known from Publication No. 41. That is, based on the publication (1
0), an insulating board for semiconductor devices (3), and a molybdenum sheet (
31), a technique is disclosed in which transistor chips (32) are stacked and each is bonded using solder. However, since alumina, which has a low thermal conductivity, is used as the insulating plate, the thermal conductivity of that part is extremely poor at 29 (W/m-K). If the heat loss of the semiconductor chip is not small (approximately 10 W or less), it will not be practical, and the device will inevitably become larger. Also, thermal stress will easily be applied to the semiconductor chip, reducing its durability and reliability. There was a problem with sexuality.
本発明の目的は、小形で、信頼性の高い半導体装置を提
供するにある。An object of the present invention is to provide a small and highly reliable semiconductor device.
本発明は、ヒートシンクを構成する金属ベース上に、絶
縁板を介して固着される半導体チップと、前記絶縁板と
金属ベース間に固着され、該両部材の熱膨張係数差によ
り発生する熱応力緩衝部材とからなる半導体装置であっ
て、前記半導体チップをシリコン系の絶縁板を介してモ
リブデンからなる熱応力緩衝部材に固着させるにある。The present invention includes a semiconductor chip that is fixed on a metal base constituting a heat sink via an insulating plate, and a semiconductor chip that is fixed between the insulating plate and the metal base to absorb thermal stress caused by the difference in coefficient of thermal expansion between the two members. In the semiconductor device, the semiconductor chip is fixed to a thermal stress buffering member made of molybdenum via a silicon-based insulating plate.
これによって、半導体チップにかかる熱応力を抑え、小
形で信頼性の高い半導体装置とすることができる。As a result, thermal stress applied to the semiconductor chip can be suppressed, and a small and highly reliable semiconductor device can be obtained.
以下本発明の実施例を第1図、第2図に基′づき説明す
る。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
第1図において、鋼等の金属ベースからなるヒートシン
ク1の上面にはモリブデンシート2が銀ロウ付3により
配置固定され、その上面には第2図に示す如く、予め両
面にメッキ層にニッケルメッキ)4が施されたシリコン
系絶縁板(シリコンカーバイト)5が高温半田6を介し
て溶接固定されている。一方半導体チツブ7は前記同様
高温半田8を介して前記絶縁板5に溶接固定されている
。In FIG. 1, a molybdenum sheet 2 is arranged and fixed by silver soldering 3 on the upper surface of a heat sink 1 made of a metal base such as steel, and the upper surface is pre-plated with nickel on both sides as shown in FIG. ) 4 is welded and fixed via high temperature solder 6 to a silicon-based insulating plate (silicon carbide) 5 . On the other hand, the semiconductor chip 7 is welded and fixed to the insulating plate 5 via high temperature solder 8 as described above.
このように構成される半導体装置はモリブデンプレート
2と絶縁板5と半導体チップ7とを加熱炉等を利用して
高温半田付けした後、前記加熱温度より低い温度で金属
ベース1に銀ロウ付けするのが作業上好ましい。In the semiconductor device constructed in this manner, the molybdenum plate 2, the insulating plate 5, and the semiconductor chip 7 are soldered at high temperature using a heating furnace or the like, and then silver soldered to the metal base 1 at a temperature lower than the heating temperature. is preferable for work.
前記シリコンカーバイト系絶縁板5は別表のとおり、熱
伝導率がアルミナの約10倍の267(W/m−K)で
あり、金属数の熱伝導率を有している。この絶縁板の表
面は、他部品であるモリブデンシート2及び半導体チッ
プ7と半田接合できるようにニッケルメッキ4が施され
ている。そして前記モリブデンシート2は熱膨張係数差
の大きい金属ベース(銅)1に銀ロウ付けにより強固に
固着されて、熱応力に対して耐久性のある構造となって
いる。As shown in the attached table, the silicon carbide insulating plate 5 has a thermal conductivity of 267 (W/m-K), which is about 10 times that of alumina, and has a thermal conductivity comparable to that of metals. The surface of this insulating plate is plated with nickel 4 so that it can be soldered to the molybdenum sheet 2 and semiconductor chip 7, which are other components. The molybdenum sheet 2 is firmly fixed to a metal base (copper) 1 having a large difference in coefficient of thermal expansion by silver brazing, and has a structure that is durable against thermal stress.
従ってこのように金属ベース1とモリブデンシート2を
銀ロウ付けして膨張係数の小さいモリブデンシートを強
固に固着しているため、他の材料間、即ちモリブデンシ
ートとシリコン絶縁板間では熱膨張係数差が小さくなり
、熱応力が発生しにくい構成となる。これによって他の
部品相互間を通常の高温半田(釦:錫:銀=95:3.
5:1.5)で半田付けしても熱応力による剥1lIl
!現象を受けにくく、耐久性を上げろことができる。Therefore, since the metal base 1 and the molybdenum sheet 2 are silver-brazed and the molybdenum sheet with a small expansion coefficient is firmly fixed, there is a difference in the thermal expansion coefficient between other materials, that is, between the molybdenum sheet and the silicon insulating plate. becomes small, resulting in a configuration in which thermal stress is less likely to occur. This allows other parts to be bonded together using normal high-temperature soldering (button: tin: silver = 95:3.
5:1.5) peeling due to thermal stress even when soldering
! It is less susceptible to phenomena and can increase durability.
25mm”)の場合の熱抵抗は、下記のようになる。The thermal resistance in the case of 25 mm'' is as follows.
0.86 0.2
Q、l116 0.6
0.86 0.4
0.86 1.6
0.86 0.6
上記より、絶縁板としてアルミナを使用した場合の総熱
抵抗
θ7.c11=0.3.+〇No+θ7kRf+θcu
= 1 、28 (deg/ W)SICでは、
θJ*Cu”θ7s1+θsrc+θMO+ Ocu
= 0 、54 [dag/ Wlとなり、通常のアル
ミナに比べて、約3倍の熱伝導の良い放熱構造を実現で
きる。0.86 0.2 Q, l116 0.6 0.86 0.4 0.86 1.6 0.86 0.6 From the above, the total thermal resistance θ7. when using alumina as the insulating plate. c11=0.3. +〇No+θ7kRf+θcu
= 1, 28 (deg/W) SIC, θJ*Cu” θ7s1+θsrc+θMO+ Ocu
= 0, 54 [dag/Wl, and a heat dissipation structure with approximately three times better heat conduction than normal alumina can be realized.
具体的に、半導体チップの損失が50Wの時には、銅ベ
ースに対するチップの温度T1は、(Tcu:銅ベース
下面の温度)
アルミナの場合
TJ= 1,28 X 50+TCLl=64 +Tc
u (度)シリコンカーバイトの場合
Ta=0.54 X 50 +Tcu= 27 +Tc
u (度)となる。Specifically, when the loss of the semiconductor chip is 50W, the temperature T1 of the chip with respect to the copper base is (Tcu: temperature of the bottom surface of the copper base) In the case of alumina, TJ = 1,28 x 50 + TCLl = 64 + Tc
u (degrees) For silicon carbide Ta = 0.54 x 50 +Tcu = 27 +Tc
It becomes u (degrees).
従って、アルミナとシリコンカーバイトでは、半導体の
ジャンクション温度を約37度下げられる。逆に言うと
、シリコンカーバイトの場合には、銅ベースの周囲温度
を37度高い所でも使用できるという効果がある。Therefore, with alumina and silicon carbide, the semiconductor junction temperature can be lowered by about 37 degrees. Conversely, silicon carbide has the advantage that it can be used in locations where the ambient temperature is 37 degrees higher than that of copper bases.
以下本発明の実施例によれば、
1)高熱伝導絶縁板を使用することにより、ヒートシン
クの構造(ヒートシンクの表面積)を小形化できるため
、省資源構造となる。According to the following embodiments of the present invention: 1) By using a highly thermally conductive insulating plate, the structure of the heat sink (surface area of the heat sink) can be made smaller, resulting in a resource-saving structure.
2)半導体チップと絶縁板の材質が、共にシリコンのた
め、半導体チップに熱応力が加わりにくく、耐久性が得
られ、信頼性の高い製品となる。2) Since both the semiconductor chip and the insulating plate are made of silicon, thermal stress is less likely to be applied to the semiconductor chip, resulting in a durable and highly reliable product.
3)半導体の直下に絶縁板を半田付けするため高電位部
が半導体チップ上と限られ、絶縁板以下をアースとする
ことができ、ケーシングが容易な構造となる。3) Since the insulating plate is soldered directly below the semiconductor, the high potential part is limited to the top of the semiconductor chip, and the area below the insulating plate can be grounded, resulting in an easy structure for casing.
4)銅ヒートシンクと半導体チップは、熱膨張係数が約
10倍違ってるが、この熱膨張係数差を、引張り強さの
大きい金属(モリブデンと銅)間で銀ロウ付けすること
で解消することができ、他の材料(半導体チップ、絶縁
板、モリブデン)間では、熱応力が発生しにくい構成と
することができる。このため、接合部(半田)の信頼性
を高められる効果がある。4) The coefficient of thermal expansion of a copper heat sink and a semiconductor chip is about 10 times different, but this difference in coefficient of thermal expansion can be resolved by silver brazing between metals with high tensile strength (molybdenum and copper). It is possible to create a structure in which thermal stress is less likely to occur between other materials (semiconductor chips, insulating plates, molybdenum). This has the effect of increasing the reliability of the joint (solder).
以上本発明によれば、小形で、信頼性の高い半導体装置
が得られる。As described above, according to the present invention, a small and highly reliable semiconductor device can be obtained.
図面は本発明半導体装置の一実施例を示すもので、第1
図は一部断面した側面図、第2図は第1図の要部拡大図
である。
1・・・ヒートシンク、2・・・モリブデンシート、3
・・・金ロウ、4・・・メッキ層、5・・・シリコン系
絶縁板、6・・・高温半田、7・・・半導体チップ。The drawings show one embodiment of the semiconductor device of the present invention.
The figure is a partially sectional side view, and FIG. 2 is an enlarged view of the main part of FIG. 1. 1... Heat sink, 2... Molybdenum sheet, 3
... Gold solder, 4... Plating layer, 5... Silicon-based insulating plate, 6... High-temperature solder, 7... Semiconductor chip.
Claims (1)
介して固着される半導体チップと、前記絶縁板と金属ベ
ース間に固着され、該両部材の熱膨張係数差により発生
する熱応力緩衝部材とからなる半導体装置において、前
記半導体チップはシリコン系の絶縁板を介してモリブデ
ンからなる熱応力緩衝部材に固着されていることを特徴
とした半導体装置。 2、特許請求の範囲第1項記載において、絶縁板はシリ
コンカーバイトからなることを特徴とした半導体装置。 3、特許請求の範囲第1項記載において、ヒートシンク
は銅ベースからなり、熱応力緩衝部材を構成するモリブ
デンと銀ロウ付けにより固着されていることを特徴とし
た半導体装置。[Scope of Claims] 1. A semiconductor chip is fixed on a metal base constituting a heat sink via an insulating plate, and a semiconductor chip is fixed between the insulating plate and the metal base, and is generated due to the difference in coefficient of thermal expansion between the two members. 1. A semiconductor device comprising a thermal stress buffering member made of molybdenum, wherein the semiconductor chip is fixed to the thermal stress buffering member made of molybdenum via a silicon-based insulating plate. 2. A semiconductor device according to claim 1, wherein the insulating plate is made of silicon carbide. 3. A semiconductor device according to claim 1, wherein the heat sink is made of a copper base and is fixed to molybdenum constituting the thermal stress buffering member by silver brazing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60220099A JPH063832B2 (en) | 1985-10-04 | 1985-10-04 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60220099A JPH063832B2 (en) | 1985-10-04 | 1985-10-04 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6281047A true JPS6281047A (en) | 1987-04-14 |
JPH063832B2 JPH063832B2 (en) | 1994-01-12 |
Family
ID=16745903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60220099A Expired - Lifetime JPH063832B2 (en) | 1985-10-04 | 1985-10-04 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH063832B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01185929A (en) * | 1988-01-20 | 1989-07-25 | Mitsubishi Electric Corp | Assembling of semiconductor device |
FR2646018A1 (en) * | 1989-04-12 | 1990-10-19 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
JPH08509844A (en) * | 1993-05-07 | 1996-10-15 | シーメンス アクチエンゲゼルシャフト | Power semiconductor device having buffer layer |
US6577687B2 (en) | 1998-12-23 | 2003-06-10 | Maxtor Corporation | Method for transmitting data over a data bus with minimized digital inter-symbol interference |
JP2005328087A (en) * | 1999-03-24 | 2005-11-24 | Mitsubishi Materials Corp | Power module substrate |
US9320178B2 (en) | 2009-04-02 | 2016-04-19 | Denso Corporation | Electronic control unit and method of manufacturing the same |
-
1985
- 1985-10-04 JP JP60220099A patent/JPH063832B2/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01185929A (en) * | 1988-01-20 | 1989-07-25 | Mitsubishi Electric Corp | Assembling of semiconductor device |
US5138439A (en) * | 1989-04-04 | 1992-08-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
FR2646018A1 (en) * | 1989-04-12 | 1990-10-19 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
JPH08509844A (en) * | 1993-05-07 | 1996-10-15 | シーメンス アクチエンゲゼルシャフト | Power semiconductor device having buffer layer |
US6577687B2 (en) | 1998-12-23 | 2003-06-10 | Maxtor Corporation | Method for transmitting data over a data bus with minimized digital inter-symbol interference |
JP2005328087A (en) * | 1999-03-24 | 2005-11-24 | Mitsubishi Materials Corp | Power module substrate |
US9320178B2 (en) | 2009-04-02 | 2016-04-19 | Denso Corporation | Electronic control unit and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH063832B2 (en) | 1994-01-12 |
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