JPH01185929A - Assembling of semiconductor device - Google Patents
Assembling of semiconductor deviceInfo
- Publication number
- JPH01185929A JPH01185929A JP1127588A JP1127588A JPH01185929A JP H01185929 A JPH01185929 A JP H01185929A JP 1127588 A JP1127588 A JP 1127588A JP 1127588 A JP1127588 A JP 1127588A JP H01185929 A JPH01185929 A JP H01185929A
- Authority
- JP
- Japan
- Prior art keywords
- electrode terminal
- semiconductor element
- jig
- plate
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 229910000679 solder Inorganic materials 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005476 soldering Methods 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 abstract description 42
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 8
- 239000001257 hydrogen Substances 0.000 abstract description 8
- 206010037660 Pyrexia Diseases 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の組立て方法に関し、特に、電極端
子上に半導体素子を半田付けする方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for assembling a semiconductor device, and particularly to a method for soldering a semiconductor element onto an electrode terminal.
従来、半導体素子が金属板を介して半田付けされかつア
ニール処理された電極端子と、この電極端子金支持する
金属ベース板とを有する半導体装置は、予め半導体素子
と金属板との高温半田による半田付けと、電極端子のア
ニール処理とをそれぞれ別工程によって施しておき、金
属ベース板。Conventionally, a semiconductor device has an electrode terminal to which a semiconductor element is soldered via a metal plate and is annealed, and a metal base plate supporting the electrode terminal metal. The attachment and annealing of the electrode terminals are performed in separate processes, respectively, and the metal base plate is assembled.
電極端子、半導体素子が半田付けされた金属板とを低温
半田を介して順次積み重ね、これらを加熱炉によって一
度に加熱することによって組立てられていた。これを第
６図ないし第９図によって説明する。第６図は半導体素
子と金属板とが半田付けされた状態を示す斜視図、第７
図は前記半導体素子が半田付けされている状態を示す断
面図、第８図および第９図は金属ペース板上に電極端子
および半導体素子を保持させた状態を示す斜視図と断面
図である。これらの図において、１は半導体素子、２は
金属板、３は前記半導体素子１を金属板２に固着させる
ための高温半田、４および５は半導体素子１を金属板２
に位置決めさせると共に、半田付けさせるための水素炉
（図示せず）に入れる下治具および上治具で、位置決め
用凹部４ａと透孔５ａとが形成されている。６は半導体
装置の基台となる金属ベース板、Ｔはこの金属ペース板
６を保持するベース付治具、８は前記ペース付治具７に
より金属ベース板６に対して位置決めされ、後述する絶
縁基板および電極端子を保持しかつ金属ベース板６に位
置決めするための位置決め板で、絶縁基板が挿入される
開口部８ａと、電極端子が嵌合される位置決め用孔８ｂ
とが形成されている。The electrode terminal and the metal plate to which the semiconductor element is soldered are sequentially stacked together using low-temperature solder, and assembled by heating them all at once in a heating furnace. This will be explained with reference to FIGS. 6 to 9. FIG. 6 is a perspective view showing a state in which a semiconductor element and a metal plate are soldered, and FIG.
The figure is a cross-sectional view showing the semiconductor element soldered, and FIGS. 8 and 9 are a perspective view and a cross-sectional view showing the electrode terminal and the semiconductor element held on the metal paste plate. In these figures, 1 is a semiconductor element, 2 is a metal plate, 3 is high-temperature solder for fixing the semiconductor element 1 to the metal plate 2, and 4 and 5 are the semiconductor element 1 and the metal plate 2.
A positioning recess 4a and a through hole 5a are formed by a lower jig and an upper jig that are placed in a hydrogen furnace (not shown) for positioning and soldering. Reference numeral 6 denotes a metal base plate serving as the base of the semiconductor device, T a jig with a base for holding the metal paste plate 6, and 8 a metal base plate 6 positioned with respect to the metal base plate 6 by the jig with paste plate 7; A positioning plate for holding the substrate and electrode terminals and positioning them on the metal base plate 6, which includes an opening 8a into which the insulating substrate is inserted and a positioning hole 8b into which the electrode terminals are fitted.
is formed.
９は前記半導体素子１が実装される電極端子で、この電
極端子９は予め別工程において水素炉によりアニール処
理されている。１０はこの電極端子９と前記金属ベース
板６とを絶縁する絶縁基板、１１は絶縁基板１０に前記
金属ベース板６および電極端子９を固着させるための低
温半田である。Reference numeral 9 denotes an electrode terminal on which the semiconductor element 1 is mounted, and this electrode terminal 9 has been previously annealed in a hydrogen furnace in a separate step. 10 is an insulating substrate for insulating the electrode terminal 9 and the metal base plate 6, and 11 is a low-temperature solder for fixing the metal base plate 6 and the electrode terminal 9 to the insulating substrate 10.
すなわち、金属ベース板６に対して固定された位置決め
板８の開口部８ａ内に低温半田１１および絶縁基板１０
を順次挿入し、その後絶縁基板１１上に低温半田１１を
載置させ、電極端子９を位置決め板８の位置決め用孔８
ｂに嵌合させることによって、金属ベース板６に対して
絶縁基板１０および電極端子９が保持されかつ位置決め
されることになる。That is, the low temperature solder 11 and the insulating substrate 10 are placed in the opening 8a of the positioning plate 8 fixed to the metal base plate 6.
are sequentially inserted, then low temperature solder 11 is placed on the insulating substrate 11, and the electrode terminal 9 is inserted into the positioning hole 8 of the positioning plate 8.
By fitting into the metal base plate 6, the insulating substrate 10 and the electrode terminal 9 are held and positioned with respect to the metal base plate 6.
次に組立て方法について説明する。先ず、第７図に示す
ように、下治具４の凹部４ａに金属板２を挿入させ、下
治具４と上治具５とを重ねた状態で、上治具５の透孔５
ａ内に高温半田３および半導体素子１を順次挿入させる
。そして、上、下治具をこのままの状態で水素炉（図示
せず）内に入れ加熱し、金属板２と半導体素子１とを半
田付けさせる。冷却後、上、下治具を開き、半導体素子
１を下治具４から取出す。次いで、第８図および第９図
に示すように、ペース付治具７上に金属ベース板６およ
び位置決め板８を位置決めし、保持させる。そして、こ
の位置決め板８によって前記金属ペース板６上に低温半
田１１．絶縁基板１０および電極端子９を保持させ、さ
らにこの電極端子９上に、前工程で半導体素子１が固着
された金属板２ｔ−低温半田１２を介して載置させる。Next, the assembly method will be explained. First, as shown in FIG. 7, the metal plate 2 is inserted into the recess 4a of the lower jig 4, and with the lower jig 4 and the upper jig 5 overlapped, the through hole 5 of the upper jig 5 is inserted.
High-temperature solder 3 and semiconductor element 1 are sequentially inserted into a. Then, the upper and lower jigs are placed in a hydrogen furnace (not shown) and heated to solder the metal plate 2 and the semiconductor element 1. After cooling, the upper and lower jigs are opened and the semiconductor element 1 is taken out from the lower jig 4. Next, as shown in FIGS. 8 and 9, the metal base plate 6 and the positioning plate 8 are positioned and held on the pasting jig 7. Then, the low temperature solder 11. is applied onto the metal paste plate 6 by the positioning plate 8. The insulating substrate 10 and the electrode terminal 9 are held, and the semiconductor element 1 is placed on the electrode terminal 9 via the metal plate 2t to which the semiconductor element 1 was fixed in the previous step and the low-temperature solder 12.
次に加熱炉（図示せず）内でベース付治具Ｔごと加熱し
、各低温半田１１および１２を溶融させ半田付けを行な
う。なお、この加熱炉は前記水素炉よシ加熱温度の低い
ものが使用されるため、半導体素子１と金属板２とを固
着した高温半田３が溶融されるようなことはない。この
ようにして各部材が半田付けされ、組立てられることに
なる。Next, the base-equipped jig T is heated in a heating furnace (not shown) to melt the low-temperature solders 11 and 12 and perform soldering. Note that since this heating furnace has a lower heating temperature than the hydrogen furnace, the high temperature solder 3 that fixed the semiconductor element 1 and the metal plate 2 will not be melted. In this way, each member is soldered and assembled.
しかるに、このような半導体装置の組立て方法では、半
導体素子１と金属板２との半田付けと、電極端子９のア
ニール処理とがそれぞれ別工程によって行なわれていた
ため、組立て工数が多くなる。また、半導体素子１およ
び金属板２は電極端子９に対して位置決めされないので
、半導体素子１の位置ずれにより次工程の自動ワイヤー
ボンド装置が半導体素子１の位置を検出できず、その稼
動率が低下するため、加熱炉の出口で半導体素子１およ
び金属板２の位置全修正する必要がおった。However, in this method of assembling a semiconductor device, the soldering of the semiconductor element 1 and the metal plate 2 and the annealing of the electrode terminals 9 are performed in separate steps, which increases the number of assembly steps. Furthermore, since the semiconductor element 1 and the metal plate 2 are not positioned with respect to the electrode terminals 9, the automatic wire bonding equipment in the next process cannot detect the position of the semiconductor element 1 due to the positional deviation of the semiconductor element 1, and its operating rate decreases. Therefore, it was necessary to completely correct the positions of the semiconductor element 1 and the metal plate 2 at the exit of the heating furnace.
本発明に係る半導体装置の組立て方法は、電極端子に対
して位置決めされるガイド板により電極端子上に半田を
介して半導体素子を保持させ、この電極端子を加熱炉で
加熱することによって電極端子に半田付けとアニール処
理とを一度に施し、しかる後、この電極端子を前記半田
より融点の低い半田によってベース板に取付けるもので
ある。In the method for assembling a semiconductor device according to the present invention, a guide plate positioned with respect to the electrode terminal holds the semiconductor element on the electrode terminal through solder, and the electrode terminal is heated in a heating furnace to form the semiconductor element into the electrode terminal. Soldering and annealing are performed at the same time, and then the electrode terminal is attached to the base plate using solder having a lower melting point than the solder.
半導体素子はガイド板によって位置決め保持され、この
半導体素子の半田付けと電極端子のアニール処理が同時
に行なわれる。The semiconductor element is positioned and held by the guide plate, and soldering of the semiconductor element and annealing of the electrode terminals are performed simultaneously.
以下、本発明の実施例を図により詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明に係るガイド板を使用して電極端子上に
半導体素子を実装する手順を説明するための分解斜視図
、第２図は電極端子をアニール処理する状態を示す断面
図、第３図は半導体素子が実装された電極端子の斜視図
、第４図および第５図は金属ペース板上に電極端子が保
持された状態を示す斜視図と断面図である。これらの図
において前記従来例で説明したものと同一もしくは同等
部材については同一符号を付し、ここにおいて詳細な説
明は省略する。これらの図において、２１は電極端子９
、後述する中治具およびガイド治具を支持するパレット
で、電極端子９の位置決め用透孔９ａを貫通する位置決
めピン２１ａが突設されている。２２は金属板２を位置
決めするための空治具で、前記パレット２１の位置決め
ピン１７ｍが貫通する位置決め穴２２＆と、金属板２お
よび高温半田２３が挿入される穴部２２ｂとが設けられ
ている。２４は半導体素子１を位置決めするためのガイ
ド治具で、前記パレット２１の位置決めピン１７ａが貫
通する位置決め穴２４ａと、半導体素子１および高温半
田３が挿入される穴部２４ｂとが設けられている。すな
わち、パレット２１．空治具２２およびガイド治具２４
によって、半導体素子１ｔ−電極端子ｓ上に保持しかつ
電極端子９に対して位置決めするガイド板を構成するこ
とになる。FIG. 1 is an exploded perspective view for explaining the procedure for mounting a semiconductor element on an electrode terminal using a guide plate according to the present invention, FIG. 2 is a sectional view showing a state in which the electrode terminal is annealed, FIG. 3 is a perspective view of an electrode terminal on which a semiconductor element is mounted, and FIGS. 4 and 5 are a perspective view and a sectional view showing the electrode terminal held on a metal paste plate. In these figures, the same or equivalent members as those explained in the conventional example are given the same reference numerals, and detailed explanation will be omitted here. In these figures, 21 is the electrode terminal 9
, is a pallet that supports a middle jig and a guide jig, which will be described later, and is provided with a protruding positioning pin 21a passing through a positioning hole 9a of the electrode terminal 9. 22 is an empty jig for positioning the metal plate 2, and is provided with a positioning hole 22& through which the positioning pin 17m of the pallet 21 passes, and a hole 22b into which the metal plate 2 and high-temperature solder 23 are inserted. . 24 is a guide jig for positioning the semiconductor element 1, and is provided with a positioning hole 24a through which the positioning pin 17a of the pallet 21 passes, and a hole 24b into which the semiconductor element 1 and high-temperature solder 3 are inserted. . That is, pallet 21. Empty jig 22 and guide jig 24
This constitutes a guide plate that holds the semiconductor element 1t and the electrode terminal s and positions it with respect to the electrode terminal 9.
次に、このように構成されたガイド板を使って半導体装
置を組立てる方法を説明する。Next, a method for assembling a semiconductor device using the guide plate configured as described above will be explained.
先ず、第１図および第２図に示すように、パレット２１
上に電極端子９と空治具２２とを順次取付ける。この際
、電極端子９の所定位置と空治具２２の穴部２２ｍが対
応することになる。そして、前記穴部２２ｂ内に高温半
田２３と金属板２とを挿入させ、さらに空治具２２の上
側にガイド治具２４を取付ける。次にガイド治具２４の
穴部２４ｂ内に高温半田３と半導体素子１とを挿入させ
る。そして、この状態でパレット２１ごと水素炉（図示
せず）内で加熱し、各高温半田３．２３に溶融させると
共に、電極端子９にアニール処理を施す。すなわち、半
導体素子１．金属板２および電極端子９の半田付けと、
電極端子９のアニール処理が同一水素炉内で同時に行な
われることになる。First, as shown in FIGS. 1 and 2, the pallet 21
The electrode terminal 9 and the empty jig 22 are sequentially attached on top. At this time, the predetermined position of the electrode terminal 9 corresponds to the hole 22m of the empty jig 22. Then, the high temperature solder 23 and the metal plate 2 are inserted into the hole 22b, and the guide jig 24 is attached above the empty jig 22. Next, the high temperature solder 3 and the semiconductor element 1 are inserted into the hole 24b of the guide jig 24. Then, in this state, the pallet 21 is heated in a hydrogen furnace (not shown) to melt each high-temperature solder 3 and 23, and the electrode terminal 9 is annealed. That is, semiconductor element 1. Soldering the metal plate 2 and the electrode terminal 9,
The annealing treatment of the electrode terminals 9 will be performed simultaneously in the same hydrogen furnace.
冷却後、第３図に示すように、ガイド治具２４および空
治具２２を取外し、パレット２１から電極端子９を取外
す。そして、この′ｔＩｔ極端子９を従来例と同様にし
て第４図および第５図に示すように、金属ベース板６に
固着させる。すなわち、予めペース付滑具Ｔ上に金属ペ
ース板６ｔ−保持させると共に位置決め板８７！Ｉ−取
付けておき、この位置決め板８に低温半田１１および絶
縁基板１０を挿入させておく。そして、この位置決め板
８に電極端子９を取付けた状態で全体を加熱炉（図示せ
ず）内で加熱することによって、金属ベース板６．絶縁
基板１０および電極端子９が各々半田付けされることに
なる。このようにして組立てることができる。After cooling, the guide jig 24 and empty jig 22 are removed, and the electrode terminal 9 is removed from the pallet 21, as shown in FIG. Then, this 'tIt pole terminal 9 is fixed to the metal base plate 6 as shown in FIGS. 4 and 5 in the same manner as in the conventional example. That is, the metal pace plate 6t is held on the paced slide T in advance, and the positioning plate 87 is also held. The low temperature solder 11 and the insulating board 10 are inserted into the positioning plate 8. Then, by heating the entire positioning plate 8 with the electrode terminal 9 attached thereto in a heating furnace (not shown), the metal base plate 6. The insulating substrate 10 and the electrode terminals 9 are each soldered. It can be assembled in this way.
なお、アニール処理は、従来、高温半田を溶融させるた
めの水素炉と同様の水素炉によって施されていたため、
本発明のようにアニール処理と半田付けを同時に行なっ
ても加熱条件は等しく、品質が低下するようなことはな
ｉｏ
したがって、半導体素子１はパレット２１．空治具２２
およびガイド治具２４によって位置決めされ、この半導
体素子１０半出付けと電極端子９のアニール処理が同時
に行なわれることになる。Note that the annealing process was conventionally performed in a hydrogen furnace similar to the one used to melt high-temperature solder.
Even if annealing and soldering are performed at the same time as in the present invention, the heating conditions are the same and the quality will not deteriorate. Empty jig 22
Then, the semiconductor element 10 is positioned by the guide jig 24, and the half-extrusion of the semiconductor element 10 and the annealing treatment of the electrode terminal 9 are performed at the same time.
また、上記実施例では電極端子９が１個の半導体装置全
組立てる例を示したが、電極端子９ｔ−複数使用するも
のでも同等の効果が得られる。Further, in the above embodiment, an example was shown in which the entire semiconductor device was assembled using one electrode terminal 9, but the same effect can be obtained even if a plurality of electrode terminals 9t are used.
以上説明したように本発明によれば、電極端子に対して
位置決めされるガイド板により電極端子上に半田を介し
て半導体素子を保持させ、この電極端子を加熱炉で加熱
することによって電極端子に半田付けとアニール処理と
を一度に施し、しかる後、この電極端子を前記半田より
融点の低い半田によってベース板に取付けるため、半導
体素子の位置決め精度が向上するから、高品質な半導体
装置が得られ、しかも次工程で使用される自動ワイヤボ
ンド装置の稼動率を向上させることができ次工程の自動
化が容易になる。また、半導体素子の半田付けと電極端
子のアニール処理が同時に行なわれるから、組立て工数
を削減させることができる。As explained above, according to the present invention, the semiconductor element is held on the electrode terminal via solder by the guide plate positioned with respect to the electrode terminal, and the semiconductor element is held on the electrode terminal by heating the electrode terminal in a heating furnace. Soldering and annealing are performed at the same time, and then the electrode terminals are attached to the base plate with solder having a lower melting point than the solder, so the positioning accuracy of the semiconductor element is improved, and a high quality semiconductor device can be obtained. Moreover, the operating rate of the automatic wire bonding equipment used in the next process can be improved, and the automation of the next process can be facilitated. Furthermore, since the soldering of the semiconductor elements and the annealing of the electrode terminals are performed at the same time, the number of assembly steps can be reduced.
第１図は本発明に係るガイド板を使用して電極端子上に
半導体素子を実装する手順を説明するための分解斜視図
、第２図は電極端子を７ニール処理する状態を示す断面
図、第３図は半導体素子が実装された電極端子の斜視図
、第４図および第５図は金属ペース板上に電極端子が保
持された状態を示す斜視図と断面図、第６図は半導体素
子と金属板とが半田付けされた状態を示す斜視図、第７
図は前記半導体素子が半田付けされている状態を示す断
面図、第８図および第９図は金属ベース板上に電極趨子
および半導体素子を保持させた状態を示す斜視図と断面
図である。
１・・・・半導体素子、３・・・・高温半田、６・・・
・金属ペース板、９・・・・電極端子、１１・・・・低
温半田、２１・・・・パレット、２２・・・・中油具、
２３・・・・高温半田、２４・・・・ガイド治具。FIG. 1 is an exploded perspective view for explaining the procedure for mounting a semiconductor element on an electrode terminal using the guide plate according to the present invention, FIG. FIG. 3 is a perspective view of an electrode terminal with a semiconductor element mounted thereon, FIGS. 4 and 5 are perspective views and cross-sectional views showing the electrode terminal held on a metal paste plate, and FIG. 6 is a perspective view of the electrode terminal on which a semiconductor element is mounted. and a metal plate are soldered together, a seventh perspective view.
The figure is a sectional view showing a state in which the semiconductor element is soldered, and FIGS. 8 and 9 are a perspective view and a sectional view showing a state in which an electrode thread and a semiconductor element are held on a metal base plate. . 1... Semiconductor element, 3... High temperature solder, 6...
・Metal paste plate, 9... Electrode terminal, 11... Low temperature solder, 21... Pallet, 22... Medium oil tool,
23...High temperature solder, 24...Guide jig.
Claims (1)
端子上に半田を介して半導体素子を保持させ、この電極
端子を加熱炉で加熱することによって電極端子に半田付
けとアニール処理とを一度に施し、しかる後、この電極
端子を前記半田より融点の低い半田によってベース板に
取付けることを特徴とする半導体装置の組立て方法。A semiconductor element is held on the electrode terminal via solder by a guide plate positioned with respect to the electrode terminal, and the electrode terminal is heated in a heating furnace to perform soldering and annealing treatment on the electrode terminal at the same time, A method for assembling a semiconductor device, characterized in that the electrode terminal is then attached to a base plate using solder having a lower melting point than the solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1127588A JPH01185929A (en) | 1988-01-20 | 1988-01-20 | Assembling of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1127588A JPH01185929A (en) | 1988-01-20 | 1988-01-20 | Assembling of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01185929A true JPH01185929A (en) | 1989-07-25 |
Family
ID=11773432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1127588A Pending JPH01185929A (en) | 1988-01-20 | 1988-01-20 | Assembling of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01185929A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009088008A (en) * | 2007-09-27 | 2009-04-23 | Mitsubishi Electric Corp | Tool and method for manufacturing semiconductor device |
| JP2012142640A (en) * | 2012-05-01 | 2012-07-26 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5246769A (en) * | 1975-10-11 | 1977-04-13 | Hitachi Ltd | Method of attaching pellet and jig used for same |
| JPS6281047A (en) * | 1985-10-04 | 1987-04-14 | Hitachi Ltd | Semiconductor device |
-
1988
- 1988-01-20 JP JP1127588A patent/JPH01185929A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5246769A (en) * | 1975-10-11 | 1977-04-13 | Hitachi Ltd | Method of attaching pellet and jig used for same |
| JPS6281047A (en) * | 1985-10-04 | 1987-04-14 | Hitachi Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009088008A (en) * | 2007-09-27 | 2009-04-23 | Mitsubishi Electric Corp | Tool and method for manufacturing semiconductor device |
| JP2012142640A (en) * | 2012-05-01 | 2012-07-26 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
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