JPH08148623A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08148623A JPH08148623A JP6289661A JP28966194A JPH08148623A JP H08148623 A JPH08148623 A JP H08148623A JP 6289661 A JP6289661 A JP 6289661A JP 28966194 A JP28966194 A JP 28966194A JP H08148623 A JPH08148623 A JP H08148623A
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- lead
- semiconductor chip
- frame
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップに接続さ
れた３本のリード端子を備える、トランジスタ又はダイ
オード等のような半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a transistor or a diode having three lead terminals connected to a semiconductor chip.
【０００２】[0002]
【従来の技術】一般に、半導体装置は、例えば、半導体
チップをエポキシ樹脂等からなるモールド部により覆
い、且つ、上記半導体チップに接続された３本のリード
端子がモールド部の両側面からそれぞれ突出する型の半
導体装置を例にとると、次のような構造を有する。2. Description of the Related Art Generally, in a semiconductor device, for example, a semiconductor chip is covered with a mold portion made of epoxy resin or the like, and three lead terminals connected to the semiconductor chip are projected from both side surfaces of the mold portion. Taking a semiconductor device of the type as an example, it has the following structure.
【０００３】すなわち、この半導体装置は、図７に示す
ように、先端にアイランド部３１が設けられた第１のリ
ード端子３２と、第１リード端子３２に対向配置された
第２リード端子３３および第３リード端子３４と、アイ
ランド部３１上にダイボンディングされた半導体チップ
３５と、この半導体チップ３５上面に設けられた２つの
電極部３６と、これら電極部３６と第２および第３リー
ド端子部３３、３４との間をワイヤボンディングにて電
気的に接続した金線等の細い金属線３７と、半導体チッ
プ３５の部分を覆うエポキシ樹脂等からなるモールド部
３８とからなる構造を有している。That is, in this semiconductor device, as shown in FIG. 7, a first lead terminal 32 having an island portion 31 at its tip, a second lead terminal 33 arranged opposite to the first lead terminal 32, and The third lead terminal 34, the semiconductor chip 35 die-bonded onto the island portion 31, two electrode portions 36 provided on the upper surface of the semiconductor chip 35, the electrode portion 36, and the second and third lead terminal portions. It has a structure including a thin metal wire 37 such as a gold wire that is electrically connected between 33 and 34 by wire bonding, and a mold portion 38 that covers the semiconductor chip 35 and is made of an epoxy resin or the like. .
【０００４】[0004]
【発明が解決しようとする課題】しかし、この半導体装
置は、金線等の高価な細い金属線３７によるワイヤボン
ディングを用いているために、製造コストが大幅にアッ
プするばかりか、前記細い金属線３７に断線が発生する
ことで、大電流用には適しない等の問題があった。However, since this semiconductor device uses wire bonding with an expensive thin metal wire 37 such as a gold wire, not only the manufacturing cost is greatly increased, but also the thin metal wire is used. Since the wire breakage occurs at 37, there is a problem that it is not suitable for a large current.
【０００５】これを解決するために、特開昭４７−３７
０７４号公報では、細い金属線３７によるワイヤボンデ
ィングを用いない、３端子型の半導体装置の構造が掲載
されている。この半導体装置は、図８（ａ）に示すよう
に、まず、第２リード端子３９及び第３リード端子４０
を、一旦、略垂直方向に折り曲げて直立させ、さらに、
図８（ｂ）に示すように、この直立した部分のそれぞれ
の先端を、それぞれ根元から第１リード端子４１に向け
て倒すことにより、この第１リード端子４１上にダイボ
ンディングされた半導体チップ４２の両電極部４３にそ
れぞれ重ねるようにして接続させるといった構造であ
る。In order to solve this, Japanese Patent Laid-Open No. 47-37
Japanese Patent No. 074 discloses a structure of a three-terminal type semiconductor device which does not use wire bonding with a thin metal wire 37. In this semiconductor device, as shown in FIG. 8A, first, a second lead terminal 39 and a third lead terminal 40 are first formed.
, Once bent in a substantially vertical direction to stand upright,
As shown in FIG. 8B, the tip of each of the upright portions is tilted from the root toward the first lead terminal 41, so that the semiconductor chip 42 die-bonded onto the first lead terminal 41. The structure is such that they are connected so as to be overlapped on both of the electrode portions 43.
【０００６】しかし、この半導体装置は、以下のような
問題があった。すなわち、第２および第３リード端子３
９、４０を、両電極部４３に対してそれぞれ押しつける
ように折曲げているため、電極部４３に大きな押圧力が
かかりやすく、仮に一定以上の大きさの押圧力がかかっ
た場合には、当該電極部４３を傷つけたり、半導体チッ
プ４２の位置ずれを生じさせたりしてしまう。また、上
記問題を防ぐために電極部４３に対する押圧力を小さく
した場合には、第２および／または第３リード端子３
８、３９は、この折曲げ直後のスプリングバックによ
り、電極部４３から離間してしまう可能性がある。However, this semiconductor device has the following problems. That is, the second and third lead terminals 3
Since 9 and 40 are bent so as to be pressed against both electrode parts 43, a large pressing force is easily applied to the electrode part 43, and if a pressing force of a certain magnitude or more is applied, The electrode part 43 may be damaged or the semiconductor chip 42 may be displaced. If the pressing force on the electrode portion 43 is reduced to prevent the above problem, the second and / or third lead terminals 3
The springs 8 and 39 immediately after bending may be separated from the electrode portion 43.
【０００７】このような不具合を防ぐためには、上記押
圧力を高精度に制御しつつ折曲げ加工を行う必要があ
り、非常に加工性が悪かった。本発明は、以上のような
状況下で考え出されたもので、量産性に優れ、且つ、信
頼性の高い半導体装置を提供することを目的とする。In order to prevent such a problem, it is necessary to perform bending while controlling the pressing force with high precision, and the workability was extremely poor. The present invention has been devised under the above circumstances, and an object of the present invention is to provide a semiconductor device having excellent mass productivity and high reliability.
【０００８】[0008]
【課題を解決するための手段】この課題を解決するため
に本発明は、上面に２つの電極部を設けた半導体チップ
と、該半導体チップの下面に接続した第１のリード端子
と、前記２つの電極部の一方に接続した第２のリード端
子と、前記２つの電極部の他方に接続した第３のリード
端子と、前記半導体チップおよび前記第１乃至第３のリ
ード端子の一部を覆うモールド部と、を備えてなる半導
体装置であって、前記電極部と第２および第３のリード
端子とを、フレームを介して各々接続していることを特
徴とする半導体装置を提供するものである。In order to solve this problem, the present invention provides a semiconductor chip having an upper surface provided with two electrode portions, a first lead terminal connected to the lower surface of the semiconductor chip, and the above-mentioned 2 A second lead terminal connected to one of the two electrode portions, a third lead terminal connected to the other of the two electrode portions, a part of the semiconductor chip and the first to third lead terminals. A semiconductor device comprising: a mold part, wherein the electrode part and the second and third lead terminals are connected to each other via a frame. is there.
【０００９】[0009]
【発明の作用及び効果】本発明の半導体装置によれば、
２つの電極部と第２および第３のリード端子とをそれぞ
れフレームを介して接続しているので、該フレームをそ
の一方端部を電極部上に、その他方端部を第２および第
３リード端子上に位置させて載置して接続することが可
能となるため、半導体チップに対してリード端子の載置
等に要する以外の押圧力を付加する必要なく上記接続が
可能となる。このため、第１リード端子上における半導
体チップの位置ずれを発生させたり、電極部を傷つけた
りすることなく、容易に上記接続をなし得る。According to the semiconductor device of the present invention,
Since the two electrode portions and the second and third lead terminals are connected to each other via the frame, one end portion of the frame is on the electrode portion and the other end portion is the second and third lead terminals. Since it is possible to place and place the terminals on the terminals for connection, it is possible to perform the above-mentioned connection without applying a pressing force other than that required for mounting the lead terminals to the semiconductor chip. For this reason, the above-mentioned connection can be easily made without causing displacement of the semiconductor chip on the first lead terminal or damaging the electrode portion.
【００１０】また、２つの電極部と第２および第３のリ
ード端子とを、フレームを介して別個に接続することが
できるので、仮に一方の剛性体が変形した状態で接続し
たとしても、他方のフレームの接続箇所を変更する等し
て、フレームどうしの電気的接続に注意をはらいながら
の接続が可能となる。このため、リード端子どうしの電
気的ショート等の不良を低減でき、信頼性を著しく向上
できる。Further, since the two electrode portions and the second and third lead terminals can be separately connected via the frame, even if one rigid body is connected in a deformed state, the other It is possible to connect the frames while paying attention to the electrical connection between the frames by changing the connection points of the frames. Therefore, defects such as electrical shorts between the lead terminals can be reduced, and the reliability can be significantly improved.
【００１１】[0011]
【実施例】以下、本発明の一実施例を、半導体装置とし
て三端子型のダイオードを例にとり、図１乃至図３を参
照しつつ説明するが、本発明がこれらに限定されること
はない。図１は、三端子型のダイオードを示す要部断面
図であり、また、図２は、三端子型のダイオードを示す
部分切欠き平面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 3 by taking a three-terminal type diode as an example of a semiconductor device, but the present invention is not limited to these. . FIG. 1 is a cross-sectional view of an essential part showing a three-terminal type diode, and FIG. 2 is a partially cutaway plan view showing a three-terminal type diode.
【００１２】これらの図の双方を参照しつつ説明する
と、このダイオードは、上面に突起状の電極部１、２を
設けた半導体チップ３と、この半導体チップ３の下面に
電気的に接続した第１リード端子４と、この第１リード
端子４に対向配置した第２リード端子５および第３リー
ド端子６と、電極部１と第２リード端子５との間および
電極部２と第３リード端子６との間を電気的に接続させ
る銅からなるフレーム７、８と、半導体チップ３および
その周囲を覆うエポキシ樹脂からなるモールド部９とか
らなるものである（図１においては電極部１、フレーム
７および第２リード端子５を省略）。Explaining with reference to both of these figures, this diode has a semiconductor chip 3 having projecting electrode portions 1 and 2 on its upper surface, and a semiconductor chip 3 electrically connected to the lower surface of this semiconductor chip 3. 1 lead terminal 4, 2nd lead terminal 5 and 3rd lead terminal 6 arranged facing this 1st lead terminal 4, between electrode part 1 and 2nd lead terminal 5, and between electrode part 2 and 3rd lead terminal 6, frames 7 and 8 made of copper for electrically connecting the semiconductor chip 3 and 6 and a mold part 9 made of epoxy resin for covering the semiconductor chip 3 and its periphery (in FIG. 1, the electrode part 1 and the frame). 7 and the second lead terminal 5 are omitted).
【００１３】上記フレーム７、８は、０．５ｍｍ程度の
厚さを有する板状体（図示せず）を、従来から用いられ
る打ち抜き加工により、図２に示すような、平面視先端
幅太の形状に加工し、さらに、従来から用いられる曲げ
加工により、図１に示すような、断面視階段形状に塑性
変形加工したものである。この形状において、曲げ角度
はそれぞれ１２０度程度となっている。また、フレーム
７は、その一方の先端部が電極部１に、その他方の先端
部が第２リード端子５に、それぞれ半田（図示せず）を
介して電気的に接続されている。さらに、フレーム８
は、その一方の先端部が電極部２に、その他方の先端部
が第３リード端子６に、それぞれ半田（図示せず）を介
して接続されている。The frames 7 and 8 have a wide tip in plan view as shown in FIG. 2 by punching a plate-like body (not shown) having a thickness of about 0.5 mm, which is conventionally used. It is processed into a shape and is further plastically deformed into a stepped shape in a sectional view as shown in FIG. 1 by a conventionally used bending process. In this shape, the bending angle is about 120 degrees. Further, one end of the frame 7 is electrically connected to the electrode portion 1 and the other end thereof is electrically connected to the second lead terminal 5 via solder (not shown). Furthermore, frame 8
Has one end connected to the electrode portion 2 and the other end connected to the third lead terminal 6 via solder (not shown), respectively.
【００１４】上記モールド部９には、その両側面の一方
から第１リード端子４が突出し、他方から第２及び第３
リード端子５、６が突出している。上記リード端子５、
６は、鉄からなるものであり、また、電極部１、２は、
銀等からなるものである。このような構造を有するダイ
オードにおいては、電極部１と第２リード端子５とをお
よび電極部２と第３リード端子６とを、それぞれフレー
ム７、８を介して接続しているので、該フレーム７、８
をその一方端部を電極部１、２上に載置し、その他方端
部を第２リード端子５上および第３リード端子６上に載
置するようにして接続することが可能となるため、半導
体チップ３に対して位置合わせや保持に要する以外の押
圧力を付加する必要がなく上記接続が可能となる。この
ため、第１リード端子４上における半導体チップ３の位
置ずれを発生させたり、電極部１、２を傷つけるたりす
ることなく、容易に上記接続をなし得る。The first lead terminal 4 projects from one of both side surfaces of the mold portion 9 and the second and third lead terminals 4 extend from the other.
The lead terminals 5 and 6 are protruding. The lead terminal 5,
6 is made of iron, and the electrode parts 1 and 2 are
It is made of silver or the like. In the diode having such a structure, the electrode portion 1 and the second lead terminal 5 and the electrode portion 2 and the third lead terminal 6 are connected to each other through the frames 7 and 8, respectively. 7, 8
Since it is possible to connect the one end part on the electrode parts 1 and 2 and the other end part on the second lead terminal 5 and the third lead terminal 6, The above connection is possible without the need to apply a pressing force to the semiconductor chip 3 other than that required for alignment and holding. Therefore, the above connection can be easily made without causing the positional displacement of the semiconductor chip 3 on the first lead terminal 4 or damaging the electrode portions 1 and 2.
【００１５】また、２つの電極部１、２と第２および第
３リード端子５、６とを、フレーム７、８を介して別個
に接続することができるので、例えば、一方のフレーム
７を図３に示すように、第３リード端子６方向に近づい
た状態で接続したとしても、他方のフレーム８の接続箇
所や接続状態を変更する等して、フレーム７、８どうし
の電気的接続に注意をはらいながらの接続が可能とな
る。このため、第２および第３リード端子５、６どうし
の電気的ショート等の不良を低減でき、信頼性を著しく
向上できる。Further, since the two electrode portions 1 and 2 and the second and third lead terminals 5 and 6 can be separately connected via the frames 7 and 8, for example, one frame 7 is illustrated. As shown in 3, even if the connection is made in the direction close to the direction of the third lead terminal 6, be careful of the electrical connection between the frames 7 and 8 by changing the connection location or connection state of the other frame 8. It is possible to connect while observing. Therefore, defects such as an electrical short circuit between the second and third lead terminals 5 and 6 can be reduced, and the reliability can be remarkably improved.
【００１６】このようなダイオードは、例えば、図４に
示す如く、次のような方法で製造される。図４におい
て、リードフレーム１０は、鉄からなる金属板（図示せ
ず）より打ち抜いた長尺帯状のものである。また、この
リードフレーム１０の長さ方向に沿う左右両縁部には、
サイドフレーム１１、１２が形成されている。Such a diode is manufactured by the following method, for example, as shown in FIG. In FIG. 4, the lead frame 10 is in the form of a long strip punched from a metal plate (not shown) made of iron. In addition, on both left and right edges along the length direction of the lead frame 10,
Side frames 11 and 12 are formed.
【００１７】また、前記両サイドフレーム１１、１２の
うち一方のサイドフレーム１１には、第１リード端子部
１３が内向きに突出するように一体的に形成されてい
る。他方のサイドフレーム１２には、第２リード端子部
１４および第３リード端子部１５が内側に突出するよう
に形成されている。第１リード端子部１３と第２及び第
３リード端子部１４、１５とは、それぞれの先端面が互
いに向き合うように配置されている。A first lead terminal portion 13 is integrally formed on one of the side frames 11 and 12 so as to project inward. The second lead terminal portion 14 and the third lead terminal portion 15 are formed on the other side frame 12 so as to project inward. The first lead terminal portion 13 and the second and third lead terminal portions 14 and 15 are arranged so that their respective tip surfaces face each other.
【００１８】このようなリードフレーム１０を用いて、
ダイオードを製造する。まず、リードフレーム１０をそ
の長手方向（図４におけるＡ方向）に沿って間欠的に移
送し、その移送する途次において、第１リード端子部１
３の先端部上面に、溶融状の半田を塗布した後に、半導
体チップ３を搭載する。その後に、上記半導体チップ３
の各電極部１、２上、第２及び第３リード端子部１４、
１５の先端部上にそれぞれ適量の溶融状の半田をそれぞ
れ塗布する。Using such a lead frame 10,
Manufacture a diode. First, the lead frame 10 is intermittently transferred along the longitudinal direction (direction A in FIG. 4), and during the transfer, the first lead terminal portion 1
After the molten solder is applied to the upper surface of the tip of the semiconductor chip 3, the semiconductor chip 3 is mounted. After that, the semiconductor chip 3
On each of the electrode portions 1 and 2, the second and third lead terminal portions 14,
Appropriate amounts of molten solder are applied onto the tip portions of 15 respectively.
【００１９】次いで、フレーム７を、その一方の先端部
が半田を塗布した電極部１上に、その他方の先端部がや
はり半田を塗布した第２リード端子部１４の先端部上に
位置するように載置し、半田による融着により接続させ
る。これと同様に、フレーム８を、その一方の先端部が
電極部２上に、その他方の先端部が第３リード端子部１
５の先端部上に接続させる。Then, one end of the frame 7 is positioned on the electrode portion 1 coated with solder, and the other end is positioned on the tip portion of the second lead terminal portion 14 also coated with solder. Then, it is connected by fusion with solder. Similarly, one end of the frame 8 is on the electrode portion 2 and the other end is the third lead terminal portion 1
Connect on top of 5.
【００２０】ここで、上記フレーム７、８の供給方法
は、例えば、予め所定形状に曲げ加工された複数のフレ
ーム７、８を異なるパーツフィーダにそれぞれ投入し、
各パーツフィーダからフレームを一旦１列状に排出し、
さらに、この排出されたフレームを個々に吸着コレット
等により吸着保持した状態で、上記所定位置に移送する
といったものが適用できる。また、フレーム７、８の接
続時には、従来から用いられる画像処理装置で、該フレ
ーム７、８の接続状態を認識することにより、１回の移
送毎にフレーム７、８の位置を設定し直すことも可能で
ある。Here, in the method of supplying the frames 7 and 8, for example, a plurality of frames 7 and 8 which have been bent into a predetermined shape in advance are respectively put into different parts feeders,
Discharge the frame from each parts feeder once in a row,
Further, it is possible to apply a method in which the discharged frames are individually suction-held by a suction collet or the like and then transferred to the predetermined position. Further, when the frames 7 and 8 are connected, an image processing apparatus that has been used conventionally recognizes the connection state of the frames 7 and 8 to reset the positions of the frames 7 and 8 for each transfer. Is also possible.
【００２１】つづいて、前記リードフレーム１５を加熱
炉（図示せず）に送り込む等することにより、半田の融
点よりも高い温度に加熱する。すると、上記半田は、こ
の加熱により溶融して半導体チップ３と第１リード端子
部１３との双方に合金化し、また、電極部１、２と第２
及び第３リード端子部１４、１５との間に塗布した半田
は、溶融して各々に合金化接合することになる。Then, the lead frame 15 is heated to a temperature higher than the melting point of the solder by sending it into a heating furnace (not shown). Then, the solder is melted by this heating and alloyed with both the semiconductor chip 3 and the first lead terminal portion 13, and the electrode portions 1, 2 and the second
And the solder applied between the third lead terminal portions 14 and 15 is melted and alloyed and joined to each.
【００２２】さらに、リードフレーム１０を移送して、
従来から用いられるモールド成形金型により、各半導体
チップ３およびその周辺を覆うモールド部９をエポキシ
樹脂により成形し、次いで、従来から用いられる打ち抜
き成形金型により、第１乃至第３リード端子部１３、１
４、１５の所定位置を切断する。以上のような方法によ
り、３端子型のダイオードは製造される。Further, the lead frame 10 is transferred,
A mold part 9 covering each semiconductor chip 3 and its periphery is molded with an epoxy resin by a conventionally used mold mold, and then the first through third lead terminal parts 13 are formed by a conventionally used punch mold. 1
The predetermined positions 4 and 15 are cut. The three-terminal type diode is manufactured by the above method.
【００２３】本実施例では、フレーム７、８は平面視形
状が先端幅太の形状となっているが、図５（ａ）および
図５（ｂ）に示すように、先端角部がテーパ形状やＲ形
状となっているもの等でもよく、これを限定するもので
なく、また、図５（ｃ）に示すように、平面視長方形状
のものを平面視ハの字状に配置することもできる。ま
た、本実施例では、フレーム７、８は断面視形状が階段
形状となっているが、これに限定するものでなく、図６
に示すように、フレーム７、８（図６中では、フレーム
７省略）は直線状のもの等を用いることも可能であり、
更に、曲げ角度は１２０度程度のものに限定するもので
ない。In the present embodiment, the frames 7 and 8 have a wide tip in a plan view, but as shown in FIGS. 5A and 5B, the tip corners are tapered. However, the shape is not limited thereto, and a rectangular shape in plan view may be arranged in a V shape in plan view as shown in FIG. 5C. it can. Further, in the present embodiment, the cross-sectional shape of the frames 7 and 8 has a step shape, but the shape is not limited to this, and FIG.
As shown in FIG. 6, the frames 7 and 8 (the frame 7 is omitted in FIG. 6) may be linear ones or the like.
Further, the bending angle is not limited to about 120 degrees.
【００２４】さらに、本実施例では、第２および第３リ
ード端子部１４、１５は平板状であるが、これに限定す
るものでなく、各フレーム７、８との接続部分である各
先端部に突起部を設けることにより、これら突起部をフ
レーム７、８を載置する際のストッパとして作用させる
ことで、フレーム７、８の第２および第３リード端子部
１４、１５に対する位置ずれを防止できる。また、第２
および第３リード端子部１４、１５の、各フレーム７、
８との接続部分にそれぞれ貫通穴を設け、フレーム７、
８の上記貫通穴に対応する位置に突起部を設けても、位
置決めの作用を得られる。Further, in the present embodiment, the second and third lead terminal portions 14 and 15 have a flat plate shape, but the present invention is not limited to this, and each tip portion which is a connection portion with each frame 7 and 8. By providing the protrusions on the protrusions, the protrusions act as stoppers when the frames 7 and 8 are placed, and thus the displacement of the frames 7 and 8 with respect to the second and third lead terminal portions 14 and 15 is prevented. it can. Also, the second
And each frame 7 of the third lead terminal portions 14 and 15,
Through holes are formed in the connecting portions with the frame 7,
Even if a protrusion is provided at a position corresponding to the above-mentioned through hole of 8, the positioning effect can be obtained.
【００２５】加えて、本実施例では、フレーム７、８は
銅からなるものであるが、これに限定するものでなく、
アルミニウムや銅等の種々の金属を用いることができ、
また、塑性変形しているものが好ましい。また、本実施
例においては、三端子型のダイオードを用いているが、
これに限定するものでなく、ダイオード以外のＩＣやト
ランジスタ等にも適用可能であり、さらに、二端子型の
種々の半導体装置に対しても適用可能である。In addition, although the frames 7 and 8 are made of copper in this embodiment, the present invention is not limited to this.
Various metals such as aluminum and copper can be used,
Further, it is preferably plastically deformed. Further, in the present embodiment, a three-terminal type diode is used,
The present invention is not limited to this, and can be applied to ICs other than diodes, transistors, and the like, and can also be applied to various two-terminal semiconductor devices.
【図１】本発明の半導体装置を示す要部断面図である。FIG. 1 is a cross-sectional view of essential parts showing a semiconductor device of the present invention.
【図２】本発明の半導体装置を示す部分切欠き平面図で
ある。FIG. 2 is a partially cutaway plan view showing a semiconductor device of the present invention.
【図３】本発明の半導体装置を作製する際に、フレーム
が各リード端子に対して変形している様子を説明するた
めの説明図である。FIG. 3 is an explanatory diagram for explaining how the frame is deformed with respect to each lead terminal when the semiconductor device of the present invention is manufactured.
【図４】本発明の半導体装置を作製する際に用いるリー
ドフレームを示す要部平面図である。FIG. 4 is a plan view of relevant parts showing a lead frame used in manufacturing the semiconductor device of the present invention.
【図５】本発明の半導体装置のリード端子の変形例を示
す要部平面図である。FIG. 5 is a main part plan view showing a modified example of the lead terminal of the semiconductor device of the present invention.
【図６】本発明の半導体装置のリード端子の変形例を示
す要部断面図である。FIG. 6 is a cross-sectional view of essential parts showing a modification of the lead terminal of the semiconductor device of the present invention.
【図７】従来の半導体装置を示す要部平面図である。FIG. 7 is a main-portion plan view showing a conventional semiconductor device.
【図８】従来の半導体装置においてリード端子の変形に
よる外観不良となったものを示す要部斜視図である。FIG. 8 is a perspective view of relevant parts showing a conventional semiconductor device having a poor appearance due to deformation of lead terminals.
１ 電極部 ２ 電極部 ３ 半導体チップ ４ 第１リード端子 ５ 第２リード端子 ６ 第３リード端子 ７ フレーム ８ フレーム ９ モールド部 １０ リードフレーム １１ サイドフレーム １２ サイドフレーム １３ 第１リード端子部 １４ 第２リード端子部 １５ 第３リード端子部 1 Electrode Part 2 Electrode Part 3 Semiconductor Chip 4 First Lead Terminal 5 Second Lead Terminal 6 Third Lead Terminal 7 Frame 8 Frame 9 Molded Part 10 Lead Frame 11 Side Frame 12 Side Frame 13 First Lead Terminal Part 14 Second Lead Terminal part 15 Third lead terminal part
Claims (1)
プと、該半導体チップの下面に接続した第１のリード端
子と、前記２つの電極部の一方に接続した第２のリード
端子と、前記２つの電極部の他方に接続した第３のリー
ド端子と、前記半導体チップおよび前記第１乃至第３の
リード端子の一部を覆うモールド部と、を備えてなる半
導体装置であって、 前記電極部と第２および第３のリード端子とを、フレー
ムを介して各々接続していることを特徴とする半導体装
置。1. A semiconductor chip having two electrode portions provided on an upper surface thereof, a first lead terminal connected to a lower surface of the semiconductor chip, and a second lead terminal connected to one of the two electrode portions. A semiconductor device comprising: a third lead terminal connected to the other of the two electrode portions; and a mold portion that covers the semiconductor chip and a part of the first to third lead terminals. A semiconductor device, wherein the electrode portion and the second and third lead terminals are connected to each other via a frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6289661A JPH08148623A (en) | 1994-11-24 | 1994-11-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6289661A JPH08148623A (en) | 1994-11-24 | 1994-11-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08148623A true JPH08148623A (en) | 1996-06-07 |
Family
ID=17746124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6289661A Pending JPH08148623A (en) | 1994-11-24 | 1994-11-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08148623A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184911A (en) * | 2000-12-15 | 2002-06-28 | Nippon Inter Electronics Corp | Resin sealed electronic component |
| US6849930B2 (en) | 2000-08-31 | 2005-02-01 | Nec Corporation | Semiconductor device with uneven metal plate to improve adhesion to molding compound |
| US7839003B2 (en) | 2007-07-31 | 2010-11-23 | Panasonic Corporation | Semiconductor device including a coupling conductor having a concave and convex |
| JP2012004594A (en) * | 2011-09-02 | 2012-01-05 | Renesas Electronics Corp | Semiconductor device |
| WO2012143964A1 (en) * | 2011-04-18 | 2012-10-26 | 三菱電機株式会社 | Semiconductor device, inverter device provided with semiconductor device, and in-vehicle rotating electrical machine provided with semiconductor device and inverter device |
| US8816411B2 (en) | 1999-01-28 | 2014-08-26 | Renesas Electronics Corporation | Mosfet package |
| JP5972172B2 (en) * | 2010-11-16 | 2016-08-17 | 富士電機株式会社 | Semiconductor device |
-
1994
- 1994-11-24 JP JP6289661A patent/JPH08148623A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8816411B2 (en) | 1999-01-28 | 2014-08-26 | Renesas Electronics Corporation | Mosfet package |
| US6849930B2 (en) | 2000-08-31 | 2005-02-01 | Nec Corporation | Semiconductor device with uneven metal plate to improve adhesion to molding compound |
| JP2002184911A (en) * | 2000-12-15 | 2002-06-28 | Nippon Inter Electronics Corp | Resin sealed electronic component |
| US7839003B2 (en) | 2007-07-31 | 2010-11-23 | Panasonic Corporation | Semiconductor device including a coupling conductor having a concave and convex |
| JP5972172B2 (en) * | 2010-11-16 | 2016-08-17 | 富士電機株式会社 | Semiconductor device |
| WO2012143964A1 (en) * | 2011-04-18 | 2012-10-26 | 三菱電機株式会社 | Semiconductor device, inverter device provided with semiconductor device, and in-vehicle rotating electrical machine provided with semiconductor device and inverter device |
| JPWO2012143964A1 (en) * | 2011-04-18 | 2014-07-28 | 三菱電機株式会社 | SEMICONDUCTOR DEVICE, INVERTER DEVICE HAVING THE SAME, AND VEHICLE ROTARY ELECTRIC DEVICE HAVING THE SAME |
| US9117688B2 (en) | 2011-04-18 | 2015-08-25 | Mitsubishi Electric Corporation | Semiconductor device, inverter device provided with semiconductor device, and in-vehicle rotating electrical machine provided with semiconductor device and inverter device |
| JP5821949B2 (en) * | 2011-04-18 | 2015-11-24 | 三菱電機株式会社 | SEMICONDUCTOR DEVICE, INVERTER DEVICE HAVING THE SAME, AND VEHICLE ROTARY ELECTRIC DEVICE HAVING THE SAME |
| JP2012004594A (en) * | 2011-09-02 | 2012-01-05 | Renesas Electronics Corp | Semiconductor device |
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