JPH0638458B2 - Chip carrier and method of manufacturing the same - Google Patents
Chip carrier and method of manufacturing the sameInfo
- Publication number
- JPH0638458B2 JPH0638458B2 JP60202643A JP20264385A JPH0638458B2 JP H0638458 B2 JPH0638458 B2 JP H0638458B2 JP 60202643 A JP60202643 A JP 60202643A JP 20264385 A JP20264385 A JP 20264385A JP H0638458 B2 JPH0638458 B2 JP H0638458B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- lsi chip
- chip
- cap
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、チップキャリアとその製造方法、特に、電子
装置等に使用され入出力パッド付きセラミック基板にＬ
ＳＩチップをフェイスダウンで実装するチップキャリア
とその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a chip carrier and a method for manufacturing the same, and more particularly to a ceramic substrate with an input / output pad used in an electronic device or the like.
The present invention relates to a chip carrier for mounting an SI chip face down and a manufacturing method thereof.
従来のチップキャリアは第２図に示すように、セラミッ
ク基板２１上の金属層２２にＬＳＩチップ２３を固着
し、ワイヤ２４でＬＳＩチップ２３と基板２１上のパッ
ド２５に電気的に接続し、キャップ２６を封止している
（例えば特開昭57−126151公報）。As shown in FIG. 2, the conventional chip carrier has an LSI chip 23 fixed to a metal layer 22 on a ceramic substrate 21, electrically connected to the LSI chip 23 and a pad 25 on the substrate 21 by a wire 24, and a cap. 26 is sealed (for example, JP-A-57-126151).
〔発明が解決しようとする問題点〕 しかしながら、このような上述した従来のチップキャリ
アでは、ＬＳＩチップがフェイスアップ実装のために、
上にヒートシンク等の放熱部品を付けても放熱効果が少
なく、下にはチップキャリアを乗せる基板が来るので放
熱部品は取り付けられなく、消費電力の多いＬＳＩチッ
プの実装には適しないという欠点がある。[Problems to be Solved by the Invention] However, in such a conventional chip carrier as described above, since the LSI chip is face-up mounted,
Even if a heat dissipation component such as a heat sink is attached to the top, the heat dissipation effect is small, and since the substrate on which the chip carrier is placed comes below, the heat dissipation component cannot be attached, which is not suitable for mounting an LSI chip with high power consumption. .
上述の課題を解決するために、本発明のチップキャリア
は、ＬＳＩチップと、内面に前記ＬＳＩチップのリード
と接続されるリード用パッドが形成され外面に前記パッ
ドと接続された突起状のパッドが形成され側面に封止の
ための金属層が形成されたセラミック基板と、前記ＬＳ
Ｉチップと前記セラミック基板の間に設けられ前記ＬＳ
Ｉチップを支持するスペーサと、前記セラミック基板が
挿入され前記セラミック基板の前記金属層に接続される
ことにより前記ＬＳＩチップを封止し前記ＬＳＩチップ
と接続されるキャップとを含む。In order to solve the above-mentioned problems, a chip carrier of the present invention has an LSI chip, a lead pad connected to a lead of the LSI chip on an inner surface, and a protruding pad connected to the pad on an outer surface. A ceramic substrate formed with a metal layer for sealing on its side surface;
The LS is provided between the I chip and the ceramic substrate.
A spacer for supporting the I-chip and a cap for sealing the LSI chip by connecting the ceramic substrate to the metal layer of the ceramic substrate and connecting with the LSI chip are connected.
さらに、本発明のチップキャリアの製造方法は、前記Ｌ
ＳＩチップと前記キャップとの接続と前記キャップと前
記セラミック基板との接続とを、Ａｕ／Ｓｎ（８０ｗｔ
％）で同時に行うことにより、このチップキャリアを製
造する。Furthermore, the manufacturing method of the chip carrier of the present invention is
The connection between the SI chip and the cap and the connection between the cap and the ceramic substrate are Au / Sn (80 wt.
%) At the same time to manufacture this chip carrier.
次に、本発明の実施例について、図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す縦断面図である。FIG. 1 is a vertical sectional view showing an embodiment of the present invention.
第１図に示すチップキャリアは、セラミック基板１の内
面にはリード用パッド２が、外面には突起状パッド３
が、側面には金属層４が、各々設けてあり、リード用パ
ッド２と突起状パッド３はセラミック基板１内で接続さ
れている。スペーサ５はゴム状のもの（例えばシリコー
ンゴム）で、接着剤６（例えばシリコーン系）でセラミ
ック基板１に付けられている。ＬＳＩチップ７はフェイ
スダウンでスペーサ５上に接着剤６で付けられ、ＬＳＩ
チップ７のリード８はセラミック基板１上のリード用パ
ッド２に接続されている。キャップ９はＬＳＩチップ７
にAu／Sn10(80／20wt%)で付けられ、セラミック基板１
の金属層４にもAu／Sn10(80／20wt%)で付けられてい
る。In the chip carrier shown in FIG. 1, lead pads 2 are provided on the inner surface of a ceramic substrate 1, and projecting pads 3 are provided on the outer surface.
However, a metal layer 4 is provided on each side surface, and the lead pad 2 and the projecting pad 3 are connected in the ceramic substrate 1. The spacer 5 is made of rubber (eg, silicone rubber) and is attached to the ceramic substrate 1 with an adhesive 6 (eg, silicone-based). The LSI chip 7 is attached face down on the spacer 5 with the adhesive 6.
The leads 8 of the chip 7 are connected to the lead pads 2 on the ceramic substrate 1. The cap 9 is the LSI chip 7
Attached to Au / Sn10 (80 / 20wt%) on the ceramic substrate 1
The metal layer 4 is also Au / Sn10 (80/20 wt%).
キャップ９はCu／MoやBeOなど熱伝導率の良いものを用
いることによりキャップ９上に付けられるヒートシンク
等の放熱部品にＬＳＩチップ７で発生する熱を効率よく
伝えられる。スペーサ５はゴム状のものを用いることに
より、スペーサ５やセラミック基板１の凹凸やＬＳＩチ
ップ７とセラミック基板１と傾きにＬＳＩチップ７の回
路面（スペーサ５側の面）へのキズを防止している。By using a material having a high thermal conductivity such as Cu / Mo or BeO for the cap 9, the heat generated in the LSI chip 7 can be efficiently transferred to a heat dissipation component such as a heat sink mounted on the cap 9. By using a rubber-like spacer 5, it is possible to prevent unevenness of the spacer 5 and the ceramic substrate 1 and scratches on the circuit surface of the LSI chip 7 (the surface on the spacer 5 side) due to the inclination between the LSI chip 7 and the ceramic substrate 1. ing.
次に、第１図に示すチップキャリアの製造手順について
説明する。Next, a manufacturing procedure of the chip carrier shown in FIG. 1 will be described.
初めに、スペーサ５をセラミック基板１に接着剤６で付
ける。First, the spacer 5 is attached to the ceramic substrate 1 with the adhesive 6.
次に、スペーサ５上にＬＳＩチップ７フェイスダウン実
装で接着剤６により付ける。そして、ＬＳＩチップ７の
リード８をセラミック基板１上のリード用パッド２に付
ける（例えば、半田付けや熱圧着ボンディング）。Next, the LSI chip 7 is mounted face down on the spacer 5 with the adhesive 6. Then, the leads 8 of the LSI chip 7 are attached to the lead pads 2 on the ceramic substrate 1 (for example, soldering or thermocompression bonding).
さらに、ＬＳＩチップ７とキャップ９との間に板状のAu
／Snをはさみ、かつ金属層４の周囲にもAu／Snを置い
て、キャップ９とセラミック基板１とを押せながら加熱
することで、ＬＳＩチップ７はキャップ９に半田付けさ
れ、かつ封止されて完成する。Furthermore, a plate-shaped Au is provided between the LSI chip 7 and the cap 9.
By sandwiching / Sn and placing Au / Sn around the metal layer 4 and heating while pressing the cap 9 and the ceramic substrate 1, the LSI chip 7 is soldered to the cap 9 and sealed. Complete.
スペーサ５は先にＬＳＩチップ７に付けてもセラミック
基板１に付けても良い。The spacer 5 may be attached to the LSI chip 7 or the ceramic substrate 1 first.
Au／Snはキャップ９かまたはＬＳＩチップ７、金属層４
かまたはキャップ９、の各々の一方または両方に予備半
田しても良い。Au / Sn is cap 9 or LSI chip 7, metal layer 4
Alternatively, one or both of each of the caps 9 may be pre-soldered.
本発明のチップキャリアとその製造方法は、LSIチップ
とキャップとの接続と封止をAu／Snにより同時に行うこ
とにより、放熱性ならびに気密性を向上できるという効
果がある。INDUSTRIAL APPLICABILITY The chip carrier and the method for manufacturing the same of the present invention have the effect that the heat dissipation and airtightness can be improved by simultaneously connecting and sealing the LSI chip and the cap with Au / Sn.
第１図は本発明の一実施例を示す縦断面、第２図は従来
の一例を示す断面図である。 １，２１……セラミック基板、２……リード用パッド、
３……突起状パッド、４……金属層、５……スペーサ、
６……接着剤、７，２３……LSIチップ、８……リー
ド、９，２６……キャップ、１０……Au／Sn、２２……
金属層、２４……ワイヤー、２５……パッド。FIG. 1 is a vertical cross-sectional view showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a conventional example. 1, 21 ... Ceramic substrate, 2 ... Lead pad,
3 ... protruding pad, 4 ... metal layer, 5 ... spacer,
6 ... Adhesive, 7,23 ... LSI chip, 8 ... Lead, 9,26 ... Cap, 10 ... Au / Sn, 22 ...
Metal layer, 24 ... Wire, 25 ... Pad.
Claims (2)
パッドが形成され外面に前記パッドと接続された突起状
のパッドが形成され側面に封止のための金属層が形成さ
れたセラミック基板と、 前記ＬＳＩチップと前記セラミック基板の間に設けられ
前記ＬＳＩチップを支持するスペーサと、 前記セラミック基板が挿入され内側面が前記セラミック
基板の前記金属層に接続されることにより前記ＬＳＩチ
ップを封止し前記ＬＳＩチップと接続されるキャップと
を含むことを特徴とするチップキャリア。1. An LSI chip, a lead pad connected to a lead of the LSI chip is formed on an inner surface, a protruding pad connected to the pad is formed on an outer surface, and a metal layer for sealing is formed on a side surface. A ceramic substrate on which is formed, a spacer provided between the LSI chip and the ceramic substrate to support the LSI chip, and the ceramic substrate is inserted and an inner surface is connected to the metal layer of the ceramic substrate. And a cap connected to the LSI chip for sealing the LSI chip.
と前記キャップと前記セラミック基板との接続とを、Ａ
ｕ／Ｓｎ（８０ｗｔ％）で同時に行うことを特徴とする
特許請求の範囲第１項記載のチップキャリアの製造方
法。2. The connection between the LSI chip and the cap and the connection between the cap and the ceramic substrate are
The method for producing a chip carrier according to claim 1, wherein the steps are performed simultaneously with u / Sn (80 wt%).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60202643A JPH0638458B2 (en) | 1985-09-12 | 1985-09-12 | Chip carrier and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60202643A JPH0638458B2 (en) | 1985-09-12 | 1985-09-12 | Chip carrier and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6262545A JPS6262545A (en) | 1987-03-19 |
| JPH0638458B2 true JPH0638458B2 (en) | 1994-05-18 |
Family
ID=16460737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60202643A Expired - Lifetime JPH0638458B2 (en) | 1985-09-12 | 1985-09-12 | Chip carrier and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0638458B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6421945A (en) * | 1987-07-16 | 1989-01-25 | Toshiba Corp | Electronic element mounting module |
| JPH01150343A (en) * | 1987-12-07 | 1989-06-13 | Nec Corp | Cap for chip carrier |
| US5264726A (en) * | 1989-07-21 | 1993-11-23 | Nec Corporation | Chip-carrier |
| CA2021682C (en) * | 1989-07-21 | 1995-01-03 | Yukio Yamaguchi | Chip-carrier with alpha ray shield |
| US5293301A (en) * | 1990-11-30 | 1994-03-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device and lead frame used therein |
| JP2827684B2 (en) * | 1992-03-17 | 1998-11-25 | 日本電気株式会社 | Semiconductor device |
| JP3400427B2 (en) * | 2000-11-28 | 2003-04-28 | 株式会社東芝 | Electronic component unit and printed wiring board device mounted with electronic component unit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961148A (en) * | 1982-09-30 | 1984-04-07 | Hitachi Ltd | Manufacture of ceramic substrate |
| JPS6076148A (en) * | 1983-10-03 | 1985-04-30 | Nec Corp | Chip carrier |
| JPS6076149A (en) * | 1983-10-03 | 1985-04-30 | Nec Corp | Chip carrier |
-
1985
- 1985-09-12 JP JP60202643A patent/JPH0638458B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6262545A (en) | 1987-03-19 |
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