JPH0216074U - - Google Patents
Info
- Publication number
- JPH0216074U JPH0216074U JP9344788U JP9344788U JPH0216074U JP H0216074 U JPH0216074 U JP H0216074U JP 9344788 U JP9344788 U JP 9344788U JP 9344788 U JP9344788 U JP 9344788U JP H0216074 U JPH0216074 U JP H0216074U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- regular
- test
- input
- circuit section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Description
第1図及び第2図は本考案のASICのテスト
信号入力回路の1実施例のブロツク結線図及び詳
細なブロツク結線図、第3図は従来例のブロツク
結線図である。
1…外部入力端子、6…正規回路部、7…テス
ト回路部、12…信号発生手段。
1 and 2 are block wiring diagrams and detailed block wiring diagrams of one embodiment of the ASIC test signal input circuit of the present invention, and FIG. 3 is a block wiring diagram of a conventional example. DESCRIPTION OF SYMBOLS 1... External input terminal, 6... Regular circuit part, 7... Test circuit part, 12... Signal generation means.
Claims (1)
規信号を出力する正規回路部と、前記正規信号の
入力により所定の信号を出力する出力部と、テス
ト信号の入力により作動し前記所定時間内に前記
正規信号と同一の信号を前記出力部に出力するテ
スト回路部とをASICに備え、前記テスト回路
部に前記テスト信号を入力するASICのテスト
信号入力回路において、 前記ASICの外部入力端子への前記正規回路
部が動作することのない論理の信号の入力により
、前記テスト回路部に前記テスト信号を発生出力
する信号発生手段を設けたASICのテスト信号
入力回路。[Claims for Utility Model Registration] A regular circuit section that operates upon input of a drive signal and outputs a regular signal after a predetermined time; an output section that outputs a predetermined signal upon input of the regular signal; and a regular circuit section that outputs a prescribed signal upon input of the regular signal; In the test signal input circuit of the ASIC, the ASIC includes a test circuit section that operates and outputs the same signal as the regular signal to the output section within the predetermined time, and inputs the test signal to the test circuit section. A test signal input circuit for an ASIC, comprising signal generating means for generating and outputting the test signal in the test circuit section by inputting a logic signal that does not cause the normal circuit section to operate to an external input terminal of the ASIC.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9344788U JPH0216074U (en) | 1988-07-14 | 1988-07-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9344788U JPH0216074U (en) | 1988-07-14 | 1988-07-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0216074U true JPH0216074U (en) | 1990-02-01 |
Family
ID=31317906
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9344788U Pending JPH0216074U (en) | 1988-07-14 | 1988-07-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0216074U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63148175A (en) * | 1986-12-10 | 1988-06-21 | Mitsubishi Electric Corp | Integrated logic circuit device |
-
1988
- 1988-07-14 JP JP9344788U patent/JPH0216074U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63148175A (en) * | 1986-12-10 | 1988-06-21 | Mitsubishi Electric Corp | Integrated logic circuit device |
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