JPS6157868U - - Google Patents
Info
- Publication number
- JPS6157868U JPS6157868U JP14221684U JP14221684U JPS6157868U JP S6157868 U JPS6157868 U JP S6157868U JP 14221684 U JP14221684 U JP 14221684U JP 14221684 U JP14221684 U JP 14221684U JP S6157868 U JPS6157868 U JP S6157868U
- Authority
- JP
- Japan
- Prior art keywords
- output
- converter
- input
- circuit
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Controls And Circuits For Display Device (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は本考案の実施例を示すＣＲＴ表示例を示
す。
１：演算回路、２：Ｄ／Ａコンバータ、３：Ｄ
Ａコンバータ、４：加算器、５：加算器、６：シ
ユミツトトリガ回路、７：シユミツトトリガ回路
、８：タイミング制御回路、９：カウンター、１
０：カウントパルス発生器、１１：文字発生回路
。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 shows an example of a CRT display showing an embodiment of the present invention. 1: Arithmetic circuit, 2: D/A converter, 3: D
A converter, 4: Adder, 5: Adder, 6: Schmitt trigger circuit, 7: Schmitt trigger circuit, 8: Timing control circuit, 9: Counter, 1
0: Count pulse generator, 11: Character generation circuit.
Claims (1)
算回路の出力を第１のＤＡコンバータ及び第２の
ＤＡコンバータに入力し、第１のＤＡコンバータ
の出力を第１の加算器に入力し、前記第２のＤＡ
コンバータの出力を第２の加算器に入力し前記第
１の加算器の出力を第１のシユミツトトリガ回路
にトリガレベルとして入力し、前記第２の加算器
の出力を第２のシユミツトトリガ回路にトリガレ
ベルとして入力し、該第２、前記第１のシユミツ
トトリガ回路には被観測入力信号を入力し両シユ
ミツトトリガ回路の出力をタイミング制御回路に
接続しその出力をゲート信号としカウントパルス
発生器によりカウントされた信号をカウンタより
出力し文字発生回路に入力し、ＣＲＴ上にカウン
ト結果の文字表示を行なう事を特徴とするオシロ
スコープ。 An arithmetic circuit that inputs cursor data and the output of the arithmetic circuit are input to a first DA converter and a second DA converter, the output of the first DA converter is input to a first adder, and the output of the arithmetic circuit is input to a first DA converter and a second DA converter. DA of
The output of the converter is inputted to a second adder, the output of the first adder is inputted as a trigger level to a first Schmitt trigger circuit, and the output of the second adder is inputted to a second Schmitt trigger circuit as a trigger level. The input signal to be observed is input to the second and first Schmitt trigger circuits, the outputs of both Schmitt trigger circuits are connected to a timing control circuit, and the output is used as a gate signal to generate a signal counted by a count pulse generator. An oscilloscope that outputs from a counter, inputs it to a character generation circuit, and displays the count result in characters on a CRT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14221684U JPS6157868U (en) | 1984-09-21 | 1984-09-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14221684U JPS6157868U (en) | 1984-09-21 | 1984-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6157868U true JPS6157868U (en) | 1986-04-18 |
Family
ID=30700543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14221684U Pending JPS6157868U (en) | 1984-09-21 | 1984-09-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6157868U (en) |
-
1984
- 1984-09-21 JP JP14221684U patent/JPS6157868U/ja active Pending
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