JPS62189675U

JPS62189675U -

Info

Publication number: JPS62189675U
Application number: JP6843887U
Authority: JP
Priority date: 1987-05-07
Filing date: 1987-05-07
Publication date: 1987-12-02
Also published as: JPH019019Y2

Description

[Brief explanation of the drawing]

第１図は従来の論理機能試験装置の概略図、第
２図はその動作説明図、第３図は本考案の論理機
能試験装置の一実施例概略図、第４図はその制御
回路の詳細説明図、第５図は制御クロツクの説明
図、第６図及び第７図はその制御状態説明図であ
る。図中、１は制御クロツク発生器、２，３はアン
ド回路、４はオア回路、５，６はナンド回路、７
はリセツト・セツト付Ｄ・フリツプ・フロツプ、
８，９はインバータ、１０，１０―１〜１０―ｎ
は制御回路をそれぞれ示す。 FIG. 1 is a schematic diagram of a conventional logic function test device, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a schematic diagram of an embodiment of the logic function test device of the present invention, and FIG. 4 is a detailed diagram of its control circuit. FIG. 5 is an explanatory diagram of the control clock, and FIGS. 6 and 7 are explanatory diagrams of its control state. In the figure, 1 is a control clock generator, 2 and 3 are AND circuits, 4 is an OR circuit, 5 and 6 are NAND circuits, and 7
D flip flop with reset/set,
8, 9 are inverters, 10, 10-1 to 10-n
indicate control circuits, respectively.

Claims

[Claims for Utility Model Registration] A device comprising a plurality of terminals and a control circuit for transmitting a signal to a logic circuit under test whose function is to be measured or for transmitting an output signal from the logic circuit under test, In a logic function testing device that selectively controls the functions of the plurality of terminals by transmitting a control signal to a control circuit,
control clock CK ₁ , second control clock CK ₂ ,
A clock generating means for generating a third control clock _CK3 ; a first control signal holding section D and a second control signal holding section X to which a control pattern signal is input for the control circuit; a first AND gate means 2; A second AND gate means 3, a first NAND gate means 5, a second NAND gate means 6, and a state holding means 7 to which the outputs of these NAND gate means are input are provided, and the output of the first control signal holding section is kept in the state. The control signal is inputted to the data terminal of the holding means and the second NAND gate means, and its inverted signal is inputted to the first NAND gate means.The output of the second control signal holding section is inputted to the second AND gate means, and its inverted signal is inputted to the first NAND gate means. The first control clock CK ₁ of the clock generating means is input to the first AND gate means, the second control clock CK ₂ is input to the second AND gate means, and the third control clock CK CK is input to the second AND gate means. ₃ is input to the first NAND gate means and the second NAND gate means, the output of the first NAND gate means is inputted to the set terminal of the state holding means, and the output of the second NAND gate means is inputted to the reset terminal of the state holding means. Logic function test equipment.