JPH019019Y2 - - Google Patents

Description

[Detailed description of the invention] [Field of industrial application] The present invention relates to a logic function testing device, and in particular, it is capable of selectively inputting either a general input signal or a clock signal to each input terminal under test. The present invention relates to a logic function testing device configured as follows.

[Conventional technology]

For example, when testing the logic function of a certain circuit, a general input signal, ie, data, is input to one input terminal among the terminals of the circuit, and a clock signal is applied to the other input terminals. Outputs obtained corresponding to each of the above inputs are detected from the output terminals. In such a case, if the circuit under test is different, the position of the data input terminal to which data is input, the position of the clock input terminal to which the clock should be input, or the position of the output terminal, etc. will be different. Therefore, it is necessary to selectively output the transmission signal to each terminal as either data or clock depending on the circuit under test. Therefore, as shown in FIG. 1, the buffer D ₁ ~
D _o and X ₁ to _{X o} were provided, and by applying a control signal as shown in FIG. 2 to each buffer, the terminals were selectively used as data terminals or clock terminals.

For example, in Figure 1, among the pins P ₁ , P ₂ , ... P _o of the logic function test equipment, P ₁ is used as a general input terminal (a terminal for inputting data to the circuit under test), and P ₂ is used as a clock input terminal. When using P _o as a terminal (terminal for inputting a clock to the circuit under test) and as an output terminal (terminal to which the output signal output from the circuit under test is transmitted), set switch S ₁₁ to S _1s. Connect, close relay R _1i and open R ₁₀ to transmit "1" to buffer D ₁ and generate "1" to P ₁ as shown in FIG. It also transmits "0" to the buffer _D1 and generates "0" at the terminal _P1 .
On the other hand, regarding terminal P ₂ used for clock, switch S ₂₁ is connected to S _2c , relay R _2i is closed, and R ₂₀ is opened, as shown in Fig. 2, transmitting "1" to buffer D ₂ and connecting terminal P. Generates a clock at ₂ .
Also, when transmitting "0" to buffer _D2 , the terminal
No clock is generated for _P2 . And for the terminal P _o used as an output terminal, the relay R _oi
Open R _op and open the buffer D _o as shown in Figure 2.
When "1" is transmitted to the buffer X _{o and "0" is transmitted to the buffer X o} , the output logic comparison circuit C _o operates and the terminal P _o
The comparison operation is performed with the expectation that "1" is output from the circuit under test, and if "1" is output at terminal P _o
This is the receiver RV _o when is not output.
The signal is transmitted to the output logic comparison circuit C _o via the output logic comparison circuit C o and the result is reported as a mismatch. Also, Batsuhua D _o and X _o
If “0” is transmitted to both terminals, the output logic comparison circuit C _o transmits “0” from the circuit under test to the terminal P _o .
The comparison operation is performed with the expectation that . However, when "1" is transmitted to buffer X _o , regardless of the value transmitted to buffer D _o ,
Furthermore, regardless of what is being transmitted to the terminal P _o , the output logic comparison circuit C _o does not operate.

(Problem that the invention aims to solve) Therefore, in conventional logic function test equipment, once a terminal is defined as a general input terminal, when it is used as a clock terminal, conversely, it is also defined as a clock terminal. When it was defined as , it had the disadvantage that special control was required to use it as a general input terminal.

[Means for solving problems]

Therefore, it is an object of the present invention to overcome these drawbacks and provide a logic function testing device having an input terminal configured so that it can be used not only as a general input terminal but also as a clock input terminal. For this purpose, the logic function testing device of the present invention is equipped with a plurality of terminals and a control circuit through which signals or clock signals are transmitted to the logic circuit under test whose function is to be measured. In the logic function testing device which selectively controls the functions of the plurality of terminals by transmitting an input signal and a control signal to the control circuit, a first control clock CK having the same cycle but different timing is provided. ₁ , a clock generating means for generating the second control clock _CK2 and the third control clock _CK3 , and a control circuit including an input signal holding section D and a control signal holding section X to which input signals are input, and a first AND gate. means 2 and second AND gate means 3
and the first NAND gate means 5, the second NAND gate means 6, and the outputs of these AND gate means and NAND gate means are input, and when a logic "1" is input to the set terminal, outputs a logic "1",
A state holding means 7 and a terminal that output logic "0" when logic "0" is input to the reset terminal, and output the input to the data terminal as is when logic "1" is input to the set and reset terminals. A driver is provided, which inputs the output of the input signal holding section to the data terminal of the state holding means and the first NAND gate means, inputs its inverted signal to the first NAND gate means, and inputs the output of the control signal holding section to the second NAND gate means. The first control clock CK ₁ of the clock generating means is input to the first AND gate means, and the second control clock CK ₂ is input to the second AND gate means.
input to the AND gate means and the third control clock
CK ₃ is input to the first and second NAND gate means, the outputs of the first and second AND gate means are input to the clock terminal of the state holding means, and the output of the first NAND gate means is input to the set of the state holding means. The output of the second NAND gate means is input to the reset terminal of the state holding means, and the output of the state holding means is applied to the driver.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 3 to 7.

FIG. 3 shows the configuration of one embodiment of the present invention, FIG. 4 is a detailed explanatory diagram of its control circuit, FIG. 5 shows the states of a plurality of control clocks, and FIGS. 6 and 7 show the control states. It is an explanatory diagram.

In the figure, the same reference numerals as the others indicate the same parts, and 1 is a control clock generator, 2 and 3 are AND circuits, 4 is an OR circuit, 5 and 6 are NAND circuits, and 7 is a reset/set circuit. A D-flip-flop (hereinafter referred to as D-FF with R-S), 8 and 9 are inverters, and 10 and 10-1 to 10-n are control circuits.

The control clock generator 1, as shown in FIG.
It generates control clocks CK ₁ , CK ₂ and CK ₃ . These control clocks CK ₁ to _{CK 3} all have the same period of the test cycle T _s , but the control clock CK ₂ is generated a time T _d after the control clock CK ₁ , and the period of the test cycle T s is the same.
Control clock CK ₃ is generated after a delay of T _w .
The values of these times T _d and T _w can also be controlled by a program.

The OR circuit 4 outputs the signal shown in FIG. 6C in response to "1" and "0" applied to the buffers D and X.

D/FF7 with R/S outputs “1” when “0” is applied to the set terminal S, and the reset terminal R
When "0" is applied to "0", "0" is output. When "1" is applied to each of the set terminal S and the reset terminal R, the circuit is configured to output the signal transmitted to the terminal _Dp by applying a clock.

The configuration of the present invention will be explained based on FIGS. 4 to 7. The control circuit 10 shown in FIG.
1 of control circuits 10-1 to 10-n in FIG.
This is a representative detailed description of one.

As shown in test period 1 in Figure 6,
For example, "0" is applied to buffer D and buffer X from a control processor. At this time, the control clock is output from clock generator 1.
When CK ₁ is generated, the inverter 8 outputs " ₁ " because the buffer D with R/S
Transmitted to FF7. At this time, since the buffer
will be applied. At this time, since "0" is being transmitted from the buffer D to the terminal D _p , the application of the control clock CK ₁ causes the R/S attached D.
FF7 outputs "0". This state is caused by the generation of control clocks CK ₂ and CK ₃ , but the AND circuit 3
is in the off state, control clock CK ₂ is not transmitted to D/FF7 with R/S, and control clock CK ₃ is not transmitted to D/FF7 with R/S.
The input NAND circuits 5 and 6 already contain “0”
Since the input is applied, this control clock
Since CK ₃ is also not transmitted to the D/FF7 with R/S, during this test period 1, the D/FF7 with R/S outputs "0", which is the driver.
It will be transmitted to terminal P via DV.

In the next test period 2, "1" is transmitted to buffers D and X, respectively. Moreover, as is clear from FIG. 6, the "1" applied to the buffers D and X is generated slightly before the control clock _CK1 is generated, and the inverter 8 outputs "0". Therefore, AND circuit 2 is in an off state. Therefore, the above control clock _CK1 is R.
Since the signal is not transmitted to the S-equipped D/FF7, the output of the R-S-equipped D/FF7 maintains the output "0" of test period 1 as it is. When the control clock CK ₂ is generated, it is transmitted to the D/FF 7 with R/S via the AND circuit 3 and the OR circuit 4. At this time, the control clock CK ₃ is not generated, and the "0" input is transmitted to the NAND circuits 5 and 6. As a result, the set terminal S and reset terminal R of the D and FF7 with R/S are respectively output. "1" will be applied. At this time, since "1" is being transmitted from the buffer D to the terminal D _p , the generation of the control clock CK ₂ causes the R/S equipped D/FF 7 to output "1". However, when the control clock _CK3 is generated next, the NAND circuit 6 outputs "0", so the DFF 7 with R/S is reset and outputs "0". As a result, during test period 2, a clock-like output as shown in FIG. 6 is generated at terminal D.

During test period 3, "1" is transmitted to buffer D and "0" is transmitted to buffer X. As a result, inverter 8 outputs "1" and AND circuit 2 is in the on state. Therefore the control clock
When CK ₁ occurs, the control clock CK ₁ passes through AND circuit 2 and OR circuit 4 to D/S with R/S.
Transmitted to FF7. At this time, the control clock _CK3
Since no has occurred, NAND circuits 5 and 6 each output "1". At this time, "1" is being transmitted from the buffer D to the terminal D _p , so in the test period 3, the control clock CK ₁ controls the R.S.
Appendix D/FF7 outputs "1". However, since "0" of buffer X is transmitted to AND circuit 3 and NAND circuits 5 and 6, the control clock
The occurrence of CK ₂ and CK ₃ does not change this condition.

In test period 4, "0" is transmitted to buffer D, and "1" is transmitted to buffer X. Therefore, the inverter 8 outputs "0" and turns off the AND circuit 2, so that the control clock _CK1 is blocked and is not transmitted to the R/S D/FF 7. Therefore, the output of D・FF7 with R・S is during the test period 4.
During the first period of , the state of test period 3 is maintained as it is and "1" is output. and control clock
When CK ₂ is generated, this control pulse CK ₂ is transmitted to the D/FF 7 with R/S via the AND circuit 3 and the OR circuit 4. At this time, the control clock
CK ₃ is not generated and the inputs of NAND circuits 5 and 6 are “0”
Therefore, these NAND circuits 5 and 6 each output "1". At this time, the terminal from buffer D
Since "0" is transmitted to D _p , the D/FF7 with R/S outputs "0". However, when the control clock _CK3 is generated, the NAND circuit 5 outputs "0", so the DFF 7 with R/S is set and outputs "1". Thus, in test period 4,
A negative clock as shown in FIG. 6 is generated at the terminal P.

Similarly, in test period 5, the buffer D
By transmitting "1" to and
During the test period 6, "0" is transmitted to the buffer D and the output is changed to the buffer X.
By transmitting "1" to buffers D and X, it is possible to generate an output that changes from "0" to "1" in the middle of the pattern, and in test period 7, by transmitting "0" to buffers D and The operation of the general signal input terminal can be performed.

FIG. 7 shows the state of the transmission signal to the terminal P in FIG. 6.

After all, in this way, during test periods 1 and 7, it is possible to give an input of "0" to the normal general signal input terminal, and in test period 3, it is possible to give an input of "1" to the general signal input terminal. Period 2
In test period 5, a positive clock with a narrow width can be given, and in test period 5, a positive clock rising state that changes from "1" to "0" can be given, and in test period 4, a narrow negative clock can be given. In the test period 6, a negative clock rising state changing from "0" to "1" can be provided.

[Effect of idea]

After all, according to the present invention, by selectively applying 2-bit control pattern signals "1" and "0" to the buffers D and X, not only the general input signal but also the clock signal can be selectively applied to the input terminal. is possible,
Furthermore, since it is possible to change the signal in the middle of the pattern, it is possible to provide a logic function testing device with a wide range of uses.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a conventional logic function test device, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a schematic diagram of an embodiment of the logic function test device of the present invention, and FIG. 4 is a detailed diagram of its control circuit. FIG. 5 is an explanatory diagram of the control clock, and FIGS. 6 and 7 are explanatory diagrams of its control state. In the figure, 1 is a control clock generator, 2 and 3 are AND circuits, 4 is an OR circuit, 5 and 6 are NAND circuits, and 7
D flip flop with reset/set,
8, 9 are inverters, 10, 10-1 to 10-n
indicate control circuits, respectively.

Claims (1)

[Claims for Utility Model Registration] A control circuit is provided with a plurality of terminals and a control circuit through which signals or clock signals are transmitted to a fixed logic circuit whose function is to be measured, and an input signal and a control signal are transmitted to the control circuit. In the logic function testing device which selectively controls the functions of the plurality of terminals by
Control clock CK ₁ , second control clock CK ₂ , third control clock CK 1
A clock generating means for generating a control clock CK ₃ , an input signal holding section D and a control signal holding section X to which an input signal is input, a first AND gate means 2, a second AND gate means 3, and a control circuit. ,
The first NAND gate means 5, the second NAND gate means 6, and the outputs of these AND gate means and NAND gate means are input, and when a logic "1" is input to the set terminal, a logic "1" is output, and the reset terminal is “0” when logic “0” is input to
A state holding means 7 and a terminal driver are provided, which output the input to the data terminal as is when logic "1" is input to the set terminal and the reset terminal, and a terminal driver, and the state holding means outputs the output of the input signal holding section. The output of the control signal holding section is input to the second AND gate means, and the inverted signal is input to the first AND gate means. The first control clock CK ₁ of the clock generating means is input to the first AND gate means, the second control clock CK ₂ is input to the second AND gate means, and the third control clock CK ₃ is input to the first AND gate means.
input to a NAND gate means and a second NAND gate means, outputs of the first and second AND gate means to the clock terminal of the state holding means, and an output of the first NAND gate means to the set terminal of the state holding means to the second NAND gate. A logic function testing device characterized in that the output of the means is inputted to a reset terminal of the state holding means, and the output of the state holding means is applied to the driver.