JPH02160391A - Test socket for semiconductor device with frame - Google Patents
Test socket for semiconductor device with frameInfo
- Publication number
- JPH02160391A JPH02160391A JP63314136A JP31413688A JPH02160391A JP H02160391 A JPH02160391 A JP H02160391A JP 63314136 A JP63314136 A JP 63314136A JP 31413688 A JP31413688 A JP 31413688A JP H02160391 A JPH02160391 A JP H02160391A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- frame
- positioning
- pins
- test socket
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000012360 testing method Methods 0.000 title claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
- Connecting Device With Holders (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、フレーム付半導体装置の電気試験用ソケット
に関し、詳しくはフラットパッケージ半導体装置の製造
工程においてリードフレームに半導体チップを搭載し樹
脂封止したのち、タイバーを切断した状態で試験を行う
ときに使用するソケットに関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a socket for electrical testing of a semiconductor device with a frame, and more specifically, a semiconductor chip is mounted on a lead frame and sealed with resin in the manufacturing process of a flat package semiconductor device. After that, it relates to sockets used when testing is performed with the tie bars disconnected.
従来、この種のソケットは、第３図（ａ）（ｂ）に示す
ように、°フレームの位置決め穴に対応する２本の位置
決めピンと、フレーム付半導体装置のリードを位置決め
する位置決め枠１０−１〜１０−４とを有していた。Conventionally, this type of socket has two positioning pins corresponding to the positioning holes of the frame and a positioning frame 10-1 for positioning the leads of the frame-equipped semiconductor device, as shown in FIGS. 3(a) and 3(b). ~10-4.
上述した従来のフレーム付半導体装置の試験用ソケット
は、半導体装置のリードを直接位置決めする構造となっ
ているので、リードの変形等を起こすという欠点がある
。The above-described conventional frame-equipped test socket for semiconductor devices has a structure in which the leads of the semiconductor device are directly positioned, and therefore has the disadvantage that the leads may be deformed.
本発明は、複数のリードを備えたフラットパッケージ半
導体装置に吊りピンを介して取付けられた金属フレーム
を有するフレーム付半導体装置の試験用ソケットにおい
て、前記金属フレームに設けられた位置決め穴又はスプ
ロケット穴に対応して設けられた少なくとも３個の位置
決めピンか設けられているというものである。The present invention provides a test socket for a framed semiconductor device having a metal frame attached to a flat package semiconductor device with a plurality of leads via hanging pins, in which a positioning hole or a sprocket hole provided in the metal frame is provided. At least three correspondingly provided positioning pins are provided.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ＞及び（ｂ＞はそれぞれ本発明の一実施例の
上面図及び側面図である。FIG. 1 (a> and (b>) are a top view and a side view, respectively, of an embodiment of the present invention.
この実施例は、第２図に示すような、複数のり−ド６を
備えたフラットパッケージ半導体装置に吊りピン７を介
して取付けられた金属フレーム４を有するフレーム付半
導体装置の試験用ソケットにおいて、金属フレーム４に
設けられた位置決め六８−１．８−２及びスプロケット
穴９−１．９−２ＣＲ密にはスプロケット穴の半分）に
対応して設けられた４個の位置決めピン２−１〜２−４
が設けられているというものである。This embodiment is a test socket for a framed semiconductor device having a metal frame 4 attached via hanging pins 7 to a flat package semiconductor device equipped with a plurality of boards 6, as shown in FIG. Four positioning pins 2-1~ provided corresponding to the positioning pin 68-1.8-2 provided on the metal frame 4 and the sprocket hole 9-1.9-2CR (more specifically, half of the sprocket hole) 2-4
is provided.
フレーム付半導体装置をこのようなソケットに装着し、
リードと接触子を接触させ（適当な重しをのせてもよい
）た状態で、各接触子には図示しない配線から電気信号
を印加して試験を行なう。Attach a semiconductor device with a frame to such a socket,
The test is performed by applying an electric signal to each contact from wiring (not shown) while the lead and the contact are in contact (an appropriate weight may be placed on them).
最終的には吊りピン７を切除するとフラットパッケージ
半導体装置が得られる。Finally, by removing the hanging pins 7, a flat package semiconductor device is obtained.
以上説明したように本発明によると、位置決めピンによ
りフレームで位置決めを行うことができるので、半導体
装置のリードの変形等の損傷をなくすことができ、歩留
りが向上する効果がある。As described above, according to the present invention, positioning can be performed using the frame using the positioning pins, so damage such as deformation of the leads of the semiconductor device can be eliminated, and the yield can be improved.
第１図（ａ）及び（ｂ）はそれぞれ本発明の一実施例の
上面図及び側面図、第２図はフレーム付半導体装置の上
面図、第３図（ａ）及び（ｂ）はそれぞれ従来例を示す
上面図及び側面図である。
１・・・ソケット本体、２−１〜２−４・・・位置決め
ピン、３・・・接触子、４・・・金属フレーム、５・・
・封止樹脂、６・・・リード、７・・・吊りピン、８−
１．８２・・・位置決め穴、９−１．９−２・・・スプ
ロケット穴、１０−１〜１０−４・・・位置決め枠。1(a) and (b) are respectively a top view and a side view of an embodiment of the present invention, FIG. 2 is a top view of a semiconductor device with a frame, and FIGS. 3(a) and (b) are respectively a conventional It is a top view and a side view which show an example. 1... Socket body, 2-1 to 2-4... Positioning pin, 3... Contact, 4... Metal frame, 5...
・Sealing resin, 6...Lead, 7...Hanging pin, 8-
1.82...Positioning hole, 9-1.9-2...Sprocket hole, 10-1 to 10-4...Positioning frame.
Claims (1)
吊りピンを介して取付けられた金属フレームを有するフ
レーム付半導体装置の試験用ソケットにおいて、前記金
属フレームに設けられた位置決め穴又はスプロケット穴
に対応して設けられた少なくとも３個の位置決めピンが
設けられていることを特徴とするフレーム付半導体装置
の試験用ソケット。In a test socket for a framed semiconductor device having a metal frame attached to a flat package semiconductor device with a plurality of leads via hanging pins, a test socket is provided corresponding to a positioning hole or a sprocket hole provided in the metal frame. A test socket for a semiconductor device with a frame, characterized in that at least three positioning pins are provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314136A JPH02160391A (en) | 1988-12-12 | 1988-12-12 | Test socket for semiconductor device with frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314136A JPH02160391A (en) | 1988-12-12 | 1988-12-12 | Test socket for semiconductor device with frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02160391A true JPH02160391A (en) | 1990-06-20 |
Family
ID=18049669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63314136A Pending JPH02160391A (en) | 1988-12-12 | 1988-12-12 | Test socket for semiconductor device with frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02160391A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106036A (en) * | 1993-10-07 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Positioning device for electronic parts in socket |
-
1988
- 1988-12-12 JP JP63314136A patent/JPH02160391A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106036A (en) * | 1993-10-07 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Positioning device for electronic parts in socket |
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