JPH04304659A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH04304659A
JPH04304659A JP3068209A JP6820991A JPH04304659A JP H04304659 A JPH04304659 A JP H04304659A JP 3068209 A JP3068209 A JP 3068209A JP 6820991 A JP6820991 A JP 6820991A JP H04304659 A JPH04304659 A JP H04304659A
Authority
JP
Japan
Prior art keywords
leadless chip
wiring
integrated circuit
circuit device
chip carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3068209A
Other languages
Japanese (ja)
Inventor
Norimasa Takada
高田　教正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3068209A priority Critical patent/JPH04304659A/en
Publication of JPH04304659A publication Critical patent/JPH04304659A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Abstract

PURPOSE:To improve a mounting density by so connecting two leadless chip carriers to each other that rear surfaces are opposed, and then placing them on a supporting board. CONSTITUTION:A first leadless chip carrier 21 is mechanically and electrically connected to a wiring 11 on the rear surface of a second leadless chip carrier 22. The carrier 21 is so disposed as to be introduced into a spot faced part of a supporting board 9. Here, the carrier 21 is electrically connected to a wiring 10 of the board 9 through a rear surface electrode 32 of the carrier 22. Thus, the mounting density can be raised nearly twice as large as that of conventional structure.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は混成集積回路装置に関し
、特に高い実装密度を実現する混成集積回路装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device that achieves high packaging density.

【０００２】0002

【従来の技術】図３（ａ），（ｂ）は通常のリードレス
チップキャリアの斜視図およびそのＡ−Ａ′断面図であ
る。端面スルーホール電極１を有する基板２は、樹脂枠
３の内側が封止樹脂４で覆われている。また、端面スル
ーホール電極１につながる表面の配線５は、ボンディン
グワイヤー６を介してＩＣペレット７に接続されている
。ＩＣペレット７は樹脂枠３で制限される領域内に塗布
される封止樹脂４で覆われている。また、裏面には端面
スルーホール電極１につながる裏面電極８が配置されて
いる。2. Description of the Related Art FIGS. 3(a) and 3(b) are a perspective view and a sectional view taken along line AA' of a conventional leadless chip carrier. In a substrate 2 having an end face through-hole electrode 1, the inside of a resin frame 3 is covered with a sealing resin 4. Further, the wiring 5 on the front surface connected to the end surface through-hole electrode 1 is connected to the IC pellet 7 via a bonding wire 6. The IC pellet 7 is covered with a sealing resin 4 applied within the area limited by the resin frame 3. Further, a back electrode 8 connected to the end surface through-hole electrode 1 is arranged on the back surface.

【０００３】従来の混成集積回路装置としては、図４の
ようにリードレスチップキャリア２１，２２を少なくと
も２１回以上搭載したものがある。これらリードレスチ
ップキャリア２１，２２は、支持基板９上の配線１０に
各々の裏面電極３１，３２を介して接続されている。As a conventional hybrid integrated circuit device, there is one in which leadless chip carriers 21 and 22 are mounted at least 21 times as shown in FIG. These leadless chip carriers 21 and 22 are connected to wiring 10 on the support substrate 9 via back electrodes 31 and 32, respectively.

【０００４】0004

【発明が解決しようとする課題】上述した従来の混成集
積回路装置では、リードレスチップキャリア２１，２２
下側には支持基板２の配線１０だけがあり、その他の部
品を配置することができないため、高い実装密度が得ら
れないという欠点がある。最近のリードレスチップキャ
リアの多ピン化に伴い、リードレスチップキャリアが大
きくなる傾向にあり、ますます実装密度の向上が困難に
なってきている。[Problems to be Solved by the Invention] In the conventional hybrid integrated circuit device described above, leadless chip carriers 21, 22
There is only the wiring 10 of the support substrate 2 on the lower side, and other components cannot be arranged, so there is a drawback that high packaging density cannot be obtained. With the recent increase in the number of pins in leadless chip carriers, leadless chip carriers tend to become larger, making it increasingly difficult to improve packaging density.

【０００５】本発明の目的は、このような問題を解決し
、実装密度をほぼ２倍近く高めた混成集積回路装置を提
供することにある。An object of the present invention is to solve these problems and to provide a hybrid integrated circuit device in which the packaging density is almost doubled.

【０００６】[0006]

【課題を解決するための手段】本発明の混成集積回路装
置の構成は、第１のリードレスチップキャリアは支持基
板上に設けた凹部に裏側にして配設され、かつその裏面
電極を介して前記支持基板の配線上に機械的及び電気的
に接続され、第２のリードレスチップキャリアは前記第
１のリードレスチップキャリアの裏面配線上に機械的お
よび電気的に接続されていることを特徴とする。[Means for Solving the Problems] In the configuration of the hybrid integrated circuit device of the present invention, a first leadless chip carrier is disposed on the back side in a recess provided on a support substrate, and The second leadless chip carrier is mechanically and electrically connected to the wiring of the support substrate, and the second leadless chip carrier is mechanically and electrically connected to the backside wiring of the first leadless chip carrier. shall be.

【０００７】本発明において、凹部が支持基板の貫通孔
であることもできる。In the present invention, the recess can also be a through hole in the support substrate.

【０００８】[0008]

【実施例】図１は本発明の第１の実施例の断面図である
。第１のリードレスチップキャリア２１は第２のリード
レスチップキャリア２２の裏面の配線１１に、機械的及
び電気的に接続されている。この構造は、例えばＱＦＰ
などのＩＣパッケージでは実現できない構造である。 第２のリードレスチップキャリア２２は支持基板９の座
ぐり部に入るように配置され裏面電極３２を介して支持
基板９の配線１０に機械的及び電気的に接続されている
。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a first embodiment of the present invention. The first leadless chip carrier 21 is mechanically and electrically connected to the wiring 11 on the back surface of the second leadless chip carrier 22. This structure is, for example, a QFP
This is a structure that cannot be realized with other IC packages. The second leadless chip carrier 22 is placed in the counterbore of the support substrate 9 and is mechanically and electrically connected to the wiring 10 of the support substrate 9 via the back electrode 32 .

【０００９】本実施例ではリードレスチップキャリアが
搭載されているのと反対の支持基板の面にも配線できる
という利点を有する。This embodiment has the advantage that wiring can also be performed on the surface of the supporting substrate opposite to that on which the leadless chip carrier is mounted.

【００１０】図２は、本発明の第２の実施例の断面図で
ある。第１の実施例と異なるのは支持基板９に貫通穴が
形成されている点である。本実施例では支持基板９を薄
くでき、薄型化に向いている。FIG. 2 is a cross-sectional view of a second embodiment of the invention. The difference from the first embodiment is that a through hole is formed in the support substrate 9. In this embodiment, the support substrate 9 can be made thinner, and is suitable for thinning.

【００１１】これら実施例では、１個のリードレスチッ
プキャリアに１個のＩＣペレットが搭載された例で説明
したが、複数個のＩＣペレットが１個のリードレスチッ
プキャリアに搭載される場合はリードレスチップキャリ
アの大きさが大きくなる傾向にあり、この場合にも本発
明は同様に適用でき、従来例に比べて実装密度向上の効
果は著しい。In these embodiments, one IC pellet is mounted on one leadless chip carrier, but when a plurality of IC pellets are mounted on one leadless chip carrier, The size of leadless chip carriers tends to increase, and the present invention can be similarly applied to this case as well, and the effect of improving the packaging density is remarkable compared to the conventional example.

【００１２】0012

【発明の効果】以上説明したように本発明は、２つのリ
ードレスチップキャリアを裏面同志向き合うようにお互
いに接続した後、支持基板に搭載しているので、従来の
構造に比べて実装密度か２倍近く高くなるという効果を
有する。[Effects of the Invention] As explained above, in the present invention, two leadless chip carriers are connected to each other so that their back sides face each other, and then mounted on a support substrate, so the packaging density is lower than that of the conventional structure. It has the effect of becoming nearly twice as expensive.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明の第１の実施例の断面図。FIG. 1 is a sectional view of a first embodiment of the invention.

【図２】本発明の第２の実施例の断面図。FIG. 2 is a sectional view of a second embodiment of the invention.

【図３】（ａ），（ｂ）はリードレスチップキャリアの
斜視図およびそのＡ−Ａ′断面図。FIGS. 3(a) and 3(b) are a perspective view of a leadless chip carrier and a sectional view thereof taken along line AA'.

【図４】従来例の混成集積回路装置の断面図。FIG. 4 is a sectional view of a conventional hybrid integrated circuit device.

【符号の説明】[Explanation of symbols]

１　　　　端面スルーホール電極 ２　　　　基板 ３　　　　樹脂枠 ４　　　　封止樹脂 ５　　　　配線 ６　　　　ボンディングワイヤー ７　　　　ＩＣペレット ８　　　　裏面電極 ９　　　　支持基板 １０，１１　　　　配線 ２１，２２　　　　リードレスチップキャリア３１，３
２　　　　裏面電極1 End surface through-hole electrode 2 Substrate 3 Resin frame 4 Sealing resin 5 Wiring 6 Bonding wire 7 IC pellet 8 Back electrode 9 Support substrate 10, 11 Wiring 21, 22 Leadless chip carrier 31, 3
2 Back electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】　　第１のリードレスチップキャリアは支
持基板上に設けた凹部に裏側にして配設され、かつその
裏面電極を介して前記支持基板の配線上に機械的及び電
気的に接続され、第２のリードレスチップキャリアは前
記第１のリードレスチップキャリアの裏面配線上に機械
的および電気的に接続されていることを特徴とする混成
集積回路装置。Claim 1: A first leadless chip carrier is disposed on the back side in a recess provided on a support substrate, and is mechanically and electrically connected to wiring on the support substrate via its back electrode. . A hybrid integrated circuit device, wherein the second leadless chip carrier is mechanically and electrically connected to the wiring on the back surface of the first leadless chip carrier. 【請求項２】　　支持基板の凸部がその支持基板に設け
られた貫通孔である請求項１記載の混成集積回路装置。2. The hybrid integrated circuit device according to claim 1, wherein the convex portion of the support substrate is a through hole provided in the support substrate.
JP3068209A 1991-04-01 1991-04-01 Hybrid integrated circuit device Pending JPH04304659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3068209A JPH04304659A (en) 1991-04-01 1991-04-01 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3068209A JPH04304659A (en) 1991-04-01 1991-04-01 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04304659A true JPH04304659A (en) 1992-10-28

Family

ID=13367182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3068209A Pending JPH04304659A (en) 1991-04-01 1991-04-01 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04304659A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8270157B2 (en) 2009-12-28 2012-09-18 Kabushiki Kaisha Toshiba Electronic device
JP2015153886A (en) * 2014-02-13 2015-08-24 コーア株式会社 Component built-in substrate
JP2016529729A (en) * 2013-08-28 2016-09-23 キュベイコン リミテッド Semiconductor die and package jigsaw submount

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8270157B2 (en) 2009-12-28 2012-09-18 Kabushiki Kaisha Toshiba Electronic device
JP2016529729A (en) * 2013-08-28 2016-09-23 キュベイコン リミテッド Semiconductor die and package jigsaw submount
JP2015153886A (en) * 2014-02-13 2015-08-24 コーア株式会社 Component built-in substrate

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