JPH03255657A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH03255657A
JPH03255657A JP2054119A JP5411990A JPH03255657A JP H03255657 A JPH03255657 A JP H03255657A JP 2054119 A JP2054119 A JP 2054119A JP 5411990 A JP5411990 A JP 5411990A JP H03255657 A JPH03255657 A JP H03255657A
Authority
JP
Japan
Prior art keywords
chips
board
bonding method
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2054119A
Other languages
Japanese (ja)
Inventor
Akio Koyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2054119A priority Critical patent/JPH03255657A/en
Publication of JPH03255657A publication Critical patent/JPH03255657A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

PURPOSE: To enable components to be densely mounted on a board by a method wherein two IC chips are mounted on the board making their rear sides overlap each other, and one of them is connected through a flip chip bonding method and the other is connected through a wire bonding method.
CONSTITUTION: Two IC chips 3 bonded together through a non-conductive adhesive agent 5 making their rear sides overlap each other are mounted on a board 1. The IC chips 3 are mounted on the board 1 through such a way that in one of the IC chips 3, a metallized electrode 2 provided onto the board 1 is electrically connected to a metallized electrode 12 formed on the chip 3 with a bump 6 through a flip chip bonding method, and in the other of the IC chips 3, the metallized electrodes 2 and 12 are electrically connected together with a gold wire 4 through a wire bonding method.
COPYRIGHT: (C)1991,JPO&Japio
JP2054119A 1990-03-05 1990-03-05 Hybrid integrated circuit device Pending JPH03255657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2054119A JPH03255657A (en) 1990-03-05 1990-03-05 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2054119A JPH03255657A (en) 1990-03-05 1990-03-05 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH03255657A true JPH03255657A (en) 1991-11-14

Family

ID=12961712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2054119A Pending JPH03255657A (en) 1990-03-05 1990-03-05 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH03255657A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327325A (en) * 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5767570A (en) * 1993-03-18 1998-06-16 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure
KR20020016278A (en) * 2000-08-25 2002-03-04 듀흐 마리 에스. Improved Method of Mounting Chips in Flip Chip Technology Process
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US7015063B2 (en) 1998-03-31 2006-03-21 Micron Technology, Inc. Methods of utilizing a back to back semiconductor device module
US7906852B2 (en) 2006-12-20 2011-03-15 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327325A (en) * 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5767570A (en) * 1993-03-18 1998-06-16 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US6337227B1 (en) 1996-02-20 2002-01-08 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6165815A (en) * 1996-02-20 2000-12-26 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6989285B2 (en) 1996-05-20 2006-01-24 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US7371612B2 (en) 1996-05-20 2008-05-13 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US7015063B2 (en) 1998-03-31 2006-03-21 Micron Technology, Inc. Methods of utilizing a back to back semiconductor device module
US7057291B2 (en) * 1998-03-31 2006-06-06 Micron Technology, Inc. Methods for securing vertically mountable semiconductor devices in back-to back relation
US7282789B2 (en) 1998-03-31 2007-10-16 Micron Technology, Inc. Back-to-back semiconductor device assemblies
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR20020016278A (en) * 2000-08-25 2002-03-04 듀흐 마리 에스. Improved Method of Mounting Chips in Flip Chip Technology Process
US7906852B2 (en) 2006-12-20 2011-03-15 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same

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