JPH01244655A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01244655A
JPH01244655A JP7237388A JP7237388A JPH01244655A JP H01244655 A JPH01244655 A JP H01244655A JP 7237388 A JP7237388 A JP 7237388A JP 7237388 A JP7237388 A JP 7237388A JP H01244655 A JPH01244655 A JP H01244655A
Authority
JP
Japan
Prior art keywords
electrodes
package body
package
outer leads
surface side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7237388A
Other languages
Japanese (ja)
Inventor
Masatoshi Yasunaga
雅敏 安永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7237388A priority Critical patent/JPH01244655A/en
Publication of JPH01244655A publication Critical patent/JPH01244655A/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To lengthen pitches, and to obtain a package capable of easily conducting an electrical test from the surface side by forming electrodes onto the surface of a package body to a plane shape. CONSTITUTION:An electrical test can be performed from the surface side at long pitches by outer leads by electrodes 3 shaped onto the surface of a package body 1. The outer leads take a gull wing type, but a J lead, an inserting pin, a leadless type, etc., may be used as the outer leads. The electrodes 3 take a circular shape, but a rectangular shape may be employed as the electrodes 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体素子を搭載するノ(ツケージに関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cage for mounting a semiconductor element.

〔従来の技術〕[Conventional technology]

第2図は従来のノ(ツケージを示す斜視図であり、巾は
パッケージ本体、121はこれに取り付けられた外部リ
ードである。
FIG. 2 is a perspective view showing a conventional package, where the width is the package body and 121 is the external lead attached to it.

次に動作について説明する。)くツケージ本体に取り付
けられた外部リード(21によってプIlント基板やソ
ケット等と電気的に接続される。
Next, the operation will be explained. ) It is electrically connected to a printed circuit board, a socket, etc. by an external lead (21) attached to the cage body.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のパッケージは以上のように構成されているので、
電気試験を行なう場合に外部リードと同じピッチのソケ
ットやプローブカードが必要で、また、Jリードやリー
ドレスタイプのパッケージでは表面側からの針当てが困
難であるなどの問題点があった。
Conventional packages are structured as above, so
When conducting electrical tests, sockets and probe cards with the same pitch as the external leads are required, and J-lead and leadless type packages have problems such as difficulty in applying needles from the front side.

この発明は上記のような間f点を解消するためになされ
たもので、外部リードより緩いピッチで、かつ表面側か
ら容易に電気試験が行なうことができるパッケージを得
ること全目的とする0 〔課蓋を解決するための手段〕 この発明に係るパッケージは、パッケージ本体表面に1
[極を設けたものである。
This invention was made in order to eliminate the above-mentioned f-point, and its overall purpose is to obtain a package that has a looser pitch than the external leads and that allows easy electrical testing from the surface side. Means for Solving Problems] The package according to the present invention has one on the surface of the package body.
[It has poles.]

〔作用〕[Effect]

この発明における電極は、パッケージ本体表面に面状に
設けられることにより、ピッチが緩和され、かつ表面側
からの電気試験が容易に女る。
By providing the electrodes in the present invention in a planar manner on the surface of the package body, the pitch is relaxed and electrical testing from the surface side can be easily performed.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について睨明する。第1
図にお−で、…はパッケージ本体、(2)ぽこれに取り
付けられた外部リード、131はパッケージ本体…の表
面に設けられた電極である。
An embodiment of the present invention will be explained below with reference to the drawings. 1st
In the figure, ... is the package body, (2) an external lead attached to the port, and 131 is an electrode provided on the surface of the package body.

次に動作について説明する。41図において、パッケー
ジ本体(110表面に設けられた電極+31によって、
外部リードより緩いヒーツチで、かつ表面側から電気試
験を行なう。
Next, the operation will be explained. In Figure 41, the electrode +31 provided on the surface of the package body (110)
Perform the electrical test from the surface side with a heat chain that is looser than the external lead.

なお、上記実施例を示す第1図では外部y−ドげガルウ
ィングタイプであるが、Jリード。
In addition, in FIG. 1 showing the above embodiment, the external Y-doggull wing type is used, but it is a J lead.

挿入ビン、リードレスタイプ等であってもよい。An insertion bottle, leadless type, etc. may be used.

また、第1図では電極(31は円形であるが矩形でもよ
い。
Further, although the electrode (31 is circular in FIG. 1), it may be rectangular.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、パッケージ本体表面
K[極を設けたので、緩いピッチで、かつ表面側より容
易IC11E気試験を行なうことができる効果がある。
As described above, according to the present invention, since the poles are provided on the surface of the package body, the IC11E test can be easily performed at a loose pitch and from the surface side.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例によるパッケージを示す斜
視図、@2図は従来のパッケージを示す斜視図である。 tll ijパッケージ本体、(21は外部リード、(
引げ電極である。 なお、図中、同一符号は同一、又は相当部分を示す@
FIG. 1 is a perspective view showing a package according to an embodiment of the present invention, and FIG. 2 is a perspective view showing a conventional package. tll ij package body, (21 is external lead, (
It is a pull electrode. In addition, in the figures, the same symbols indicate the same or equivalent parts@

Claims (1)

【特許請求の範囲】[Claims]  半導体素子を搭載するパッケージにおいて、パッケー
ジ本体表面に電極を設けたことを特徴とする半導体装置
A semiconductor device characterized in that, in a package mounting a semiconductor element, electrodes are provided on the surface of the package body.
JP7237388A 1988-03-26 1988-03-26 Semiconductor device Pending JPH01244655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7237388A JPH01244655A (en) 1988-03-26 1988-03-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7237388A JPH01244655A (en) 1988-03-26 1988-03-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01244655A true JPH01244655A (en) 1989-09-29

Family

ID=13487437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7237388A Pending JPH01244655A (en) 1988-03-26 1988-03-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01244655A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259367A (en) * 1992-03-12 1993-10-08 Nec Corp Flat ic package
US5808357A (en) * 1992-06-02 1998-09-15 Fujitsu Limited Semiconductor device having resin encapsulated package structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259367A (en) * 1992-03-12 1993-10-08 Nec Corp Flat ic package
US5808357A (en) * 1992-06-02 1998-09-15 Fujitsu Limited Semiconductor device having resin encapsulated package structure
US6031280A (en) * 1992-06-02 2000-02-29 Fujitsu Limited Semiconductor device having resin encapsulated package structure
US6271583B1 (en) 1992-06-02 2001-08-07 Fujitsu Limited Semiconductor device having resin encapsulated package structure

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