JPH11312781A - Bridge type semiconductor device and its manufacture - Google Patents

Bridge type semiconductor device and its manufacture

Info

Publication number
JPH11312781A
JPH11312781A JP13449998A JP13449998A JPH11312781A JP H11312781 A JPH11312781 A JP H11312781A JP 13449998 A JP13449998 A JP 13449998A JP 13449998 A JP13449998 A JP 13449998A JP H11312781 A JPH11312781 A JP H11312781A
Authority
JP
Japan
Prior art keywords
semiconductor chip
die pad
lead frame
lead
bridge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13449998A
Other languages
Japanese (ja)
Inventor
Koji Furusato
広治 古里
Mitsumasa Sasaki
光政 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP13449998A priority Critical patent/JPH11312781A/en
Publication of JPH11312781A publication Critical patent/JPH11312781A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To improve productivity by holding a semiconductor chip between two lead frames, to which units in bridge units are connected continuously in the X and Y directions and which have the same or approximately the same shape, and soldering the semiconductor chip. SOLUTION: A first lead frame, in which solder, etc., are printed beforehand onto die pad sections, is placed on a jig, etc., and diode chips D2, D3 and D1, D4 are incorporated into the die pad sections 1a, 2a while polarity is made to differ respectively. A second lead frame is put on so that the die pad sections 3a, 4a of the second lead frame having the same shape or approximately the same shape as the first lead frame are orthogonally crossed with the die pad sections 1a, 2a of the first lead frame. Since a bridge circuit is formed under the state, the bridge circuit is joined and unified by soldering by heating. Accordingly, a plurality of the bridge type semiconductor devices can be assembled simultaneously only by the semiconductor chip and solder and the two lead frames having approximately the same shape, and productivity is improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】本発明は、電気及び電子機器等に適用され
るブリッジ型半導体装置の構造及びその製造方法に関す
る。 (2)
[0001] The present invention relates to a structure of a bridge type semiconductor device applied to electric and electronic equipment and the like, and a method of manufacturing the same. (2)

【0002】[0002]

【従来の技術】この種の従来装置の製法は、実用新案登
録第2566480号に詳述されているように、1枚の
リードフレーム(金属板)上の夫々ダイパッド部に各半
導体チップを導電極性(N側又はP側)を揃えて搭載
し、更に夫々チップ間に接続子を配置組み立て、これを
はんだ付けした後、トランスファーモールド法等により
樹脂封止している。
2. Description of the Related Art As described in detail in Japanese Utility Model Registration No. 2566480, a method of manufacturing a conventional device of this kind is to attach each semiconductor chip to a die pad portion on a single lead frame (metal plate). (N-side or P-side) are aligned and mounted. Further, connectors are arranged and assembled between the chips, soldered, and then sealed with a resin by a transfer molding method or the like.

【0003】[0003]

【発明が解決しようとする課題】上記の従来方法では半
導体チップの導電極性を揃えて組み込むことが可能なた
めこの点で組み立て工数を大幅に向上できる利点がある
が、夫々半導体チップ間を個々の接続子により接続する
工程を要するために同時大量生産方法としては問題があ
り、又、製品の形状が大きくなる難点がある。
In the above-mentioned conventional method, since the semiconductor chips can be incorporated with the same conductivity polarity, there is an advantage that the number of assembling steps can be greatly improved in this respect. There is a problem as a simultaneous mass production method because a step of connecting with a connector is required, and there is a problem that the shape of the product becomes large.

【0004】本発明は上記の問題点に鑑み、近年の電子
機器の小型化、高信頼、低価格化に適応し得る安定且つ
量産に適した生産性の高い製造方法及び装置の提供を目
的とする。
SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a stable production method and apparatus suitable for mass production that can be adapted to miniaturization, high reliability and low cost of electronic equipment in recent years. I do.

【0005】[0005]

【課題を解決するための手段】本発明は、X方向及びY
方向にブリッジ単位ユニットが連接された同一形状又は
略同一形状の2枚のリードフレーム間に半導体チップを
挟持する如く組み立てはんだ付けするようにしたもので
ある。また、半導体チップが組み立てられた状態で、リ
ードフレームの一部を除去することにより、1枚の状態
と同様の構造となり、生産性を高められる。除去方法は
レーザを用いることにより、半導体チップに機械的スト
レスを与えることなく、切断が可能となる。
SUMMARY OF THE INVENTION The present invention is directed to an X direction and a Y direction.
A semiconductor chip is sandwiched between two lead frames of the same shape or substantially the same shape in which bridge unit units are connected in the direction, and soldering is performed. Further, by removing a part of the lead frame in a state where the semiconductor chip is assembled, a structure similar to that of a single chip is obtained, and productivity can be improved. By using a laser as a removing method, cutting can be performed without giving a mechanical stress to the semiconductor chip.

【0006】(3)(3)

【発明の実施の形態】請求項1の発明は、互いに平行状
態に配置されると共に、間隔を設けて2つの半導体チッ
プを搭載するスペースを持つダイパッド部と、これと一
体の端子部を備えた金属板ユニットをXY方向に複数個
連接した第1のリードフレーム及び第2のリードフレー
ムの夫々ダイパッド間に半導体チップを挟持してはんだ
付けするようにしたことを特徴とするブリッジ型半導体
装置の製造方法を提供するもので、これによりブリッジ
ダイオードの量産を可能にする。
According to the first aspect of the present invention, there is provided a die pad portion which is arranged in parallel with each other and has a space for mounting two semiconductor chips at intervals, and a terminal portion integral with the die pad portion. A method of manufacturing a bridge type semiconductor device, wherein a semiconductor chip is sandwiched and soldered between die pads of a first lead frame and a second lead frame in which a plurality of metal plate units are connected in the X and Y directions. A method is provided, which enables mass production of bridge diodes.

【0007】請求項2の発明は、樹脂封止工程を付加す
ることにより樹脂封止型ブリッジダイオードの量産を可
能にした。請求項3の発明は、樹脂封止工程に先立って
一方のリードフレームの一部をレーザ切断で除去する工
程を含むブリッジ型半導体装置の製造方法を提供するも
ので、これによりトランスファーモールド時の樹脂流れ
をスムーズにして樹脂の充填漏れを防ぎ、製品信頼性の
向上を図る。
The invention of claim 2 enables mass production of a resin-sealed bridge diode by adding a resin-sealing step. The invention according to claim 3 provides a method for manufacturing a bridge type semiconductor device including a step of removing a part of one of the lead frames by laser cutting prior to a resin sealing step. Smooth the flow to prevent resin leakage and improve product reliability.

【0008】請求項4の発明は、半導体チップのはんだ
付け後、第1及び第2リードフレームをブリッジ単位ユ
ニットに分割する切断工程を含むブリッジ型半導体装置
の製造方法を提供するもので、これにより分割時の半導
体チップへのダメージを防止する。
According to a fourth aspect of the present invention, there is provided a method of manufacturing a bridge type semiconductor device including a cutting step of dividing the first and second lead frames into bridge unit units after soldering the semiconductor chip. Prevents damage to the semiconductor chip at the time of division.

【0009】請求項5の発明は、一方の平行配置された
ダイパッド部に導電極性を異にして搭載された第1第2
の半導体チップ及び第3第4の半導体チップと、該半導
体チップ上に該ダイパッド部と略直角方向に平行配置さ
れた他方のダイパッド部と、該一方のダイパッド部から
伸張する第1、第2のリード端子と、他方のダイパッド
部から該リード端子と反対方向に伸張する第3、第4の
リード端子と、該ダイパッド部及び半導体チップと、該
リード端子の一部を封止する樹脂部を (4) 備えたブリッジ型半導体装置を提供する。
According to a fifth aspect of the present invention, there is provided a first and second die pads which are mounted with different conductive polarities on one of the die pads arranged in parallel.
Semiconductor chip, the third and fourth semiconductor chips, the other die pad portion disposed on the semiconductor chip in a direction substantially perpendicular to the die pad portion, and the first and second semiconductor chips extending from the one die pad portion. The lead terminal, the third and fourth lead terminals extending from the other die pad portion in the opposite direction to the lead terminal, the die pad portion, the semiconductor chip, and the resin portion for sealing a part of the lead terminal are referred to as ( 4) To provide a bridge-type semiconductor device provided.

【0010】[0010]

【実施例】図1、図2及び図3は本発明の一実施例を示
すブリッジ型半導体装置の平面図、側面図及び電気的等
価回路図で、各図においてD1〜D4は半導体(ダイオ
ード)チップ、1〜4はリード端子、16は樹脂部であ
る。又、リード端子3、4及びこれと夫々一体化された
ダイパッド部3a、4aは略斜め方向に平行状態に配置
され、各ダイパッド部3a、4aには間隔を設けて2つ
の半導体チップD1、D4又はD2、D3を搭載するス
ペースを持ち、後述する一方のリードフレームから分割
される。又、装置の裏面側のリード端子1、2も同様な
ダイパッド部1a、2aを有し、他方のリードフレーム
から分割される。そして各ダイパッド3a、4a及び1
a、2a間には導電極性(P又はN)の異なる如く半導
体チップD1〜D4が挟持されており、この構造は所謂
小型薄型の表面実装タイプ(SMD)を示す。因みにこ
の実施例構造は、縦が約5mm、横が約4mm、高さが約
1.5mmの形状を持つ。
1, 2 and 3 are a plan view, a side view and an electrical equivalent circuit diagram of a bridge type semiconductor device showing an embodiment of the present invention, wherein D 1 to D 4 are semiconductors (diodes). Chips, 1 to 4 are lead terminals, and 16 is a resin part. The lead terminals 3 and 4 and the die pads 3a and 4a integrated with the lead terminals 3 and 4 are disposed in a substantially oblique direction in parallel with each other. Alternatively, it has a space for mounting D2 and D3, and is divided from one lead frame described later. The lead terminals 1 and 2 on the back side of the device also have similar die pad portions 1a and 2a, and are separated from the other lead frame. And each die pad 3a, 4a and 1
Semiconductor chips D1 to D4 are sandwiched between a and 2a so as to have different conductive polarities (P or N), and this structure is a so-called small and thin surface mount type (SMD). Incidentally, the structure of this embodiment has a shape of about 5 mm in length, about 4 mm in width, and about 1.5 mm in height.

【0011】図4、図5は本発明に適用するリードフレ
ームの構造を示し、各(a)図は平面図、(b)図は部分的
拡大図である。図中Aは一方のリードフレーム、Bは他
方のリードフレームで一方のリードフレームAにおいて
5及び5aは、枠体を兼ねたサイドレール、6及び6a
はパイロット穴、又AUは該枠体内の電極板単位ユニット
でリード端子1及び2と略平行配置されたダイパッド部
1a、1bを持つ。そしてこの単位ユニットは枠体内で
X方向(矢印)及びY方向に複数個連接されている。
4 and 5 show the structure of a lead frame applied to the present invention. FIG. 4 (a) is a plan view and FIG. 4 (b) is a partially enlarged view. In the drawing, A is one lead frame, B is the other lead frame, and in one lead frame A, 5 and 5a are side rails serving also as a frame, 6 and 6a.
Denotes a pilot hole, and AU has a die pad unit 1a, 1b which is an electrode plate unit in the frame and is arranged substantially parallel to the lead terminals 1 and 2. A plurality of the unit units are connected in the X direction (arrow) and the Y direction in the frame.

【0012】次に図5の他方のリードフレームBもフレ
ームAと同等サイドレール7、7aとパイロット穴8、
8aと単位ユニットBUを有する。尚、ユニットBUに
おいてダイパッド部3a、4bは略水平方向に平行状態
に配置されている。
Next, the other lead frame B in FIG.
8a and a unit unit BU. Note that, in the unit BU, the die pad portions 3a and 4b are disposed in a substantially parallel state in a horizontal direction.

【0013】(5)次に本発明装置の製造方法につい
て、図4、図5、図6及び図7を参照して説明 する。先ず、ダイパッド部に予めはんだ等が印刷された
リードフレームAを図示しない治具等に置き、次いで該
ダイパッド部1a、2aにダイオードチップD2、D3
及びD1、D4を夫々極性を異にして組み込む。次いで
リードフレームBのダイパッド部3a、4aが該ダイパ
ッド部1a、2aと直交する如く該リードフレームBを
載置する。この状態でブリッジ回路が形成され、これを
加熱によるはんだ付けで接合し一体化する。図6はこの
状態を示す。(a)図は平面図、(b)図は側面図である。
因みにリードフレームA、Bは、半導体装置を複数個同
時に組み立てる為に、例えばX方向に25個でY方向に
5個の125個分を有する構造となっている。
(5) Next, a method for manufacturing the device of the present invention will be described with reference to FIGS. 4, 5, 6 and 7. First, a lead frame A on which solder or the like is printed in advance on a die pad portion is placed on a jig or the like (not shown). Then, the diode chips D2 and D3
And D1 and D4 with different polarities. Next, the lead frame B is placed so that the die pad portions 3a and 4a of the lead frame B are orthogonal to the die pad portions 1a and 2a. In this state, a bridge circuit is formed, which is joined and integrated by soldering by heating. FIG. 6 shows this state. (a) is a plan view and (b) is a side view.
Incidentally, the lead frames A and B have, for example, a structure having 25 pieces in the X direction and five pieces in the Y direction for 125 pieces in order to assemble a plurality of semiconductor devices at the same time.

【0014】次の工程では、半導体装置は信頼性及び機
械的強度の確保等の目的で、トランスファーモールド法
等により樹脂部16を形成するが、2枚のリードフレー
ムA、Bを重ね合わせたサイドレール切断前の状態で
は、サイドレールが二重(7、5)になっており、トラ
ンスファーモールド法で樹脂部を形成時固定しにくい、
サイドレール間に樹脂が入り込んでしまう恐れがあり、
その為、組み立て後にサイドレールの一方7を除去する
必要がある。プレス等を用いて金型で切断すると、半導
体チップに機械的ストレスを与えて接続部のはんだに亀
裂を生じるので、レーザを用いてサイドレールの一方7
を除去する。図7はこの状態を示し(a)図は平面図、
(b)図は側面図である。
In the next step, the semiconductor device is formed with a resin portion 16 by transfer molding or the like for the purpose of securing reliability and mechanical strength. Before the rail is cut, the side rails are double (7, 5), which makes it difficult to fix the resin part when forming it by the transfer molding method.
There is a risk that resin will enter between the side rails,
Therefore, it is necessary to remove one of the side rails 7 after assembly. When cutting with a die using a press or the like, a mechanical stress is applied to the semiconductor chip to cause cracks in the solder at the connection portion.
Is removed. FIG. 7 shows this state, and FIG.
(b) is a side view.

【0015】次に樹脂封止工程でトランスファーモール
ド法等により樹脂部16を夫々ユニット部に形成し、切
断装置等により露出する不要な枠体を除去し、個々のブ
リッジダイオードに分割する。
Next, in the resin sealing step, the resin portions 16 are formed in the respective unit portions by a transfer molding method or the like, and unnecessary frames exposed by a cutting device or the like are removed and divided into individual bridge diodes.

【0016】図8は、本発明に適用するリードフレーム
の他の実施例を示す平面図で、(a)図 (6) はリードフレームA、(b)図はリードフレームB、(c)
図は半導体チップを挟持した状態を示す。この実施例で
フレームAは前記実施例(図4)と同一形状であり(b)
図において、フレームBもAを同一形状にしたことであ
る。この構造では同一フレーム二枚(A、B)の組み合わ
せて構成される為、フレーム自体が作り易く、生産性が
向上する。尚、完成後のブリッジダイオードは平面形状
が略菱形になり、半導体チップからの発熱を均等に分散
できる。
FIGS. 8A and 8B are plan views showing another embodiment of the lead frame applied to the present invention. FIG. 8A shows a lead frame A, FIG. 8B shows a lead frame A, and FIG.
The figure shows a state where a semiconductor chip is sandwiched. In this embodiment, the frame A has the same shape as the previous embodiment (FIG. 4) (b).
In the figure, the frame B has the same shape as that of the frame A. In this structure, two identical frames (A, B) are combined, so that the frame itself is easy to make and productivity is improved. Note that the bridge diode after completion has a substantially rhombic planar shape, so that heat generated from the semiconductor chip can be evenly dispersed.

【0017】[0017]

【発明の効果】以上、本発明のブリッジ型半導体装置に
ついて説明したが、端子部が4端子以外の半導体装置で
も同様の効果が得られる。また、本発明のリードフレー
ム長さは、長尺なほど生産性が高まり、一定の長さに限
定するものではなく応用範囲が広い。又、半導体チップ
と、接続のはんだ及び略同一形状の2枚のリードフレー
ムのみで、複数個同時に組み立てでき、生産性の高いブ
リッジ型半導体装置を提供できる。樹脂部形成前の機械
的に弱い状態のリードフレームをレーザにより、ストレ
スを与えることなく、不要な部分を容易に除去できる。
As described above, the bridge type semiconductor device of the present invention has been described. However, the same effect can be obtained in a semiconductor device having a terminal portion other than four terminals. In addition, the longer the lead frame length of the present invention, the higher the productivity. The length of the lead frame is not limited to a fixed length, but has a wide range of application. Further, a bridge-type semiconductor device having high productivity can be provided because a plurality of semiconductor chips, solder for connection and two lead frames of substantially the same shape can be simultaneously assembled. Unnecessary portions can be easily removed without applying stress to the lead frame in a mechanically weak state before forming the resin portion by using a laser.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す平面図FIG. 1 is a plan view showing an embodiment of the present invention.

【図2】本発明の一実施例を示す側面図FIG. 2 is a side view showing one embodiment of the present invention.

【図3】電気的等価回路図[Figure 3] Electrical equivalent circuit diagram

【図4】本発明に適用するリードフレームAの構造図FIG. 4 is a structural diagram of a lead frame A applied to the present invention.

【図5】本発明に適用するリードフレームBの構造図FIG. 5 is a structural diagram of a lead frame B applied to the present invention.

【図6】本発明の製法を説明する工程図 (7)FIG. 6 is a process chart (7) for explaining the production method of the present invention.

【図7】本発明の製法を説明する工程図FIG. 7 is a process chart illustrating a production method of the present invention.

【図8】本発明に適用するリードフレームの他の実施例FIG. 8 shows another embodiment of the lead frame applied to the present invention.

【符号の説明】[Explanation of symbols]

1、2,3,4 リード端子 1a、2a、3a、4a ダイパッド部 5、5a、7、7a サイドレール 6、6a、8、8a パイロット穴 AU、BU 単位ユニット D1、D2、D3、D4 半導体(ダイオード)チップ 16 樹脂 1,2,3,4 Lead terminal 1a, 2a, 3a, 4a Die pad part 5,5a, 7,7a Side rail 6,6a, 8,8a Pilot hole AU, BU Unit unit D1, D2, D3, D4 Semiconductor ( Diode) chip 16 resin

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 互いに平行状態に配置されると共に、間
隔を設けて2つの半導体チップを搭載するスペースを持
つダイパッド部と、これと一体の端子部を備えた金属板
ユニットをXY方向に複数個連接した第1のリードフレ
ーム及び第2のリードフレームの夫々のダイパッド間に
半導体チップを挟持してはんだ付けするようにしたこと
を特徴とするブリッジ型半導体装置の製造方法。
1. A plurality of metal plate units provided in parallel to each other and having a space for mounting two semiconductor chips with a space therebetween, and a metal plate unit having a terminal unit integrated therewith in the XY direction. A method for manufacturing a bridge-type semiconductor device, wherein a semiconductor chip is sandwiched and soldered between respective die pads of a connected first lead frame and a second lead frame.
【請求項2】 はんだ付けした後、樹脂封止する工程を
含む請求項1のブリッジ型半導体装置の製造方法。
2. The method for manufacturing a bridge-type semiconductor device according to claim 1, further comprising a step of sealing with a resin after soldering.
【請求項3】 樹脂封止工程に先立って一方のリードフ
レームの一部を除去する工程を含む請求項1又は請求項
2のブリッジ型半導体装置の製造方法。
3. The method for manufacturing a bridge type semiconductor device according to claim 1, further comprising a step of removing a part of one of the lead frames prior to the resin sealing step.
【請求項4】 半導体チップのはんだ付け後、第1及び
第2リードフレームをブリッジ単位ユニットに分割する
工程を含む請求項1,請求項2,又は請求項3のブリッ
ジ型半導体装置の製造方法。
4. The method according to claim 1, further comprising the step of dividing the first and second lead frames into bridge unit units after soldering the semiconductor chip.
【請求項5】 一方の平行配置されたダイパッド部に導
電極性を異にして搭載された第1、2第2の半導体チッ
プ及び第3、第4の半導体チップと、該半導体チップ上
に該ダイパッド部と略直角方向に平行配置された他方の
ダイパッド部と、該一方のダイパッド部から伸張する第
1、第2のリード端子と、他方のダイパッド部から該リ
ード端子と反対方向に伸張する第3、第4のリード端子
と、該ダイパッド部及び半導体チップと、該リード端子
の一部を封止する樹脂部を備えたブリッジ型半導体装
置。
5. A first semiconductor chip, a second semiconductor chip, and a third semiconductor chip mounted on one of the die pads arranged in parallel with different conductive polarities, and the die pad on the semiconductor chip. The other die pad portion, which is arranged in a direction substantially perpendicular to the portion, first and second lead terminals extending from the one die pad portion, and a third lead terminal extending from the other die pad portion in a direction opposite to the lead terminal. A bridge type semiconductor device comprising: a fourth lead terminal; a die pad portion; a semiconductor chip; and a resin portion for sealing a part of the lead terminal.
JP13449998A 1998-04-28 1998-04-28 Bridge type semiconductor device and its manufacture Pending JPH11312781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13449998A JPH11312781A (en) 1998-04-28 1998-04-28 Bridge type semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13449998A JPH11312781A (en) 1998-04-28 1998-04-28 Bridge type semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH11312781A true JPH11312781A (en) 1999-11-09

Family

ID=15129760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13449998A Pending JPH11312781A (en) 1998-04-28 1998-04-28 Bridge type semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH11312781A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6762067B1 (en) * 2000-01-18 2004-07-13 Fairchild Semiconductor Corporation Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails
US8922015B2 (en) 2012-04-05 2014-12-30 Renesas Electronics Corporation Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6762067B1 (en) * 2000-01-18 2004-07-13 Fairchild Semiconductor Corporation Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails
US8922015B2 (en) 2012-04-05 2014-12-30 Renesas Electronics Corporation Semiconductor device
US9230948B2 (en) 2012-04-05 2016-01-05 Renesas Electronics Corporation Method of manufacturing a semiconductor device

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