JPH02153753A - Thermal head - Google Patents

Abstract

PURPOSE:To obtain a thermal head realizing clear thermal recording by forming each of many heat generating constitutional parts which are provided together with a driving thin film transistor on one substrate in a layered structure of a heat generating resistance layer and a rectifying semiconductor layer. CONSTITUTION:A single crystal N-type silicon substrate 10 is provided with many heat generating constitutional parts 5, N-MOS, C-MOS and a plurality of bump electrodes 11 in every block. One block forms one thermal head. Each heat generating constitutional part 5 is obtained by laminating a heat generating resistance element 6 and a rectifying diode 7. An insulating film 12 of SiO2 is formed on an upper surface of the substrate 1 through oxidizing treatment, and an insulating protective film 13 having high insulating property is further formed on the film 12 through CVD process. An anode electrode 14 made of such metal as Al, Al-Si, Cu or the like is patterned on the upper face of the film 13. Accordingly, the area occupied by one heat generating constitutional part 5 corresponding to one dot can be remarkably reduced and the resolving power of the thermal head can be enhanced, whereby considerably clear thermal printing can be achieved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a thermal head for performing thermosensitive recording.

[Prior Art] A conventional thermal head that performs thermal recording by selectively generating heat from a heating element has only a heating element section on a substrate, and is separate from a drive circuit section. Therefore, when the printed dots have a fine pitch, it becomes difficult to connect the heating element section and the drive circuit section.

To solve this problem, the wires of the thermal head are spread out in a fan shape from the heat generating element side, but this still has the problem of poor productivity and an increase in the size of the device.

For this reason, recently, it has been considered to provide the heating element section and the drive circuit section on one substrate. In this structure, an insulating film is formed on a substrate, and a heating element section and a drive circuit section are formed on this insulating film. The rectifying diode is provided in a corresponding manner, and the rectifying diode allows current to flow only through the heat generating resistor element specified in the drive circuit section to generate heat.

[Problem to be solved by the invention]However, in such a thermal head, 1
Since the heat generating part consists of a plurality of heat generating resistor elements and rectifying diodes, and these are arranged in a plane, the area of one heat generating element, that is, one dot, consisting of a heat generating resistor element and a rectifying diode is large. There is a problem that the resolution decreases.

The purpose of this invention is to reduce the area occupied by one heating element corresponding to one dot, thereby increasing the resolution and
To provide a thermal head capable of clear thermal recording.

[Means for Solving the Problems] The thermal head of the present invention has a plurality of heat generating components provided on two substrates together with driving thin film transistors each having a laminated structure of a heat generating resistor layer and a rectifying semiconductor layer. It is.

[Function] According to the thermal head of the present invention, each heat generating component provided on two substrates together with a drive thin film transistor has a laminated structure of a heat generating resistor layer and a rectifying semiconductor layer.
The area occupied by one heat generating component corresponding to a dot can be reduced. Therefore, the resolution of the thermal head can be greatly increased, and clear thermal recording can be performed.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 2 shows the circuit configuration of the thermal head of this invention.
In this circuit configuration, the image signal is input as a data signal to the D terminal of the shift register circuit l. A clock signal is input to each 01 terminal of the shift register circuit 1. Data for one line is input to the shift register circuit l in accordance with a clock signal. All data for one line inputted to the shift register circuit 1 is transferred from the Q terminal of the shift register circuit 1 to the D terminal of the latch circuit 2 by a strobe signal inputted as a latch pulse to each terminal of the latch circuit 2. are transferred in parallel and held in the latch circuit 2. The data held in the latch circuit 2 is inputted from the Q terminal of the latch circuit 2 to the transistor element 4 via a gate circuit 3 such as an AND circuit in accordance with instructions of an enable signal that determines printing timing and the like. The transistor element 4 is driven based on input data, and selectively outputs a low level signal to each row line of the heat generating components 5 arranged in a matrix. Each heat generating component 5 is formed by connecting a heat generating resistor element 6 and a rectifying diode 7 in series, and selectively receives a high level signal from a column line selection circuit 8 based on a control signal for each column in a matrix. When the low level signal from the transistor element 4 is applied, a current flows through the heat generating resistor element 6 only at the location where it intersects with the low level signal from the transistor element 4, thereby generating heat.

At this time, the heat generating resistor element 6 to which the high level signal is supplied is rectified by each rectifying diode 7, so it does not generate heat.The 0th column line selection circuit 8 sequentially supplies a high level signal to each column line. Accordingly, the image signal held in the latch circuit 2 is updated, so that the heat generating resistor elements 6 to which the low level signal is supplied for each column generate heat at the same timing.

The transistor element 4 of such a thermal head is, for example, an n-MOS, and is connected to other circuits such as a shift register circuit 1, a latch circuit 2. The gate circuit 3 and the column line selection circuit 8 are C-MOS, etc., and are collectively formed on a silicon substrate 10, which will be described later, together with the source 8 component 5.

FIG. 1 shows the configuration of the thermal head of the present invention, rl
! JO is a single-crystal n-type silicon substrate (wafer).On this silicon substrate LO, each flock has a large number of heat generating components 5, n-MOS, C-MOS, etc.
(only a portion is shown) and a plurality of bump electrodes 11 are formed and each block is cut so that one block forms a thermal head.Hereinafter, the structure of each element will be explained in order.

Each heat generating component 5 includes a heat generating resistor element 6 and a rectifying diode 7.
are stacked, and are arranged in a matrix on the left end side of the silicon substrate 10. That is, the upper surface of the silicon substrate 10 is insulated with Si02! 112 is formed by oxidation treatment, and on this insulating layer 12, a highly insulating protective film 13 made of phosphosilicate glass (PSG) is formed by CV D (Ches+1cal).
It is formed by the Vapor Deposition method. A1.
An anode electrode 14 made of metal such as Al-5i or Cu is patterned. This seven-node electrode 14 is one electrode of the rectifying diode 7, and is connected to the above-mentioned column line selection circuit 8 for each column. Further, on the upper surface of the seven-node electrode 14, a heating resistance layer 15 made of polycrystalline silicon doped with impurities is formed in a matrix. This heating resistance layer 15 has a predetermined sheet resistance (a10/hole) by doping a predetermined amount of phosphorus (P) ions as an impurity. That is, since the total resistance value of this heating resistance layer 15 is determined by the implantation concentration of P ions and its area, the amount of implantation of P ions (for example,

(about IX 1015 to IX 1021 at+s/cm3) and the amount of non-etching, and is finally adjusted to about several tens to hundreds of ohms. On the upper surface of the heat generating resistor layer 15, an n-type semiconductor layer 16 made of polycrystalline silicon doped with impurities is formed in a matrix in the same shape as the heat generating resistor layer 15. This n-type semiconductor layer 16 corresponds to the rectifying diode 7,
P ions are doped at a lower concentration than that of the heating resistance layer 15. Further, on the upper surface of this n-type semiconductor layer 16, an AI
A cathode electrode 17 made of metal such as , ^IJi is deposited,
A pattern is formed by sputtering or the like, and this cathode electrode 17 and the above-mentioned n-type semiconductor layer 16 constitute a Schottky barrier diode, which is the rectifying diode 7. That is, when the cathode electrode 17 is formed on the upper surface of the n-type semiconductor layer 16, a barrier is formed in the n-type semiconductor layer 16 due to an interface phenomenon between the two, thereby forming a rectifying diode. Note that one end of the cathode electrode 17 is connected to a wiring pattern 24 of the drain of the transistor element 4, which will be described later. Then, each of the anode electrodes 14 and the heating resistor layer 1 laminated in this way
5. The n-type semiconductor layer 16 and the cathode electrode 17 are maintained!
It is covered with an I film 18. This protective Wi18 has oxidation resistance and wear resistance, and is S +02, Si
It consists of N, 5iON, etc. Note that an insulating layer is also formed between each heating component 5, and although this insulating layer is actually formed as a layer overlapping with the protective film 18, it is illustrated as a single-layer protective film 18 in the drawing. There is.

The transistor element 4 is a field effect (FET) type n-MO
5, and is formed on the right side of the heat generating component 5 in the silicon substrate IO. Namely.

A p-type region 19 doped with B ions is formed inside that portion of the upper surface of the silicon substrate 10, and this p-type region 19 is doped with B ions.
A pair of n-type regions 20.20 doped with P ions are formed within the type region 19. This pair of n-type regions 20 and 20 form source and drain electrodes, respectively.

A pair of n-type regions 2 are formed on the upper surface of the silicon substrate IO in which the n-type regions 20 and 20 are formed in the p-type region 19 in this way.
An insulation M12 is formed except for the central portion including 0.20. Further, a gate electrode 22 made of polycrystalline silicon is formed at a location between the pair of n1fi regions 20 and 20 with a gate insulating film 21 made of 5iOz interposed therebetween. Further, source and drain wiring patterns 23 and 24 are located at locations corresponding to the pair of n-type regions 20 and 20.
is formed. In this case, the intermediate gate electrode 22 is formed to have a low resistance by doping with P ions in the same manner as the heating resistance layer 15, and the entire surface of the gate electrode 22 is formed so as not to be short-circuited with the wiring patterns 23 and 24. It is covered with 1 g and 11 g of protection made of phosphosilicate glass. In addition, source and drain wiring patterns 23.2
4 is made of a low resistance metal such as AI, Al-5i, No, W, etc., and is electrically connected to a pair of n-type regions 20 and 20, respectively, and a cathode electrode 17 is connected to the drain wiring pattern 24. has been done.

The C-MOS that constitutes the shift register circuit 1, latch circuit 2, and gate circuit 3 may also be of FET type.
The transistor element 4 is formed on the right side of the transistor element 4 described above, and is made of an n-MOS, a p-MOS, or the like. in this case,
The n-MO3 has exactly the same configuration as the transistor element 4 described above, and the p-MOS has the same structure as the n-MO5 described above except that a pair of p-type regions (not shown) are formed inside the upper surface side of the silicon substrate IO. It has exactly the same configuration.

The bump electrode 11 is an electrode for depositing various signals into the C-MOS, and a plurality of bump electrodes (in this embodiment, for image signals, clock signals, strobe signals,
6) for the enable signal and two for the control signals. That is, the insulation g on the silicon substrate 10
12 and the upper surfaces of the wiring pattern 25, a protective ata is formed by etching at predetermined locations. Ti-W is used as a barrier metal in this knee-chipped area.
A pad portion 26 is formed by laminating an alloy and Au as an adhesion metal by vapor deposition, sputtering, etc. and is electrically connected to the wiring pattern 25 . This pad part 2
A bump electrode 11 is formed on 6 by Au plating. In this case, the barrier metal of the pad portion 26 may be Ti, Cu, Ti-N, WJ-in addition to Ti-W alloy.
The bump electrode 11 may have a single layer structure or a laminated structure such as 5i, and the adhesion metal may have a single layer structure or a layer structure such as Cr, Pb, Sn, etc.
A solder alloy may also be used.

Next, a case of manufacturing a thermal head as described above will be described. In this case, each thermal head is obtained by dividing one silicon substrate IO into a large number of blocks, forming the required elements for each block at the same time, and finally cutting each block. In the following explanation, only one block of the silicon substrate 10 will be explained.

First, a single-crystal n-type silicon substrate (wafer) 10 is prepared, and this silicon substrate IO is heated to about 1000°C to perform oxidation treatment (thermal oxidation treatment) to form a Si02 film on the surface of the silicon substrate IO. do. Then, a photoresist film is patterned on the 5i02 film by photolithography method, and S
The i02 film is etched to form transistor elements 4 and C.
- Remove SiOzJgl from a portion corresponding to the MOS formation region. Then, the insulation [12] shown in FIG. 1 is formed.

After this, the part without insulation [912, that is, S 1o211
G! A gate insulating film 21 is formed on the removed portion by dry oxidation or 1101 oxidation, and a polycrystalline silicon layer is formed on this gate insulating film 21 by CVD using monosilane (SiHs) gas. Then, P ions are implanted into this polycrystalline silicon layer to
After increasing the ion concentration and reducing the resistance value to a predetermined value,
This polycrystalline silicon layer is etched to form each gate electrode 22 of the transistor element 4 and C-MO3.

After that, each p of transistor element 4 and C-MO5
P ions are implanted into wall region 19 through gate insulating film 21 to form a pair of n-type regions 20.20. This pair of n-type regions 20 and 20 become a source and a drain, respectively.

Then, the gate insulating film 21 on each n-type region 20, 20 is removed by etching, an insulating protective film made of PSG is deposited on the entire surface by atmospheric pressure CVD, and this insulating protective film is etched to remove unnecessary parts. remove parts. Then, each gate electrode 22 of the transistor element 4, the C-MO 5, and the insulation M13 are covered with the insulation insulation film 18 made of PSG. Although not shown, a p-MOS is also formed in parallel with the above-described process.

&d, So17) Full surface D A1. Conductive gold such as Al-5i, No, W, etc. is formed by sputtering or vapor deposition, and the metal film is etched using a photoresist film patterned on the surface by photolithography as a mask to remove unnecessary parts. remove. As a result, seven node electrodes 14 connected to each heat generating component 5 are formed, and the transistor elements 4. C-MO3
, the wiring patterns 23, 24, 25 of the bump electrodes 11 are also formed at the same time. In this case, each of the seven node electrodes 14 is led out to the column line selection circuit 8 for each column. In addition, each wiring pattern 23 of the transistor element 4 and C-MO5
．． 24 are electrically connected to each n-type copper area 20 or p-type copper area (not shown), respectively.

After this, similarly to the case of forming the gate electrode 22, a polycrystalline silicon layer is generated on the 7-node electrode 14 by the CVD method using monosilane (SiH4) gas, and P ions are implanted into this polycrystalline silicon layer. , the P ion concentration is increased to reduce the resistance value to a predetermined value, and then the polycrystalline silicon layer is plasma etched to remove unnecessary portions and formed into an island shape of a predetermined area. As a result, the heating resistance layer 15, which is the heating resistance element 6, is formed. In this case, the sheet resistance of the polycrystalline silicon layer before P ion implantation is several Ω/hole to several MΩ/hole, and this ultimately becomes several tens of Ω/hole after P ion implantation.

After removing the heat generating resistor layer 15 and forming the protective film 18 at almost the same height as the heat generating resistor layer 15, a polycrystalline silicon layer is again generated on the entire surface in the same manner as described above. After implanting P ions into the polycrystalline silicon layer, unnecessary portions are removed by etching the polycrystalline silicon layer to form an n-type semiconductor layer 16 having the same shape as the heating resistor layer 15. In this case, the impurity concentration of the n-type semiconductor layer 16 is
5, and this n-type semiconductor layer 16 is removed and a 11 film 18 is formed at approximately the same height as the n-type semiconductor layer 16.

Thereafter, a contact hole is formed by etching and removing the protective layer 111918 in a portion corresponding to the wiring pattern 24 of the drain of the transistor element 4, and the protective IN! An aluminum-based metal film such as AI or Al-5i is formed on the entire surface of 118 by sputtering or vapor deposition, and unnecessary portions are removed by etching the metal film.

As a result, a cathode electrode ai17 is formed. This cathode electrode 17 is electrically connected to the n-type semiconductor layer 16 in each row in a matrix, and one end thereof is connected to the wiring pattern 24 for the drain of the transistor element 4 via a contact hole. Furthermore, when the cathode electrode 17 is formed in this manner, a barrier is formed within the n-type semiconductor layer 16 due to an interface phenomenon with the n-type semiconductor layer 16, and this causes the Shutkey barrier diode as the rectifying diode 7 to generate heat. An end layer is formed on the resistance layer 15.

Thereafter, a retaining layer 18 is again formed on the entire surface by sputtering, vapor deposition, etc., and this retaining film 18 is etched to remove unnecessary portions corresponding to the bump electrodes 11. After this, Konoho! A Ti-W alloy as a barrier metal and Au as an adhesion metal are sequentially deposited on the entire surface of the t17918 by vapor deposition or sputtering to form a metal layer, and a resist is applied on the surface of this metal layer by spin coating, Etch and remove the bump forming area. After this etched portion is plated with Au to form the bump electrode 11, the diced portion of the silicon substrate 10 is etched and etched away, and the metal layers other than the resist and pad portion 26 described above are sequentially etched. and remove it. Finally, each block of the silicon substrate 10 is diced and separated into individual blocks to obtain the thermal head of the present invention as shown in FIG.

Therefore, according to such a thermal head, a large number of heat generating components 5, transistor elements 4 . Since the and C-MOS are integrally formed, the number of bump electrodes 11 for connecting an external circuit board or the like can be reduced to a minimum (several pieces). Therefore, there is no need to spread out the wiring section in a fan shape as in the conventional case, so the entire device can be configured compactly. In particular, each heat generating component 5
is an insulating film 12 and an insulating protection 1! on a silicon substrate lO.
! 18, the anode electrode 14, the heating resistance layer 15, n
Since the semiconductor layer 16 and the cathode electrode 17 are formed by sequentially stacking them, the area occupied by one heat generating component 5 corresponding to one dot can be made extremely small. Therefore,
The resolution of the thermal head can be increased and extremely clear thermal recording can be performed. In this case, the rectifying diode 7 is formed by the n-type semiconductor layer 16 and the cathode electrode 17.
Since the Schottky barrier diode is constructed, there is an advantage that a p-type region is not required compared to a pn junction diode, and the manufacturing process can be simplified.

Note that this invention is not limited to the embodiments described above, and can be modified and applied in various ways. @ For example, heating resistance layer 15
．． The n-type semiconductor layer 16, the p-type region 19, the n-type region 20, etc. do not need to be formed by ion implantation, and may be formed by a thermal diffusion method. For example, the cathode electrode 17, the n-type semiconductor layer 16, the heat generating resistor layer 15, and the anode electrode 14 may be laminated in this order. In this case, the uppermost anode electrode 14 is If a metal harder than At, such as copper, is used, wear resistance can also be improved.

Furthermore, the silicon substrate 1O does not necessarily have to be a single crystal, and an insulating substrate such as glass or quartz may be used. In this case, the active region of each transistor element 4 is formed by forming a polycrystalline silicon layer on the surface of the insulating substrate. 5. This polycrystalline silicon layer is doped with a predetermined impurity. Further, the heat generating components 5 do not need to be arranged in a matrix, and may be arranged in a line.

[Effects of the Invention] As described in detail above, according to the thermal head of the present invention, each heat generating component provided on two substrates together with a driving thin film transistor has an aM structure of a heat generating resistor layer and a rectifying semiconductor layer. Therefore, it is possible to reduce the area occupied by one heat generating component corresponding to one dot. Therefore, the resolution of the thermal head can be greatly increased, and clear thermal recording can be performed.

[Brief explanation of the drawing]

FIG. 1 is an enlarged sectional view of the main parts of the thermal head of the present invention.
FIG. 2 is a circuit diagram of the thermal head. 4...Transistor element, 5...Heating component. 6... Heat generating resistor element, 7... Rectifying diode, lO... silicon substrate, 14...
... 7 node electrodes, 15 ... heating resistance layer, 1
6...n-type semiconductor layer, 17... cathode electrode.

Claims (1)

[Scope of Claims] A thermal head in which a large number of heat generating components and driving thin film transistors are provided on a single substrate, wherein the heat generating component has a laminated structure of a heat generating resistor layer and a rectifying semiconductor layer. Features a thermal head.