JP2504144B2 - Thermal head and manufacturing method thereof - Google Patents

Description

The present invention relates to a thermal head for heat-sensitive recording and a method for manufacturing the same.

[Prior Art] A conventional thermal head that performs heat-sensitive recording by selective heat generation of a heating element has only the heating element and is separate from the drive circuit section. Therefore, when the print dots have a fine pitch, it becomes difficult to connect the heating element to the drive circuit section. To cope with this problem, the wiring of the thermal head is extended in a fan shape from the side of the heating element. However, the productivity is still poor, and there is a problem that the apparatus becomes large.

For this reason, recently, it has been considered to provide the heating element and the drive circuit section on one substrate. In this structure, an insulating layer is formed on a substrate, and a heating element and a thin film transistor are formed on this insulating layer. The thin film transistor having this structure is a MOS transistor that serves as a driver element, and has a configuration in which polycrystalline silicon is formed on an insulating layer and the polycrystalline silicon is doped with impurities.

[Problems to be Solved by the Invention] However, since the thin film transistor in which impurities are doped into polycrystalline silicon has a low electric mobility, the width of the gate needs to be increased in order to increase the electric mobility even a little. And the constraint that the length must be as large as possible. Therefore, it is not suitable for high-density printing. In addition, in order to improve the electric mobility of polycrystalline silicon, an experiment in which polycrystalline silicon is once made amorphous and then returned to polycrystalline silicon is reported, but this method requires a large number of steps. Many are extremely poor in productivity. Moreover, even with this technology, the mobility of electricity is still not sufficient, and each gate must be made quite large. For this reason, the resolution is limited to about 8 dots / mm at the most, and it has not yet reached a practical level for high quality printing.

An object of the present invention is to provide a thermal head having good electric mobility, capable of fine pitch formation, suitable for high-density printing, and excellent in productivity, and a manufacturing method thereof.

[Means for Solving the Problems] A thermal head according to the present invention has a large number of thin film resistance elements made of polycrystalline silicon arranged in an array on a single crystal semiconductor substrate, and the single crystal semiconductor substrate is made of polycrystalline silicon. A drive circuit section including a shift register, which is composed of a transistor having a gate electrode, is formed, and each thin film resistance element is a heat generating section driven by the drive circuit section. The method for manufacturing a thermal head of the present invention comprises a step of forming an insulating layer and a gate insulating layer on a single crystal semiconductor substrate, and a large number of polycrystalline silicon layers on the insulating layer and the gate insulating layer, respectively. A step of forming a thin film resistance element and a gate electrode, and diffusing impurities into at least each of the thin film resistance elements to reduce the resistance value of the thin film resistance elements. And a step of forming a diffusion region by diffusing impurities in the semiconductor substrate and forming a wiring pattern made of a low-resistance metal, forming a drive circuit section including a shift register composed of a large number of transistors, and the drive circuit. And a step of connecting the portion to each of the thin film resistance elements, and a step of depositing an insulating protective film on the entire surface.

In such a thermal head and its manufacturing method,
Since the active layer of the transistor that constitutes the drive circuit section including the shift register is single crystal silicon, high-speed and high-resolution printing is possible, and this drive circuit section is on the same substrate as the thin film resistance element for heat generation. Since it is formed, the connection between the two is extremely simple, and since the thin film resistance element and the gate electrode of each transistor are both polycrystalline silicon, they can be formed in the same process, which makes the manufacturing efficient.
Further, since the thin film resistance element is formed on the single crystal semiconductor substrate, the heat generation of the thin film resistance element is sufficiently accumulated, and high printing quality can be maintained.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows the structure of the thermal head of the present invention. In the figure, reference numeral 1 denotes a single-crystal n-type silicon substrate (wafer). On this silicon substrate 1, a thin film heating element 2, a thin film transistor 3, a drive circuit section composed of a C-MOS transistor, and a bump section 4 are collectively formed. The thin film transistor 3 is an n-MOS.FET, and the drive circuit unit configured by a C-MOS transistor constitutes a shift register circuit, a latch circuit, a gate circuit and the like. Hereinafter, the configuration of each element will be described in order.

The thin-film heating element 2 is a portion that generates heat, and is formed near the left end of the silicon substrate 1. That is, the heat generation portion 5 is formed on the upper surface of the silicon substrate 1 in a raised manner. This raised heat generating portion 5 is covered with an insulating film 6 of SiO ₂ , and a heating resistance layer 7 formed by doping polycrystalline silicon with impurities is formed on the surface of the insulating film 6. As shown in FIGS. 2A and 2B, the heat generation portion 5 extends over the entire length of the silicon substrate 1 in the width direction (vertical direction in FIG. 1).
It is formed by protruding in a convex shape. In addition, the heat generating resistance layer 7 is 16 dots / m along the longitudinal direction of the heat generating portion 5 described above.
They are arranged at equal intervals with a pitch of m. Further, the heating resistance layer 7 is doped with a predetermined amount of phosphorus (P) ions as impurities, so that a predetermined sheet resistance (several tens of Ω) is obtained.
/ □). That is, since the total resistance value of the heating resistance layer 7 is determined by the implantation concentration of P ions and its area, it is adjusted by the implantation amount of P ions and the amount of non-etching, and finally several tens to several hundreds Ω. It is adjusted to the extent. Further, on the insulating film 6 around the heat generating resistance layer 7, a highly insulating insulating protective film 8 made of linker glass (PSG) is formed by a CVD (Chemical Vapor Deposition) method, and on the insulating protective film 8. The wiring patterns 9 and 15 are formed so as to be electrically connected to both end portions of the heating resistance layer 7. The wiring patterns 9 and 15 are made of a low resistance metal such as Al, Al-Si, Mo and W, the left wiring pattern 9 forms an earth line, and the right wiring pattern 15 forms an electrode wiring described later. A protective film 10 is formed on the surfaces of the heating resistance layer 7 and the wiring patterns 9 and 15. This protective film 10 has oxidation resistance and wear resistance,
It may have a two-layer structure of SiO ₂ and SiN or a single layer of SiON. The protective film 10 is formed such that the portion corresponding to the heat generation portion 5 projects higher than the protective film 10 in the entire surrounding area. This structure has each heating resistance layer 7
It is extremely effective to bring the surface of the protective film 10 in the area corresponding to the above into contact with thermal paper or thermal ink sheet.

The n-MOS forming the thin film transistor 4 has a field effect (F
(ET) type, and is formed in a portion of the silicon substrate 1 far away from the thin film heating element 2 to the right.
That is, a p-type region 11 doped with boron (B) ions is formed inside the upper surface of the silicon substrate 1 at that portion, and P ions are doped in the region of the p-type region 11 2 Two n-type regions 12, 12 are formed. The two n-type regions 12 and 12 serve as source and drain electrodes, respectively. The upper surface of the silicon substrate 1 in which the n-type regions 12 and 12 are thus formed in the p-type region 11 is the same as the thin-film heating element 2 except for the central portion including the two n-type regions 12 and 12. The film 6 is formed and two n-type regions are formed.
The portion located between the 12 and 12, a gate electrode 14 made of the same polycrystalline silicon and heating resistor layer 7 of thin-film heat generating element 2 via the gate insulating film 13 made of SiO ₂ is formed, 2 Source and drain wiring patterns 15, 15 are formed at locations corresponding to the two n-type regions 12, 12. In this case, the intermediate gate electrode 14 is formed to have a low resistance by doping P ions similarly to the thin film heating element 2, and the entire surface thereof is formed so as not to be short-circuited with the wiring patterns 15 and 15. It is covered with the same insulating protective film 8. In addition, source and drain wiring patterns 15 and 15
Is made of a low resistance metal such as Al, Al-Si, Mo and W, and is connected to two n-type regions 12 and 12, respectively, and one wiring pattern 15 is the right end of the heating resistance layer 7 of the thin film heating element 2. Is electrically connected to the section. And this wiring pattern 1
The same protective film 10 as the thin film heating element 2 is formed so as to cover the insulating protective film 8 on the gate electrodes 15 and 15. The protective film 10 is formed lower than the protective film 10 of the thin film heating element 2.

The drive circuit section composed of C-MOS transistors is of FET type that constitutes a shift register circuit, a latch circuit, a gate circuit, etc., and is composed of an n-MOS and a p-MOS, and is on the right side of the above-mentioned thin film transistor 3. Approaching n-
It is formed in the order of MOS and p-MOS. In this case, n-MO
S has the same structure as the thin film transistor 3 described above. That is, B is present inside the upper surface of the silicon substrate 1.
A p-type region 16 doped with ions is formed, and two n-type regions 17, 17 doped with P ions are formed in the p-type region 16. On the upper surface of the silicon substrate 1 in this portion, except for the central portion including the two n-type regions 17 and 17, the same insulating film 6 of SiO ₂ as the thin film transistor 3 described above is formed. A gate electrode 14 made of polycrystalline silicon, which is the same as that of the thin film transistor 3, is formed at a position between the _two 17 and 17 via a gate insulating film 18 made of SiO ₂ and two n-type regions 1 are formed.
Source and drain wiring patterns 19 and 19 are formed at locations corresponding to 7 and 17. In this case as well, the gate electrode 14 is formed with a low resistance by doping P ions similarly to the thin film heating element 2, and the thin film heating element 2 is formed so that the entire surface thereof is not short-circuited with the wiring patterns 19 and 19. It is covered with the same insulating protective film 8. Then, the same protective film 10 as the thin film heating element 2 is formed so as to cover the wiring patterns 19 and 19 and the insulating protective film 8 on the gate electrode 14.

The p-MOS has the same structure as the n-MOS described above except that two p-type regions 20, 20 are formed inside the upper surface of the silicon substrate 1. That is, two p-type regions
2 is on the upper surface of the silicon substrate 1 where 20 and 20 are formed.
One, except for the central portion including a p-type region 20 and 20, and the insulating film 6 of SiO ₂ is formed, at a position located between the two p-type regions 20 and 20, a gate insulating made of SiO ₂ The gate electrode 14 made of polycrystalline silicon is formed through the film 18,
Source and drain wiring patterns 19, 19 are formed at locations corresponding to the two p-type regions 20, 20. Also in this case, the entire surface of the gate electrode 14 is covered with the insulating protective film 8 so as not to short-circuit with the wiring patterns 19, 19. And
A protective film 10 is formed so as to cover the wiring patterns 19, 19 and the insulating protective film 8 on the gate electrode 14.

The bump portion 4 is an electrode that takes in various signals to the drive circuit portion formed of C-MOS transistors, and a plurality of bump portions (for example, image signals, clock signals,
4) such as a strobe signal and an enable signal. That is, a protective film 10 having a predetermined portion etched is formed on the upper surface of the wiring pattern 21 formed on the silicon substrate 1 with the insulating film 6 of SiO ₂ and the insulating protective film 8 interposed therebetween. Ti-W alloy and Au
A metal layer 22 such as is formed by vapor deposition or sputtering and is connected to the wiring pattern 21, and an Au plating layer 23 is provided on the metal layer 22.

Next, with reference to FIGS. 3A to 3J, a case of manufacturing the thermal head as described above will be described.

First, as shown in FIG. 3 (A), a silicon substrate (wafer) 1 is prepared, one surface of the silicon substrate 1 is etched, and the portion indicated by the dotted line is removed to elevate the formation region of the thin film heating element 2. Then, the convex heat generation portion 5 is formed.
In this case, the thickness to be etched is several μm to several tens μm. Further, the etching is performed by plasma etching using gas or using a chemical solution containing hydrofluoric acid as a main component.

After that, the silicon substrate 1 is heated to about 1000 ° C. to be oxidized (thermal oxidation treatment), and the surface of the silicon substrate 1 is
The SiO ₂ film 24 is formed. Then, a photoresist film is patterned on the SiO ₂ film 24 by photolithography. That is, a photoresist film is formed by coating on the SiO ₂ film 24, and the photoresist film is exposed through a mask,
The exposed photoresist film is developed to remove unnecessary portions. As a result, the photoresist film is patterned. The SiO ₂ film 24 is etched using the photoresist film thus patterned as a mask to remove unnecessary portions, that is, the p-type regions 11 and 16 of the thin film transistor 3 and the C-MOS, as shown in FIG. 3B. The SiO ₂ film 24 in the portion corresponding to is removed. Then, B ions are implanted and doped into the portion of the silicon substrate 1 where the SiO ₂ film 24 has been removed to form the p-type regions 11 and 16 in the silicon substrate 1.

After that, the SiO ₂ film 24 is once removed, and the silicon substrate 1 is again thermally oxidized to form the SiO ₂ film on the entire surface thereof. Then, a photoresist film is patterned on the surface of the SiO ₂ film by the photolithography method, and the SiO ₂ is etched using the photoresist film as a mask, as shown in FIG.
As shown in FIG. 5, the SiO ₂ film in the portions corresponding to the p-type regions 11 and 16 of the thin film transistor 3 and the C-MOS and the formation region of the p-MOS is removed. As a result, the insulating film 6 made of SiO ₂ is formed at a predetermined position on the silicon substrate 1 including the heat generation portion 5.
Are formed. Then, the gate insulating films 13 and 18 are formed on the portion where the SiO ₂ film is removed by dry method or oxidation of HCl.

Then, a polycrystalline silicon layer 25 is formed on the entire surface by a CVD method using monosilane (SiH ₄ ) gas, and then a third silicon layer is formed.
As shown in FIG. 6C, P ions are implanted into the entire polycrystalline silicon layer 25 to increase the P ion concentration of the polycrystalline silicon layer 25 in the portion corresponding to the heat generation portion 5 and set the resistance value to a predetermined value. Reduce. In this case, the P ion concentration should be increased in consideration of the implantation amount of P ions when the n-type regions 12 and 17 are formed in the subsequent step (step of FIG. 3E). deep. That is, the sheet resistance of the polycrystalline silicon layer 25 before the implantation of P ions is several KΩ / □ to several MΩ.
/ □, which is finally set to several tens of Ω / □. In addition,
In this case, the polycrystalline silicon layer 25 corresponding to the thin film transistor 3 and each of the gate electrodes 14 such as C-MOS, and the polycrystalline silicon layer 25 corresponding to the heating resistance layer 7 of the thin film heating element 2 are formed.
When the implantation amount of P ions is the same, a single process is required. However, if the implantation amount of P ions into the polycrystalline silicon layer 25 of the thin film heating element 2 is large, a resist mask is used. Then, P ions may be implanted again only into the polycrystalline silicon layer 25 of the thin film heating element 2, or a resist mask may be formed on each of them to perform another step.

Then, a photoresist film is patterned on the surface of the polycrystalline silicon layer 25 by a photolithography method, and the polycrystalline silicon layer 25 is used as a mask.
To remove unnecessary portions. As a result, as shown in FIG. 3D, the thin film heating element 2, the thin film transistor 3, and the heating resistance layer 7 made of polycrystalline silicon doped with P ions in the respective regions where the C-MOS is formed, and the respective gates. The electrodes 14 ... Are formed.

By the way, an important matter regarding each heating resistance layer 7 is to heat only a required heating portion in order to improve the resolution. Therefore, in this embodiment, as shown in FIGS. 2A and 2B, the inside of the area A corresponding to the upper surface of the heat generation portion 5 has a higher resistance than the outside of the area. There is. As this method, in FIG. 2 (A), the P ion concentration in the A region of each heating resistance layer 7 is made smaller than the region outside the region, or the B region is doped in the region outside the A region. Show. Also, FIG. 2 (B)
Forms a slit S in each heating resistance layer 7 in the area A,
A method of narrowing the width of the conductive path with respect to the area outside the area will be described.
Of course, a method combining both methods can also be adopted. In any case, the total resistance value of each heating resistance layer 7 is, for example, several tens of Ω
Adjust to several hundred Ω.

Next, as shown in FIG. 3 (E), the gate insulating layer 18 of the p-MOS is masked with the photoresist film 26, and the gate insulating layer is formed in the p-type regions 11 and 16 of the thin film transistor 3 and the C-MOS. Two sets of n-type regions for implanting P ions via 13
12 and 17 are formed. The two sets of n-type regions 12 and 17 serve as a source and a drain, respectively, and their surfaces are gate insulating layers.
Since P ions are implanted through 13, it does not get rough.

Then, after the photoresist film 26 is removed by etching, as shown in FIG. 3 (F), a photoresist film 27 is patterned again on the entire surface by the photolithography method, and the photoresist film 27 is used as a mask. p-MOS
B ions in the silicon substrate 1 corresponding to the p-MOS formation region are implanted through the gate insulating layer 18 to form two p-type regions 20. These two p-type regions 20 also serve as the source and drain, respectively.

After that, the photoresist film 28 is removed by etching, the photoresist film is patterned again by the photolithography method, and the thin film transistor 3 and each of the n-type regions 12, 17 and p of the C-MOS are patterned using this photoresist film as a mask. The portions of the gate insulating layers 13 and 18 corresponding to the mold region 20 are removed by etching. Then, an insulating protective film made of PSG is deposited on the entire surface by the atmospheric pressure CVD method, a photoresist film is patterned on the surface of the insulating protective film by a photolithography method, and the insulating protective film is used as a mask with the photoresist film as a mask. By etching, as shown in FIG. 3 (G), unnecessary portions, that is, the thin film heating element 2 and each n-type region 1
The portions corresponding to 2, 17 and the p-type region 20 are removed. As a result, the thin film transistor 3, each gate electrode 14 of the C-MOS, and the insulating layer 7 are covered with the insulating protective film 8 made of PSG.

Next, a low resistance metal film such as Al, Al-Si, Mo and W is formed on the entire surface by sputtering or vapor deposition, and a photoresist film is patterned on the surface by a photolithography method. The metal film is etched as a mask to remove unnecessary portions, and the thin film transistor 3 and the C-MO are removed as shown in FIG.
Wiring patterns 9, 15, 19, and 21 are formed on the portions of S corresponding to the n-type regions 12 and 17, the portion of the p-MOS corresponding to the p-type region 20, and the portions corresponding to the bump portion 4. The wiring patterns 15 and 19 are electrically connected to the n-type regions 12 and 17 and the p-type region 20, respectively. In this case, one wiring pattern 15 of the thin film transistor 3 is also electrically connected to one end (right end) of the heating resistance layer 7 of the thin film heating element 2. The wiring pattern 9 of the ground line is electrically connected to the other end (left end) of the heating resistance layer 7.

Thereafter, as shown in FIG. 3 (I), a protective film 10 is formed on the entire surface by sputtering, vapor deposition or the like. As described above, the protective film 10 has oxidation resistance and wear resistance, and has, for example, a two-layer structure of SiO ₂ and SiN, or a single layer of SiON. You may form. Further, the protective layer 9 is formed so that the portion of the thin film heating element 2 is higher than the other portions.

Then, a photoresist film is patterned on the surface of the protective film 10 by the photolithography method, and the protective film 10 is etched using the photoresist film as a mask to remove unnecessary portions, that is, unnecessary portions, as shown in FIG. 3 (J). Bump part 4
And the portion corresponding to. After that, the photoresist film is removed, and Ti-W is formed on the entire surface of the etched protective film 10.
The alloy and Au are deposited by vapor deposition or sputtering to form the metal layer 22. Further, a resist 28 is deposited on the surface of the metal layer 22 by spin coating, and the bump formation region is etched and removed. Then, the Au plating layer 23 is formed on the etched portion. As a result, the bump portion 4 which is the bump electrode is formed.

Finally, the portion to be diced is removed by etching, the resist 28 and the metal layer 22 described above are sequentially removed by etching, and the silicon substrate 1 is diced at predetermined locations to be individually cut off. Is obtained.

Therefore, according to the thermal head as described above, a large number of thin film heating elements 2, ...
Since the thin film transistors 3, ... And the C-MOS forming the shift register circuit, the latch circuit, the gate circuit, etc. are all integrally formed, the number of connection points is small, for example, about four,
The connection work is simple and the productivity is good, and the size of the entire device can be reduced. In particular, a thin film transistor 3 for driving a thin film heating element 2 made of polycrystalline silicon
Is a p-type region 11 formed by doping the n-type silicon substrate 1 on which the thin-film heat generating elements 2 are arranged with p-type impurities of B ions.
And p-type region 11 is doped with an n-type impurity of P ions to form an n-type region 12, and a wiring pattern is formed thereon.
Since the gate electrode 14 is formed via the gate insulating film 15 and the gate insulating film 13, the thin film transistor 3 is formed in the single crystal silicon substrate.
It is possible to form each channel of ..., By which, the mobility of electricity of the thin film transistor 3 is extremely good. Therefore, the width and length of the gate can be reduced,
A fine pitch can be achieved. As a result, it is possible to perform clear thermal recording with high resolution, which is suitable for high density printing.

Further, according to such a thermal head, the insulating film 6 and the gate insulating films 13 and 18 are formed on the silicon substrate 1, and the heating resistance layer 7 made of polycrystalline silicon is formed on the insulating film 6.
After forming the gate electrode 14 made of polycrystalline silicon on the gate insulating films 13 and 18, the wiring patterns 15 and 19 are formed, and the surfaces thereof are covered with the protective film 10. Even if the width and length of the gate are reduced to achieve a fine pitch, each element can be formed with high accuracy, and in addition to the thin film transistor 3, ...
-Even if a MOS is formed, the manufacturing process does not become complicated, so the productivity is extremely good.

Although the n-type regions 12 and 17 and the p-type region 20 are formed by ion implantation in the above-described embodiment, the present invention is not limited to this, and they may be formed by a thermal diffusion method. That is, when the n-type region is formed by the thermal diffusion method, the gate insulating film 13,
18 is etched away and P ions diffuse into p-type region 16. Therefore, it is sufficient to implant P ions into the heating resistance layer 7 of the thin film heating element 2 in a separate process.

In addition, in the above-described embodiment, the p-type region 20 is formed after forming the n-type regions 12 and 17, but the present invention is not limited to this.
The n-type regions 12 and 17 may be formed after forming 20. Alternatively, the polycrystalline silicon layer 25 may be formed after forming the n-type regions 12, 17 and the p-type region 20.

[Advantages of the Invention] As described above, in the thermal head and the method of manufacturing the same according to the present invention, since the active layer of the transistor forming the drive circuit portion including the shift register is single crystal silicon,
High-speed and high-resolution printing is possible, and since this drive circuit section is formed on the same substrate as the thin film resistance element for heat generation, the connection between the two is extremely simple and the thin film resistance element and the gate of each transistor Since both electrodes are made of polycrystalline silicon, it is possible to form them in the same process, which makes manufacturing more efficient. Furthermore, since the thin film resistance element is formed on a single crystal semiconductor substrate, sufficient accumulation of heat from the thin film resistance element is possible. Therefore, it is possible to maintain high print quality.

[Brief description of drawings]

1 to 3 show an embodiment of the present invention. FIG. 1 is an enlarged sectional view of a main part of a thermal head, and FIGS. 2 (A) and 2 (B).
Is a plan view of relevant parts showing different etching states of the heating resistance layer of the thin-film heating element, and FIGS. 3 (A) to 3 (J) are enlarged cross-sectional views in the manufacturing process of the thermal head. 1 ... Silicon substrate, 2 ... Thin film heating element, 3 ... Thin film transistor, 6 ... Insulating film, 7 ... Heating resistance layer, 10 ...
... Protection film, 11, 16, 20 ... p-type region, 12, 17 ... n-type region, 13, 18 ... gate insulating film, 14 ... gate electrode, 9,
15, 19, 21 …… Wiring pattern.

Continuation of the front page (56) Reference JP-A-58-92240 (JP, A) JP-A-61-141183 (JP, A) JP-A-54-161344 (JP, A) JP-A-62-204964 (JP , A) JP-A-62-33472 (JP, A) JP-A-63-265448 (JP, A) Actual Kaihei 1-110931 (JP, U) Actual Kaihei 1-93438 (JP, U)

Claims (2)

(57) [Claims] 1. A shift comprising a plurality of thin-film resistance elements made of polycrystalline silicon arranged in an array on a single crystal semiconductor substrate, and a transistor having a gate electrode made of polycrystalline silicon on the single crystal semiconductor substrate. A thermal head characterized in that a drive circuit section including a register is formed, and each thin film resistance element is a heat generating section driven by the drive circuit section. 2. A step of forming an insulating layer and a gate insulating layer on a single crystal semiconductor substrate, and, respectively, on the insulating layer and the gate insulating layer.
Forming a number of thin film resistance elements and gate electrodes made of polycrystalline silicon; diffusing impurities into at least each of the thin film resistance elements to reduce the resistance of the thin film resistance elements; diffusing impurities into the semiconductor substrate. To form a diffusion region and a wiring pattern made of a low resistance metal to form a drive circuit section including a shift register composed of a large number of transistors and connect the drive circuit section to each of the thin film resistance elements. A method of manufacturing a thermal head, comprising: a step; and a step of depositing an insulating protective film on the entire surface.