JP2591115B2 - Thermal head - Google Patents

Description

The present invention relates to a thermal head for performing thermal recording.

[Prior Art] Conventionally, as shown in FIG. 6, a thermal head for performing thermal recording by selective heat generation of heat generating elements has a large number of heat generating elements (resistors) 1 arranged on a substrate. The transistor elements 2 are connected to one end of each of the heating elements 1, and the other ends of the heating elements 1 are grounded to the ground 4 via a common ground line 3. In such a thermal head, when a drive signal is applied to the transistor elements 2 from the data latch section, a current selectively flows through the heating elements 1 to generate heat, and the heat is used to directly perform thermal recording on thermal paper. Alternatively, thermal recording is performed on recording paper via a thermal ink sheet.

[Problems to be Solved by the Invention] In such a thermal head, the current flowing through the heating element 1 and generating heat is grounded to the ground 4 via the common ground line 3, so that the wiring of the ground line 3 itself is provided. The current flowing through the heating element 1 may be divided by the resistance and flow back to another heating element 1. Such a reverse current causes the other heating elements 1 to generate heat, so that accurate thermal recording cannot be performed and the resolution is reduced. Therefore, there is a problem that the ground line 3 is greatly restricted by its wiring material and wiring shape.

That is, when a metal such as aluminum is used as the wiring material of the ground line 3, the width of the wiring is increased to reduce the wiring resistance. For example, if the width of the head is 8 mm, the width of the aluminum wiring (earth line) is 0.5 mm
However, since the resistance value is proportional to the length of the wiring, the width of the aluminum wiring becomes as large as about 2.5 mm with a head having a width of 40 mm.

In addition, when the width of the wiring is increased as described above, the heating element 1
Cannot be arranged at the edge of the substrate, so that the heat-generating element 1 is not used if the thermal paper or the recording paper is held on a flat surface.
Cannot be satisfactorily brought into contact with the thermal paper or thermal ink sheet. When a platen is used, the heating elements 1 may be located at the center, but when the size of the substrate is fixed, the distance from the transistor elements 2 cannot be large, so that the transistor elements 2. However, there is a problem that the heat is adversely affected.

Another object of the present invention is to enable the thin-film heating element to be reliably and satisfactorily brought into contact with thermal paper or a heat-sensitive ink sheet, and to increase the distance between the thin-film heating element and the transistor element without increasing the size of the substrate. Can be
An object of the present invention is to provide a thermal head capable of performing thermal recording satisfactorily without affecting the transistor element thermally.

[Means for Solving the Problems] The invention according to claim 1, wherein a number of thin-film heating elements are arranged on a semiconductor substrate, and ions are doped on an upper surface along one edge of the semiconductor substrate to form each of the thin-film heating elements. It is characterized by a thermal head in which a large number of diodes connected to the element are arranged and a ground line for commonly connecting the diodes is formed by laminating on each diode. Since a ground line arranged along one edge of the semiconductor substrate and commonly connecting each diode is laminated on each diode, a good print quality can be secured without increasing the size of the substrate.

According to a second aspect of the present invention, in the first aspect, a ground line for commonly connecting the diodes is formed in the semiconductor substrate. Since the ground line can be formed only by doping, manufacturing is facilitated.

Embodiment A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 3 shows a circuit configuration of the thermal head of the present invention. In this circuit configuration, the image signal is input to the D terminal of the shift register circuit 10 as a data signal. The clock signal is input to each Cl terminal of the shift register circuit 10.
The shift register circuit 10 receives one line of data according to a clock signal. All the data for one line input to the shift register circuit 10 is latched from the Q terminal of the shift register circuit 10 by the strobe signal input to each L terminal of the latch circuit 11 as a latch pulse.
The data is transferred in parallel to the D terminal 11 and held in the latch circuit 11. The data held in the latch circuit 11 is input from the Q terminal of the latch circuit 11 to the transistor element 13 via the AND gate circuit 12 in accordance with an instruction of an enable signal for determining a print timing or the like. The transistor element 13 is driven based on the input data, and selectively supplies a current to the thin-film heating element 14 to generate heat. When a current flows through the thin-film heating element 14 in this manner, it is grounded to the ground 17 via the diode 15 and the ground line 16. The diode 15 prevents a voltage from being divided by the wiring resistance of the ground line 16 and flowing back to another thin-film heating element 14 when a current flows through the ground line 16. In this case, the transistor element 13 is, for example, an n-MOS FET, and the other circuits, that is, the shift register circuit 10, the latch circuit 11, and the gate circuit 12 are C-MOS F
These are ET, which are formed together with a thin-film heating element 14 and a diode 15 on a silicon substrate 20 described later.

FIG. 1 shows the structure of a thermal head according to the present invention. In the figure, reference numeral 20 denotes an n-type silicon substrate (wafer). As described above, the n-MOS • FET, the C-MOS • FET, and the bump portion 21 are formed on the silicon substrate 20 together with the thin film heating element 14 and the diode 15. Hereinafter, the configuration of each element will be described in order.

The thin-film heating element 14 is a portion that generates heat, and is a silicon substrate.
20 is formed near the left end. That is, the heat generating portion 22 is formed on the upper surface of the silicon substrate 20 so as to protrude. The raised heat generating portion 22 is covered with an insulating film 23 of SiO ₂ , and on the surface of the insulating film 23, a heat generating resistance layer 24 formed by doping impurities into polycrystalline silicon is formed. As shown in FIGS. 2A and 2B, the heat generating portion 22 is formed so as to protrude in a trapezoidal cross section over the entire length of the silicon substrate 20 in the width direction (vertical direction in FIG. 1). Also, the heating resistance layer
24 are arranged at regular intervals at a pitch of 16 dots / mm along the longitudinal direction of the heat generating portion 22 described above. In this case, each of the heat generating resistance layers 24 is formed so as to extend from one lower surface of the heat generating portion 22 protruding in a trapezoidal cross section to the upper surface and continue to the other lower surface. This heating resistance layer
24 has a predetermined sheet resistance (several tens of Ω / □) by being doped with a predetermined amount of phosphorus (P) ions as impurities. That is, since the total resistance value of the heating resistance layer 24 is determined by the implantation concentration of phosphorus ions and the area thereof, the total resistance value is adjusted by the implantation amount of phosphorus ions and the amount of non-etching, and finally becomes about several tens to several hundreds Ω. Has been adjusted. In this case, each heating resistance layer 24 is
Only the portion facing the upper surface of 22 has the above-described predetermined sheet resistance (several tens of ohms / square), and the other portions have a smaller resistance. The details will be described later.
Then, a protective film 25 is formed on the surface of the heating resistance layer 24. This protective film 25 has oxidation resistance and abrasion resistance. Even if it has a two-layer structure of SiO ₂ and SiN,
It may be a single layer of iON.

The diode 15 is for preventing backflow to another thin-film heating element 14 when the thin-film heating element 14 generates heat, and is mounted on a silicon substrate.
It is formed at the left end of 20. That is, the silicon substrate 20
A p-type region 26 is formed by implanting boron (B) ions inside the upper surface of the substrate. The p-type region 26 forms the ground line 16 of the thin-film heating element 14 described above,
In the region of the p-type region 26, n-doped with P ions
A mold region 27 is formed. On the upper surface of the silicon substrate 20 in which the n-type region 27 is formed in the p-type region 26,
Except for the central part of the mold region 27, the same Si
An O ₂ insulating film 23 is formed, and the insulating film 23 and the n-type region
One end 28 of the heating resistance layer 24 of the thin-film heating element 14 is connected to the periphery of 27. This one end 28 is for conducting the thin film heating element 14 and the diode 15. On the upper surface of one end 28 of the heat generating resistance layer 24, a CVD (Chemical Vapor Deposi
An insulating protective film 29 made of link glass (PSG) and having a high insulating property is formed by the method, and the same protective film 25 as the thin-film heating element 14 is formed on the upper surface of the insulating protective film 29. The protective film 25 is formed to be lower than the protective film 25 of the thin-film heating element by the height of the heat generating portion 22. In other words, the protection film 25 of the thin-film heating element 14 is formed higher than that of the diode 15. The silicon substrate 20 itself serves as the ground line 16, and when such a thermal head is used, preferably, the bottom surface 20a of the silicon substrate 20 is connected to the ground line of the device.

The n-MOS constituting the transistor element 13 has a field effect (F
ET) type, and is formed in a portion of the silicon substrate 20 far away from the thin film heating element 14 to the right.
That is, a p-type region 30 doped with B ions is formed inside the upper surface side of the silicon substrate 20 in that portion,
In the region of the p-type region 30, P-doped 2
Two n-type regions 31, 31 are formed. These two n-type regions 31, 31 serve as source and drain electrodes, respectively. As described above, two n-type regions are formed on the upper surface of the silicon substrate 20 in which the n-type regions 31 and 31 are formed in the p-type region 30.
Except for the central portion including 31, 31, the same insulating film 23 as the thin-film heating element 14 is formed, and a portion located between the two n-type regions 31, 31 is a gate insulating film made of SiO _2. A gate electrode 33 made of the same polycrystalline silicon as the heating resistance layer 24 of the thin film heating element 14 is formed via
Source and drain wiring patterns 34, 34 are formed at locations corresponding to the two n-type regions 31, 31, respectively. In this case, the intermediate gate electrode 33 is formed with low resistance by doping P ions similarly to the thin-film heating element 14, and the entire surface is insulated in the same manner as the diode 15 so as not to be short-circuited with the wiring patterns 34, 34. It is covered with a protective film 29. Also,
Source and drain wiring patterns 34, 34 are Al, Al-S
It is made of a metal such as i, Mo, W, or the like, and is connected to two n-type regions 31, 31, respectively. One of the wiring patterns 34 is electrically connected to the side surface of the raised heat forming portion 22 of the thin film heating element 14. It is connected. Then, the thin film heating element is covered by covering the insulating protection film 29 on the wiring patterns 34, 34 and the gate electrode 33.
The same protective film 25 as 14 is formed. As is clear from FIG. 1, each heat generating resistance layer 24 is formed on the upper surface of the raised portion of the heat generating portion 22, and the upper surface is positioned so as to protrude from the upper surfaces of the wiring patterns 34, 34. In this structure, the upper surface of the protective film 25 coated on each heating resistance layer 24 is made flat. If the wiring pattern around each heating resistor layer 24 protrudes beyond each heating resistor layer 24, the protective film 25 coated on each heating resistor layer 24
Is depressed from its surroundings, so that a gap is formed between the protective film 25 facing each heat generating resistance layer 24 and the thermal paper, resulting in loss of heat conduction.

Further, as is apparent from FIG. 1, the protective film 25 in a region facing each heat generating resistance layer 24 is formed to protrude from both left and right portions thereof. This structure is extremely effective for bringing the surface of the protective film 25 in a region facing each heat generating resistance layer 24 into close contact with the thermal paper.

The C-MOS constituting the shift register circuit 10, the latch circuit 11, and the gate circuit 12 is of an FET type,
The MOS transistor and the p-MOS transistor 13
Are formed in the order of n-MOS and p-MOS close to the right side of. In this case, the n-MOS is the transistor element 13 described above.
It has exactly the same configuration as. That is, the silicon substrate
Inside the upper surface side of 20 is a p-type region 35 doped with B ions.
Are formed, and two n-type regions 36, 36 doped with P ions are formed in the p-type region 35. On this portion of the upper surface of the silicon substrate 20, two n-type regions 36 are provided.
Except for the central part including 36, the transistor element described above
An insulating film 23 of the same SiO _{2 as that} of 13 is formed, and a portion located between the two n-type regions 36 is the same polycrystalline as the transistor element 13 through a gate insulating film 37 of SiO _2. A gate electrode 33 made of silicon is formed, and source and drain wiring patterns 38, 38 are formed at locations corresponding to the two n-type regions 36, 36. Also in this case, the gate electrode 33 has a smaller doping amount of P ions than the heating resistance layer 24 of the thin film heating element 14, and its entire surface is the same as the diode 15 so as not to be short-circuited with the wiring patterns 38, 38. It is covered with an insulating protective film 29. Then, the same protective film 25 as the thin-film heating element 14 is formed so as to cover the wiring patterns 38, 38 and the insulating protective film 29 on the gate electrode 33.

The p-MOS has exactly the same configuration as the above-described n-MOS except that two p-type regions 39 and 39 are formed inside the upper surface side of the silicon substrate 20. That is, two p-type regions
On the upper surface of the silicon substrate 20 where 39 and 39 are formed, 2
Except for a central portion including the two p-type regions 39, 39, an insulating film 23 of SiO ₂ is formed. A gate insulating layer made of SiO ₂ is provided between the two p-type regions 39, 39. A gate electrode 33 made of polycrystalline silicon is formed through the film 37,
Source and drain wiring patterns 38, 38 are formed at locations corresponding to the two p-type regions 39, 39. Also in this case, the entire surface of the gate electrode 33 is covered with the insulating protection film 29 so as not to short-circuit with the wiring patterns 38, 38. And
A protective film 25 is formed to cover the wiring patterns 38, 38 and the insulating protective film 29 on the gate electrode 33.

The bump portion 21 is an electrode for taking in various signals into the C-MOS, and a plurality of (four in this embodiment, an image signal, a clock signal, a strobe signal, and an enable signal) are provided on the right end of the silicon substrate 20. That is, the silicon substrate 20
On the upper surface of the wiring pattern 40 formed via the insulating film 23 of SiO ₂ and the insulating protective film 29, a protective film 25 having a predetermined portion etched is formed, and in the etched portion,
A metal layer 41 such as a Ti-W alloy and Au is formed by vapor deposition or sputtering and connected to the wiring pattern 40, and an Au plating layer 42 is formed on the metal layer 41.

Next, a case of manufacturing the above-described thermal head will be described with reference to FIGS.

First, as shown in FIG. 4 (A), a silicon substrate (wafer) 20 is prepared, one surface of the silicon substrate 20 is etched, and a portion shown by a dotted line is removed to raise a region where the thin film heating element 14 is formed. Thus, a trapezoidal heat generating portion 22 is formed.
In this case, the thickness to be etched is several μm to several tens μm. Eshing is performed by plasma etching using a gas or a chemical solution containing hydrofluoric acid as a main component.

Thereafter, the silicon substrate 20 is heated to about 1000 ° C. to perform an oxidation process (thermal oxidation process),
An SiO ₂ film 43 is formed. Then, a photoresist film is patterned on the SiO ₂ film 43 by a photolithography method. That is, a photoresist film is applied and formed on the SiO ₂ film 43, and the photoresist film is exposed through a mask,
The exposed photoresist film is developed to remove unnecessary portions. Thereby, the photoresist film is patterned. Thus the SiO ₂ film 43 is etched using a photoresist film patterned as a mask, unnecessary portions such as shown in FIG. 4 (B), i.e. the diode
15, the transistor element 13, and each p-type region 2 of the C-MOS
The portions of the SiO ₂ film 43 corresponding to 6, 30, and 35 are removed. Then, in the portion of the silicon substrate 20 where the SiO ₂ film 43 has been removed, B
Ions are implanted and diffused to form p-type regions 26, 30 and 35 in the silicon substrate 20.

After that, the SiO ₂ film 43 is once removed, and the Si
An O ₂ film 44 is pattern-formed, a photoresist film (not shown) is formed on the surface of the SiO ₂ film by a photolithography method, and using this photoresist film as a mask,
A region corresponding to the region where the diode 15 is to be formed, that is, a portion corresponding to the p-type region 26 is removed by etching.
Is formed as shown in FIG. 4 (C). Then, the P-type region 26 of the diode 15 is
Ions are implanted to form an n-type region 27. in this case,
The gate insulating film 45 is formed in the n-type region 27 by implanting P ions.
To prevent roughening of the surface.

Thereafter, the SiO ₂ film 44 and the gate insulating film 45 are removed by etching, and the silicon substrate 20 is again subjected to a thermal oxidation treatment to form an SiO ₂ film on the surface. Then, a photoresist film is patterned by photolithography on the surface of the SiO ₂ film, SiO ₂ using the photoresist film as a mask
The film is etched, and as shown in FIG. 4 (D), the p-type regions 30, 35 of the transistor element 13 and the C-MOS and the SiO ₂ film corresponding to the formation region of the p-MOS are removed. Although not shown, in this state, the portion of the SiO ₂ film corresponding to the diode 15 is not removed. Then, the gate insulating films 32, 3 are dry-etched or oxidized with HCl in the removed portions.
Form 7. Thereafter, a photoresist film is formed again on the surfaces of the SiO ₂ insulating film 23 and the gate insulating films 32 and 37 by photolithography, and only the SiO ₂ film corresponding to the n-type region 27 of the diode 15 is removed. As shown in FIG. 3D, the n-type region 27 is brought into a state in which polycrystalline silicon can be contacted.

Then, a polycrystalline silicon layer 46 is formed on the entire surface by CVD using monosilane (SiH ₄ ) gas.
As shown in FIG. 4D, P ions are implanted into the entire polycrystalline silicon layer 46 to increase the P ion concentration of the polycrystalline silicon layer 46 in a portion corresponding to the heat generating portion 22 and to set the resistance to a predetermined value. Decrease. In this case, the P ion concentration is increased in consideration of the amount of P ions implanted in forming the n-type regions 31 and 36 in the subsequent step (the step of FIG. 4 (F)). deep. That is, the sheet resistance of the polycrystalline silicon layer 46 before implantation of P ions is several KΩ / □ to several MΩ.
/ □, which is finally reduced to several tens Ω / □. In addition,
In this case, the conductive layer 28 of the diode 15 and the transistor element
13 and the polycrystalline silicon layer 46 corresponding to each gate electrode 33 of C-MOS and the like and the polycrystalline silicon layer 46 corresponding to the heating resistance layer 24 of the thin film heating element 14 have the same P ion implantation amount. However, if a large amount of P ions is implanted into the polycrystalline silicon layer 46 of the thin-film heating element 14, a resist mask is applied to the thin-film heating element 14.
The P ions may be implanted again only into the polycrystalline silicon layer 46, or may be formed as separate steps by forming respective resist masks.

Thereafter, a photoresist film is patterned on the surface of the polycrystalline silicon layer 46 by photolithography, and using this photoresist film as a mask, the polycrystalline silicon layer 46 is formed.
Is etched to remove unnecessary portions. As a result, as shown in FIG.
14, a heat-generating resistor layer 24 formed by doping P ions into polycrystalline silicon, and respective doped electrodes 33 are formed in respective regions where the transistor element 13 and the C-MOS are formed. By the way, an important matter regarding each heating resistance layer 24 is that only a required heating portion is heated in order to improve resolution. For this reason, in the present embodiment, as shown in FIGS. 2A and 2B, the inside of the region A corresponding to the upper surface of the heat generating portion 22 is made to have a higher resistance than the portion outside the region. ing. FIG. 2 (A) shows a method of making the P ion concentration in the A region of each heating resistor layer 24 smaller than that in the region outside the region, or doping the A region with B ions. . FIG. 2B shows a method in which a slit S is formed in each heating resistance layer 24 in the region A and the width of the conductive path is narrower than the portion outside the region. Of course, a method combining both methods can also be adopted. In any case, the total resistance value of each heating resistance layer 24 is adjusted to, for example, several tens Ω to several hundred Ω.

Next, as shown in FIG. 4F, the p-MOS gate insulating film 37 is masked with a photoresist film 47, and the gate insulating film is formed in the p-type regions 30 and 35 of the transistor element 13 and the C-MOS. P ions are implanted through the film 32 to form two sets of n-type regions.
31 and 36 are formed. These two n-type regions 31 and 36 serve as a source and a drain, respectively, and each surface thereof is a gate insulating film.
Since the P ions are implanted via 32, the P ions are not roughened.

Then, after the photoresist film 47 is removed by etching, as shown in FIG. 4 (G), a photoresist film 48 is formed on the entire surface again by photolithography, and the photoresist film 48 is used as a mask. p-MOS
B ions are implanted into the silicon substrate 20 corresponding to the p-MOS formation region via the gate insulating film 37 to form two p-type regions 39. These two p-type regions 39 also serve as a source and a drain, respectively.

Thereafter, the photoresist film 48 is removed by etching, and a photoresist film is patterned again by a photolithography method, and the n-type regions 31, 36 of the transistor element 13 and the C-MOS are formed using the photoresist film as a mask. Portions of the gate insulating films 32 and 37 corresponding to the p-type region 39 are removed by etching. Then, an insulating protective film made of PSG is applied over the entire surface by a normal pressure CVD method, and a photoresist film is patterned on the surface of the insulating protective film by a photolithography method, and the insulating protective film is formed using the photoresist film as a mask. Then, as shown in FIG. 4H, unnecessary portions, that is, the thin film heating elements 14 and the respective n-type regions 3 are formed.
The portions corresponding to 1, 36 and the p-type region 39 are removed. As a result, one end 28 of the heating resistance layer 24 and the transistor element 1
3. The gate electrodes 33 of the C-MOS and the insulating layer 23 are made of PSG.
Covered with an insulating protective film 29 made of.

Next, a metal film having conductivity such as Al, Al-Si, Mo, W, etc. is formed on the entire surface by sputtering or vapor deposition, and a photoresist film is patterned on the surface by a photolithography method. Etching the metal film using the film as a mask to remove unnecessary parts,
As shown in FIG. 4 (I), a portion corresponding to the n-type regions 31 and 36 of the transistor element 13 and the C-MOS, a portion corresponding to the p-type region 39 of the p-MOS, and a portion corresponding to the bump portion 21 The wiring patterns 34, 38, and 40 are formed at the portions where they are to be formed. These wiring patterns 34 and 38 are in conduction with n-type regions 31 and 36 and p-type region 39, respectively. In this case, the transistor element
One of the wiring patterns 34 is also electrically connected to the heating resistance layer 24 of the thin-film heating element 14.

Thereafter, as shown in FIG. 4 (J), a protective film 25 is formed on the entire surface by sputtering or vapor deposition. The protective film 25 has oxidation resistance and abrasion resistance as described above. For example, the protective film 25 has a two-layer structure of SiO ₂ and SiN or a single layer of SiON or the like. It may be formed. The protective layer 25 is formed so that the portion of the thin-film heating element 14 is higher than other portions.

Then, a pattern of a photoresist film is formed on the surface of the protective film 25 by a photolithography method, and the protective film 25 is etched using the photoresist film as a mask. As shown in FIG. Bump part 21
And the portion corresponding to. Thereafter, the photoresist film is removed, and Ti-W
The metal layer 41 is formed by depositing an alloy and Au by vapor deposition or sputtering. Further, a resist 49 is applied to the surface of the metal layer 41 by spin coating, and the bump formation region is removed by etching. Then, the Au plating layer 42 is applied to the etched portion to form the bump 21 as a bump electrode.

Finally, the portion to be diced is removed by etching as shown in FIG.
41 is sequentially etched and removed, and the silicon substrate 20 is
When dicing is performed at a location indicated by a two-dot chain line in the drawing to separate the individual components, the thermal head of the present invention is obtained.

Therefore, according to the above-described thermal head, predetermined signals (image signals, clock signals, strobe signals, strobe signals, etc.) are transmitted from the bumps 21 to the C-MOS constituting the shift register circuit 10, the latch circuit 11, and the gate circuit 12. When an enable signal is supplied, the transistor element 14 is driven, and a current is selectively passed through the thin-film heating element 15 to generate heat. With this heat, thermal recording is performed on recording paper via thermal paper or thermal ink sheet. be able to.

In particular, according to such a thermal head, the current flowing through the thin-film heating element 14 and generating heat is grounded to the ground 17 through the diode 15, the p-type region 26 of the diode 15, which is the ground line 16, and the silicon substrate 20. Therefore, the diode 15 can reliably prevent the current from flowing back to the other thin-film heating element 14 due to the wiring resistance of the ground line 3 as in the related art. Therefore, it is possible to perform clear thermal recording with high resolution. Moreover, the diode 15
Therefore, it is not necessary to increase the wiring width of the ground line 3 to reduce the wiring resistance as in the related art, and the width of the ground line 16 can be reduced. Therefore, the diodes 15 can be arranged and formed at the left end of the silicon substrate 20, and accordingly, the thin film heating elements 14 can be arranged and formed near the left end of the silicon substrate 20.

Also, as described above, the diode 15 and the thin-film heating element 14
Is formed at the end of the silicon substrate 20, the thin film heating element 14
Can be in good contact with thermal paper or thermal ink sheet, etc. placed on a flat surface.
Without increasing the size of 20, the distance between the thin-film heating element 14 and the transistor element 13 can be greatly increased, so that the transistor element 13 is not adversely affected by heat. Therefore, the thin-film heating element 14 operates well, and clear thermal recording with good resolution can be performed.

Next, a second embodiment of the present invention will be described with reference to FIG. The second embodiment differs from the first embodiment only in the structure of the diode 50, and has the same configuration as that of the first embodiment.
That is, this diode 50 is
Ions are implanted to form a p-type region 51, and this p-type region
Except for the central portion of 51, an insulating film 23 of SiO ₂ is formed, and this insulating film 23 is covered with an insulating protective film 29 of PSG.
A wiring pattern 52 is formed on the central portion of the wiring pattern 52, and the wiring pattern 52 is covered with a protective film 25. In this case, the wiring pattern 52 forms the ground line 16 and is made of a metal such as Al, Al-Si, Mo, W, etc.
And the heating resistance layer 24 of the adjacent thin-film heating element 14 is also connected. In the second embodiment, if the silicon substrate 20 is not n-type, it is of course necessary to form an n-type semiconductor region around the p-type region 51. The wiring pattern 52 is connected to a ground (not shown), and the silicon substrate 20 is connected to a negative electrode of a power supply. Also in such a diode 50, the current generated by the thin-film heating element 14 can be prevented from flowing back to another thin-film heating element 14, so that the first
In addition to the same operation and effect as the embodiment, there is no need to particularly form an n-type region in the p-type region 51.
The distance between the transistor and the transistor element 13 can be further increased than in the first embodiment, and the manufacturing process can be simplified.

In the above-described embodiment, the n-type regions 27, 31, and 36 and the p-type region 39 are formed by ion implantation. However, the present invention is not limited to this, and may be formed by a thermal diffusion method. That is, when the n-type region is formed by the thermal diffusion method, the gate insulating film
32 and 37 are removed by etching, and P ions are p-type region 3
Spreads within 0,35. Therefore, P ions are implanted into the heating resistance layer 24 of the thin film heating element 14 in a separate step.

Further, in the above-described embodiment, the p-type region 39 is formed after the n-type regions 31 and 36 are formed.
The n-type regions 31, 36 may be formed after the formation of the 39. Alternatively, the polycrystalline silicon layer 46 may be formed after forming the n-type regions 31, 36 and the p-type region 39.

[Effects of the Invention] As described above, in the thermal head of the present invention, the diodes are arranged along one edge of the semiconductor substrate, and the ground lines that commonly connect the diodes are stacked on the diodes. Good printing quality can be ensured without increasing the size of the substrate. If a ground line for commonly connecting the diodes is formed in the semiconductor substrate, the ground line can be formed only by doping ions, so that the manufacturing is facilitated.

[Brief description of the drawings]

1 to 4 show a first embodiment of the present invention. FIG. 1 is an enlarged sectional view of a main part of a thermal head, and FIG. 2 (A).
(B) is a plan view of a principal part showing a different etching state of the polycrystalline silicon layer of the thin film heating element, FIG. 3 is a circuit configuration diagram of the thermal head shown in FIG. 1, and FIGS. 4 (A) to (K) are FIG. 5 is an enlarged sectional view of a main part of a thermal head according to a second embodiment, and FIG.
FIG. 1 is a schematic diagram showing a circuit configuration of a conventional thermal head. 14 ... Thin film heating element, 15, 50 ... Diode, 20 ... Silicon substrate.

Claims (2)

(57) [Claims] A plurality of thin-film heating elements arranged on a semiconductor substrate; a plurality of diodes connected to each of the thin-film heating elements by doping ions on an upper surface along one edge of the semiconductor substrate; A thermal head, wherein a ground line for connecting the diodes in common is formed on each diode. 2. A thermal head according to claim 1, wherein a ground line for commonly connecting said diodes is formed in said semiconductor substrate.