JP2775779B2 - Thermal head and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thermal head for performing thermal recording and a method for manufacturing the same.

[Prior Art] Conventionally, a thermal head that performs thermal recording by selective heat generation of a heating element has only a heating element on a substrate and is separate from a drive circuit unit. Therefore, the wiring section of the thermal head and the separate drive circuit section are connected by wire bonding. In such a thermal head, when a drive signal is supplied from a separate drive circuit unit to a wiring unit via a wire, the heating element selectively generates heat, and the heat causes the recording paper or the recording paper or the heat-sensitive ink sheet to pass through the heat-sensitive ink sheet. Perform thermal recording directly on thermal paper.

[Problems to be Solved by the Invention] In such a thermal head, the number of wiring portions of the heating element is large, and when the print dots have a fine pitch, the interval between the wiring portions becomes narrow. Connection becomes difficult. To cope with this problem, the wiring of the thermal head is widened in a fan shape from the heating element side. However, there is still a problem that the connection workability is poor and the entire apparatus becomes large.

Also, in the method of connecting the wiring part of the thermal head and the separate drive circuit part by wire bonding, extra height is required due to the slack of the wire, and it is also bonded and sealed with resin. After that, the degree of freedom of deformation is almost eliminated, so that there is a problem that the assembling becomes difficult and the long-term reliability is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to minimize the number of bump electrodes for connection, to reduce the size of the entire device, and to easily and easily connect bump electrodes without using wire bonding, thereby improving the connection workability. An object of the present invention is to provide a thermal head which is excellent, has high connection reliability, and is excellent in productivity, and a method of manufacturing the same.

[Means for Solving the Problems] A thermal head according to the present invention includes a plurality of thin-film resistance elements and circuit elements for driving the thin-film resistance elements arranged and formed on a substrate, and a wiring conductor having a plurality of pad portions. It is formed in a predetermined pattern, the entire surface of the substrate is covered with a protective film except for the pad portion, and a plurality of gold bump electrodes connected to the respective pad portions are projected on the protective film. It is formed.

Further, in the method of manufacturing a thermal head according to the present invention, a number of thin film heating elements and circuit elements are arrayed and formed on a substrate for each block, and thereafter, the thin film heating elements and the circuit elements are connected for each block. After forming a wiring conductor and a plurality of pad portions, covering the entire surface thereof with a protective film, removing the protective film in a portion corresponding to each of the pad portions, and forming a bump made of gold on each of the pad portions. In this method, electrodes are formed, and then the substrate is cut into blocks to obtain individual thermal heads.

[Operation] According to the thermal head of the present invention, since a large number of thin-film resistance elements and circuit elements for driving these are integrally formed on the substrate, the number of bump electrodes for connection to an external circuit can be extremely reduced. it can. Therefore, the size of the entire apparatus can be reduced, and the wire connection or the like is not used. Therefore, the connection work can be performed easily and easily, and the connection work can be improved. In addition, since a bump electrode made of gold is formed on the pad portion of the wiring conductor so as to protrude above the protective film, an external circuit or the like can be easily and reliably connected to the bump electrode, and the connection reliability is high. You can get things.

According to the method of manufacturing a thermal head of the present invention, a large number of thin film heating elements, circuit elements, wiring conductors, and a plurality of pad portions are formed on a substrate for each block, and the entire surface is covered with a protective film. After that, the protective film in a portion corresponding to each of the pad portions is removed, and a bump electrode made of gold is formed on each of the pad portions. Thereafter, the substrate is cut for each block to obtain individual thermal components. Since the heads are obtained, a large number of thermal heads can be obtained at one time, and the productivity is extremely good.

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

FIG. 3 shows a circuit configuration of the thermal head of the present invention. In this circuit configuration, the image signal is input to the D terminal of the shift register circuit 1 as a data signal. The clock signal is input to each C1 terminal of the shift register circuit 1.
The shift register circuit 1 receives one line of data according to a clock signal. All data for one line input to the shift register circuit 1 is transferred from the Q terminal of the shift register circuit 1 to the D terminal of the latch circuit 2 by a strobe signal input to each L terminal of the latch circuit 2 as a latch pulse. The data is transferred in parallel and held in the latch circuit 2. The data held in the latch circuit 2 is input from the Q terminal of the latch circuit 2 to the transistor element 4 via the AND gate circuit 3 according to an instruction of an enable signal for determining a print timing or the like. The transistor element 4 is driven based on the input data, and selectively supplies a current to the thin-film heating element 5 to generate heat. When a current flows through the thin-film heating element 5 in this manner, it is grounded to the ground 8 via the diode 6 and the ground line 7. This diode 6 prevents a voltage from being divided by the wiring resistance of the earth line 7 and flowing back to another thin film heating element 5 when a current flows to the earth line 7. In this case, the transistor element 4 is, for example, an n-MOS-FET, and the other circuits, that is, the shift register circuit 1, the latch circuit 2, and the gate circuit 3 are C-MOS-F
These are formed together with the thin-film heating element 5 and the diode 6 on a silicon substrate 10 described later.

FIG. 1 shows the structure of a thermal head according to the present invention. In the figure, reference numeral 10 denotes a single-crystal n-type silicon substrate (wafer). The silicon substrate 10 includes a plurality of thin film heating elements 5 and diodes 6 along with n-MOS FETs and C
-MOS • FET and a plurality of bump electrodes 11 are formed, and each block is cut so that one block forms a thermal head. Hereinafter, the configuration of each element will be described in order.

The thin-film heating element 5 is a portion that generates heat, and is a silicon substrate.
10 is formed near the left end. That is, the heat generating portion 12 is formed on the upper surface of the silicon substrate 10 so as to protrude. The raised heat generating portion 12 is covered with an insulating film 13 of SiO ₂ , and on the surface of the insulating film 13, a heat generating resistance layer 14 formed by doping polycrystalline silicon with impurities is formed. As shown in FIGS. 2A and 2B, the heat generating portion 12 extends over the entire length of the silicon substrate 10 in the width direction (vertical direction in FIG. 1).
It is formed to protrude in a trapezoidal cross section. Further, the heat generating resistance layer 14 is formed along the longitudinal direction of the heat generating portion 12 described above.
They are arranged at regular intervals with a pitch of up to 32 dots / mm. In this case, each of the heat generating resistance layers 14 is formed so as to extend from one lower surface of the heat generating portion 12 raised in a trapezoidal cross section to the upper surface and to continue to the other lower surface. The heating resistance layer 14 is doped with a predetermined amount of phosphorus (P) ion as an impurity, so that a predetermined sheet resistance (several tens Ω /
□). That is, since the total resistance value of the heating resistance layer 14 is determined by the implantation concentration of P ions and the area thereof, it is adjusted by the implantation amount of P ions and the amount of non-etching, and finally several tens to several hundreds Ω. It has been adjusted to the extent. In this case, in each heating resistance layer 14, only the portion facing the upper surface of the heat generation portion 12 has the above-described predetermined sheet resistance (several tens of Ω / □), and the other portions have a smaller resistance. It is said. The details will be described later. Then, a protective film 15 is formed on the surface of the heating resistance layer 14. The protective film 15 has oxidation resistance and wear resistance, and may have a two-layer structure of SiO ₂ and SiN or a single layer of SiON.

The diode 6 prevents backflow to another thin-film heating element 5 when the thin-film heating element 5 generates heat.
It is formed at the left end of 10. That is, the silicon substrate 10
A p-type region 16 is formed by implanting boron (B) ions inside the upper surface of the substrate. The p-type region 16 forms the ground line 7 of the thin-film heating element 5 described above.
In the region of the p-type region 16, P-doped n
A mold region 17 is formed. On the upper surface of the silicon substrate 10 in which the n-type region 17 is formed in the p-type region 16,
Except for the central part of the mold region 17, the same Si as the thin film heating element 5 is used.
An O ₂ insulating film 13 is formed, and one end 18 of the heating resistance layer 14 of the thin film heating element 5 is connected to the center of the n-type region 17.
This one end 18 is for conducting the thin film heating element 5 and the diode 6. Then, on the upper surface of one end 18 of the heat generating resistance layer 14, a highly insulating insulating protective film 19 made of linked glass (PSG) is formed by a CVD (Chemical Vapor Deposition) method. Is formed with the same protective film 15 as the thin-film heating element 5. This protective film 15
Is formed lower than the protective film 15 of the thin-film heating element by the height of the heat generating portion 12. In other words, the thin film heating element 5
Is formed higher than that of the diode 6. The silicon substrate 10 itself serves as the ground line 7, and when using such a thermal head, the bottom surface 10a of the silicon substrate 10 is preferably connected to the ground line of the device.

The n-MOS constituting the transistor element 4 has a field effect (F
ET) type, and is formed in a portion of the silicon substrate 10 far away to the right from the thin film heating element 5.
That is, a p-type region 20 doped with B ions is formed inside the upper surface side of the silicon substrate 10 in that portion,
Two n-type regions 21, 21 doped with P ions are formed in the p-type region. The two n-type regions 21 and 21 form source and drain electrodes, respectively. As described above, two n-type regions 2 are formed on the upper surface of the silicon substrate 10 in which the n-type regions 21 and 21 are formed in the p-type region 20.
Except for the central portion including 1 and 21, the same insulating film 13 as the thin-film heating element 5 is formed. A gate insulating film made of SiO ₂ is provided between the two n-type regions 21 and 21. A gate electrode 23 made of the same polycrystalline silicon as the heating resistance layer 14 of the thin film heating element 5 is formed via
Source and drain wiring patterns 24, 24 are formed at locations corresponding to the two n-type regions 21, 21, respectively. In this case, the intermediate gate electrode 23 is formed with low resistance by doping P ions like the thin-film heating element 5, and the entire surface thereof is insulated in the same manner as the diode 6 so as not to short-circuit with the wiring patterns 24, 24. It is covered with a protective film 19. Also,
Source and drain wiring patterns 24, 24 are Al, Al-S
It is made of a low-resistance metal such as i, Mo, W, or the like, and is connected to two n-type regions 21 and 21 respectively.
Reference numeral 24 is electrically connected to the lower portion of the side surface of the raised heat forming portion 12 of the thin film heating element 5. And this wiring pattern
The same protective film 15 as that of the thin-film heating element 5 is formed so as to cover the insulating protective film 19 on the gate electrodes 23 and 24, 24. As is clear from FIG. 1, each heating resistance layer 14 is formed on the upper surface of the raised portion of the heat generating portion 12, and the upper surface is formed by a wiring pattern.
24, 24 are positioned so as to protrude from the upper surface. In this structure, the upper surface of the protective film 15 which is coated on each heat generating resistance layer 14 is made flat. If the wiring pattern around each heating resistor layer 14 protrudes beyond each heating resistor layer 14, the protective film 15 coated on each heating resistor layer 14 faces each heating resistor layer 14. Since the portion to be depressed is more depressed than its surroundings, a gap is formed between the protective film 15 facing each heating resistor layer 14 and a heat-sensitive ink sheet 48 to be described later, and heat conduction is lost. Further, as is apparent from FIG. 1, the protective film 15 in a region facing each heat generating resistance layer 14 is formed to protrude from both left and right portions thereof. This structure
This is extremely effective in bringing the surface of the protective film 15 in the region facing each heat-generating resistor layer 14 into close contact with the thermal ink sheet 48.

The C-MOS constituting the shift register circuit 1, the latch circuit 2, and the gate circuit 3 is of the FET type,
The above-described transistor element 4 comprising a MOS and a p-MOS
Are formed in the order of n-MOS and p-MOS close to the right side of. In this case, the n-MOS is the transistor element 4 described above.
It has exactly the same configuration as. That is, the silicon substrate
Inside the upper surface side of 10 is a p-type region 25 doped with B ions.
Are formed, and two n-type regions 26, 26 doped with P ions are formed in the p-type region 25. On this portion of the upper surface of the silicon substrate 10, two n-type regions 26,
Except for the central portion including 26, the same SiO ₂ insulating film 13 as that of the above-described transistor element 4 is formed, and a gate made of SiO ₂ is provided between two n-type regions 26, 26. A gate electrode 23 made of the same polycrystalline silicon as the transistor element 4 is formed via an insulating film 27, and source and drain wiring patterns 28, 28 are formed at locations corresponding to the two n-type regions 26, 26. ing. Also in this case, the gate electrode 23 is formed with low resistance by doping P ions similarly to the thin-film heating element 5, and the entire surface is insulated in the same manner as the diode 6 so as not to short-circuit with the wiring patterns 28, 28. It is covered with a protective film 19. Then, the same protective film 15 as the thin film heating element 5 is formed so as to cover the wiring patterns 28, 28 and the insulating protective film 19 on the gate electrode 23.

The p-MOS has exactly the same configuration as the above-described n-MOS except that two p-type regions 29, 29 are formed inside the upper surface of the silicon substrate 10. That is, two p-type regions
2 is formed on the upper surface of the silicon substrate 10 where the 29 and 29 are formed.
Except for a central portion including the two p-type regions 29, 29, an insulating film 13 of SiO ₂ is formed. A gate insulating layer of SiO ₂ is provided between the two p-type regions 29, 29. A gate electrode 23 made of polycrystalline silicon is formed through a film 27,
Source and drain wiring patterns 28, 28 are formed at locations corresponding to the two p-type regions 29, 29. Also in this case, the entire surface of the gate electrode 23 is covered with the insulating protective film 19 so as not to short-circuit with the wiring patterns 28, 28. And
A protective film 15 is formed to cover the wiring patterns 28, 28 and the insulating protective film 19 on the gate electrode 23.

The bump electrode 11 is an electrode for taking in various signals into the C-MOS, and a plurality of (four in this embodiment, an image signal, a clock signal, a strobe signal, and an enable signal) are provided on the right end of the silicon substrate 10. That is, the silicon substrate
On the upper surface of the wiring pattern 30 formed on the insulating film 13 of SiO ₂ and the insulating protective film 19 on the protective film 15, a protective film 15 having a predetermined portion etched is formed. In the etched portion, a pad portion 31 formed by laminating a Ti-W alloy as a barrier metal and Au as an adhesion metal by vapor deposition, sputtering, or the like is formed so as to be electrically connected to the wiring pattern 30. The bump electrode 11 is formed on the pad portion 31 by Au plating. In this case, the pad
As barrier metal of 31 other than Ti-W alloy, Ti, Cu,
It may have a single-layer structure or a laminated structure of Ti-N, W, W-Si or the like, and the metal for adhesion may have a single-layer structure or a laminated structure of Cr, Pb, Sn or the like. , A solder-based alloy may be used.

Next, a case of manufacturing the above-described thermal head will be described with reference to FIGS.

In this case, each thermal head is obtained by dividing a single wafer into a number of blocks, forming necessary elements for each block simultaneously, and finally cutting each block. The description shows only one block of the upper wafer.

First, as shown in FIG. 4 (A), a single-crystal n-type silicon substrate (wafer) 10 is prepared, one surface of the silicon substrate 10 is etched, and a portion shown by a dotted line is removed to remove the thin-film heating element 5. The trapezoidal heat generating portion 12
To form In this case, the thickness to be etched is several μm to
It is several tens μm. The etching is performed by plasma etching using a gas or a chemical solution containing hydrofluoric acid as a main component.

Thereafter, the silicon substrate 10 is heated to about 1000 ° C. to perform an oxidation process (thermal oxidation process), and the surface of the silicon substrate 10 is
An SiO ₂ film 33 is formed. Then, a photoresist film is patterned on the SiO ₂ film 33 by a photolithography method. That is, a photoresist film is applied and formed on the SiO ₂ film 33, and the photoresist film is exposed through a mask,
The exposed photoresist film is developed to remove unnecessary portions. Thereby, the photoresist film is patterned. The SiO ₂ film 33 is etched using the photoresist film thus patterned as a mask, and unnecessary portions as shown in FIG. 4B, that is, the diode 6, the transistor element 4, and each p-type of the C-MOS. Type area 1
The portions of the SiO ₂ film 33 corresponding to 6, 20, and 25 are removed. Then, the silicon substrate 10 in the portion where the SiO ₂ film 33 has been removed
Ions are implanted and diffused to form a large number of p-type regions 16, 20, and 25 in the silicon substrate 10 for each block.

Thereafter, the SiO ₂ film 33 is once removed, and the Si
An O ₂ film 34 is formed, a photoresist film (not shown) is patterned on the surface of the SiO ₂ film by a photolithography method, and the region where the diode 6 is formed, that is, the p-type region 16 is formed using the photoresist film as a mask. Then, a portion corresponding to is removed by etching, and a gate insulating film 35 is formed on this portion as shown in FIG. 4 (C). Then, P ions are implanted into the p-type region 16 of the diode 6 via the gate insulating film 35 to form an n-type region 17. In this case, the gate insulating film 35 prevents the surface of the n-type region 17 from being roughened by implantation of P ions.

Thereafter, the SiO ₂ film 34 and the gate insulating film 35 are removed by etching, and the silicon substrate 10 is again subjected to thermal oxidation to form an SiO ₂ film on its surface. Then, a photoresist film is patterned by photolithography on the surface of the SiO ₂ film, SiO ₂ using the photoresist film as a mask
The film is etched, and as shown in FIG. 4D, the p-type regions 20, 25 of the transistor element 4 and the C-MOS and the SiO ₂ film corresponding to the formation region of the p-MOS are removed. Although not shown, in this state, the swelling SiO ₂ film corresponding to the diode 6 is not removed. Then, the gate insulating films 22 and 2 are formed on the removed portions by dry or oxidation of HCl.
Form 7. Thereafter, a photoresist film is formed on the surfaces of the SiO ₂ film insulating film 13 and the gate insulating films 22 and 27 again by photolithography, and then the n-type region 17 of the diode 6 is formed.
Only the SiO ₂ film corresponding to the above is removed, and as shown in FIG. 4D, the n-type region 17 is brought into contact with the polycrystalline silicon.

Then, a polycrystalline silicon layer 36 is formed on the entire surface by CVD using monosilane (SiH ₄ ) gas.
As shown in FIG. 4D, P ions are implanted into the entire polycrystalline silicon layer 36 to increase the P ion concentration of the polycrystalline silicon layer 36 in a portion corresponding to the heat generating portion 12, and to set the resistance to a predetermined value. Decrease. In this case, the P ion concentration is increased in consideration of the amount of P ions implanted when the n-type regions 21 and 26 are formed in the subsequent step (the step of FIG. 4 (F)). deep. That is, the sheet resistance of the polycrystalline silicon layer 36 before implantation of P ions is several KΩ / □ to several MΩ.
/ □, which is finally reduced to several tens Ω / □. In addition,
In this case, a polycrystalline silicon layer 36 corresponding to each of the gate electrodes 23 of the transistor element 4 and the C-MOS and the like, and a polycrystalline silicon layer 36 corresponding to the heating resistance layer 14 of the thin film heating element 5 are formed.
However, if the implantation amount of P ions is equal, only one process is required. However, if the implantation amount of P ions into the polycrystalline silicon layer 36 of the thin-film heating element 5 is large, a resist mask is used. May be performed, and P ions may be implanted again only into the polycrystalline silicon layer 36 of the thin-film heating element 5, or may be formed as separate steps by forming respective resist masks.

Thereafter, a photoresist film is patterned on the surface of the polycrystalline silicon layer 36 by photolithography, and using this photoresist film as a mask, the polycrystalline silicon layer 36 is formed.
Is etched to remove unnecessary portions. As a result, as shown in FIG. 4 (E), in each of the formation regions of the diode 6, the thin film heating element 5, the transistor element 4, and the C-MOS, a heating resistance layer formed by doping P ions into polycrystalline silicon. 14, and the respective gate electrodes 23 are formed. By the way, an important matter regarding each heating resistance layer 14 is that only a required heating portion is heated in order to improve resolution. For this reason, in this embodiment, as shown in FIGS. 2A and 2B, the inside of the region A corresponding to the upper surface of the heat generating portion 12 is made to have a higher resistance than the portion outside the region. ing. As a method for this, in FIG. 2 (A), a method of making the P ion concentration in the A region of each heating resistance layer 14 smaller than that outside the region or doping the B ion outside the A region is adopted. Show. FIG. 2B shows a method in which a slit S is formed in each heating resistance layer 14 in the region A and the width of the conductive path is made narrower than the region outside the region. Of course, a method combining both methods can also be adopted. In any case, the total resistance value of each heating resistance layer 14 is adjusted to, for example, several tens Ω to several hundred Ω.

Next, as shown in FIG. 4 (F), the gate insulating film 27 of the p-MOS is masked with a photoresist film 37, and the gate insulating film is formed in the p-type regions 20 and 25 of the transistor element 4 and the C-MOS. P ions are implanted through the film 22 to form two sets of n-type regions.
21 and 26 are formed. These two n-type regions 21 and 26 serve as a source and a drain, respectively.

Then, after removing the photoresist film 37 by etching, as shown in FIG. 4 (G), a photoresist film 38 is again formed on the entire surface by photolithography, and the photoresist film 38 is used as a mask. p-MOS
B ions are implanted into the silicon substrate 10 corresponding to the p-MOS formation region via the gate insulating film 27 to form two p-type regions 29. These two p-type regions 29 also serve as a source and a drain, respectively.

Thereafter, the photoresist film 38 is removed by etching, and a photoresist film is patterned again by the photolithography method. Using the photoresist film as a mask, the n-type regions 21, 26 of the transistor element 4 and the C-MOS are formed. Portions of the gate insulating films 22 and 27 corresponding to the p-type region 29 are removed by etching. Then, an insulating protective film made of PSG is applied over the entire surface by a normal pressure CVD method, and a photoresist film is patterned on the surface of the insulating protective film by a photolithography method, and the insulating protective film is formed using the photoresist film as a mask. Then, as shown in FIG. 4H, unnecessary portions, that is, the thin film heating elements 5 and the n-type regions 2 are removed.
The portions corresponding to 1, 26 and p-type region 29 are removed. As a result, one end 18 of the heating resistor layer 14, the transistor element 4, the gate electrodes 23 of the C-MOS, and the insulating layer 13
It is covered with an insulating protective film 19 made of.

Next, a metal film having conductivity such as Al, Al-Si, Mo, W, etc. is formed on the entire surface by sputtering or vapor deposition, and a photoresist film is patterned on the surface by a photolithography method. Etching the metal film using the film as a mask to remove unnecessary parts,
As shown in FIG. 4 (I), a portion corresponding to each of the n-type regions 21 and 26 of the transistor element 4 and the C-MOS, a portion corresponding to the p-type region 29 of the p-MOS, and a portion corresponding to the bump electrode 11 The wiring patterns 24, 28, and 30 are formed in the portions to be formed. Each of the wiring patterns 24 and 28 has an n-type region 21, 26 and p
It becomes conductive with the mold region 29. In this case, one wiring pattern 24 of the transistor element 4 is also electrically connected to the heating resistance layer 14 of the thin film heating element 5.

Thereafter, as shown in FIG. 4 (J), a protective film 15 is formed on the entire surface by sputtering or vapor deposition. The protective film 15 has oxidation resistance and wear resistance as described above, and has, for example, a two-layer structure of SiO ₂ and SiN, or a single layer of SiON, and is formed by a CVD method. It may be formed. The protective layer 15 is formed so that the portion of the thin film heating element 5 is higher than other portions.

Then, a pattern of a photoresist film is formed on the surface of the protective film 15 by a photolithography method, and the protective film 15 is etched using the photoresist film as a mask, as shown in FIG. Bump electrode
The part corresponding to 11 is removed. Thereafter, the photoresist film is removed, and a Ti-W alloy as a barrier metal and a metal for adhesion are formed on the entire surface of the etched protective film 15.
The metal layer 32 is formed by sequentially depositing Au by vapor deposition or sputtering. Further, a resist 39 is applied to the surface of the metal layer 32 by spin coating, and the bump formation region is removed by etching. Then, Au plating is applied to the etched portion to form the bump electrode 11. The height of the bump electrode 11 is
10 to maximize the joint strength with the external electrode
About 30 μm.

Finally, the dicing portion of the silicon substrate 10 is removed by etching as shown in FIG.
9 and the metal layer 32 other than the pad portion 31 are sequentially etched and removed, and the silicon substrate 10 is diced at each block, that is, at a location indicated by a two-dot chain line in FIG. A thermal head is obtained.

Next, a case where the above-described thermal head is connected to the circuit board 43 of the device and used will be described with reference to FIGS.

As shown in FIG. 5, this thermal head has a rectangular flat plate shape, and has a heating section 40 formed of a thin film heating element 5 and a diode 6 at the left end of the upper surface. A drive circuit section 41 made of a C-MOS is formed, and four bump electrodes 11 are provided at the upper right corner.
A flexible sheet 42 is connected to the bump electrodes 11, and is connected to a circuit board 43 of the device via the flexible sheet 42. In the flexible sheet 42, a plurality of wirings 45, which are formed by etching a copper foil and applying solder plating on the lower surface of a flexible film 44, are formed in a pattern. One end of each of the wirings 45 has a plurality of bump electrodes 11 ... As shown in FIG. 6, they are joined at one time by thermocompression bonding of a thermocompression jig 46, and the joined portions are covered with an insulating adhesive 47 such as silicon rubber. Also,
The other end of each wiring 45 is connected to a circuit board 43 by a similar thermocompression jig 46.
This joint is also covered with an insulating adhesive 47 such as silicon rubber. The circuit board 43 drives the thermal head drive circuit 41 by supplying an image signal, a clock signal, a strobe signal, and an enable signal.

Thus, the circuit board 43 is provided via the flexible sheet 42.
As shown in FIG. 7, the thermal head connected to
The heat generating portion 40 and the drive circuit portion 41 are positioned on the lower surface side while being bent at the portion of the flexible sheet 42 and held in a state of being inclined to the left with respect to the circuit board 43 in a vertical state. Therefore, the heat generating portion 40 of the thermal head is located at the lower left end, and the heat generating portion 40 is in close contact with the recording paper 49 via the thermal ink sheet 48.

In this state, when a predetermined signal (image signal, clock signal, strobe signal, enable signal) is given from the circuit board 43 to the bump electrodes 11 of the thermal head via the flexible sheet 42, the drive circuit section 41 operates. Then, the transistor element 5 selectively supplies a current to the thin-film heating element 6 of the heating section 40 to generate heat, and the heat transfers the ink of the thermal ink sheet 48 to the recording paper 49 to perform thermal recording. In this case, since the surface of the protective film 15 in that portion of the heat generating portion 40 protrudes more than the protective film 15 in the other portion due to the protrusion of the heat generating portion 12, only the surface of the heat generating portion 40 is good for the thermal ink sheet 48. , So that clear thermal recording can be performed. In particular, since the thin-film heating element 5 of the heating section 40 is connected to the diode 6, the diode 6 can reliably prevent the backflow of the current, so that high-resolution thermal recording can be performed.

Therefore, according to the above-described thermal head, since a large number of thin film heating elements 5, transistor elements 4, and C-MOSs are integrally formed on the silicon substrate 10, the bump electrodes for connection of the external circuit board 43 and the like are formed. The number of 11 can be reduced to the minimum (several). This eliminates the necessity of expanding the wiring portion in a fan shape as in the related art, so that the entire device can be made compact. In particular, since the number of the bump electrodes 11 is about four and is formed so as to protrude above the protective film 15, the connection workability is good, and the connection can be performed reliably and well. Moreover, this connection does not need to be connected one by one by wire bonding as in the related art, and a plurality of bump electrodes 11 can be connected at once by the thermocompression jig 46.
Can be easily and easily connected, and the productivity is extremely good.Moreover, the bump electrode 11 is formed on the pad portion 31 which is electrically connected to the wiring pattern 30 at the portion where the protective film 15 is etched. In addition, since the pad portion 31 is made of a barrier metal having high conductivity and a metal for adhesion, conduction reliability is extremely high.

In the above-described thermal head, the thin-film heating element 5, the diode 6, the transistor element 4,
Since each element such as C-MOS and C-MOS can be simultaneously formed in parallel, productivity is extremely high.

Note that the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, it is not necessary to perform the thermal recording on the recording paper 49 via the thermal ink sheet 48, and the thermal recording may be performed by bringing the heating section 40 of the thermal head into direct contact with the thermal paper. Also, one end of the thin-film heating element 5 does not necessarily need to be connected to the diode 6, but may be connected to a wiring pattern as a ground line made of a low-resistance metal.

In the above-described embodiment, the n-type regions 17, 21, 26 and the p-type region 29 are formed by ion implantation. However, the present invention is not limited to this, and may be formed by a thermal diffusion method. That is, when the n-type region is formed by the thermal diffusion method, the gate insulating film
22 and 27 are removed by etching, and P ions are p-type region 2
Spreads in 0,25. Therefore, P ions are implanted into the heating resistance layer 14 of the thin film heating element 5 in a separate step.

Further, in the above-described embodiment, the p-type region 29 is formed after the n-type regions 21 and 26 are formed.
The n-type regions 21 and 26 may be formed after the formation of 29. Alternatively, the polycrystalline silicon layer 36 may be formed after forming the n-type regions 21 and 26 and the p-type region 29.

Furthermore, although each element was formed on the single crystal silicon substrate 10, the present invention is not limited to this. A polycrystalline silicon layer is formed on the surface of the insulating substrate, and a predetermined impurity is doped into the polycrystalline silicon layer to form a thin film heating element. 5 and each element such as a transistor may be formed.

[Effects of the Invention] As described in detail above, according to the thermal head of the present invention, since a large number of thin film resistance elements and circuit elements for driving the thin film resistance elements are integrally formed on the substrate, the overall size of the apparatus can be reduced. In addition to this, the number of bump electrodes for connection to an external circuit can be extremely reduced, and the connection operation can be made simple and easy. In addition, since a bump electrode made of gold is formed on the pad portion of the wiring conductor so as to protrude above the protective film, an external circuit or the like can be connected to the bump electrode reliably and satisfactorily, and a connection with high connection reliability can be obtained. Can be.

According to the method of manufacturing a thermal head of the present invention, a large number of thin film heating elements, circuit elements, wiring conductors, and a plurality of pad portions are formed on a substrate for each block, and the entire surface is covered with a protective film. After that, the protective film in a portion corresponding to each of the pad portions is removed, a bump electrode made of gold is formed on each of the pad portions, and thereafter, the substrate is cut into blocks to form individual thermal heads. , A large number of thermal heads can be obtained at one time, and the productivity is extremely good.

[Brief description of the drawings]

1 to 7 show an embodiment of the present invention. FIG. 1 is an enlarged sectional view of a main part of a thermal head, and FIGS. 2 (A) and 2 (B).
3 is a plan view of a principal part showing different etching states of the polycrystalline silicon layer of the thin film heating element, FIG. 3 is a circuit configuration diagram of the thermal head of FIG. 1, and FIGS. FIG. 5 is a plan view showing a state in which a flexible sheet is joined to a thermal head. FIG. 6 is a view showing a state in which the flexible sheet is joined to a thermal head by a thermocompression jig. FIG. 4 is a diagram showing a use state of the thermal head. 4 ... transistor element, 5 ... thin film heating element, 10 ...
Silicon substrate, 11 ... bump electrode, 14 ... heating resistance layer,
15 ... Protective film, 24, 28, 30 ... Wiring pattern, 31 ... Pad part.

Claims (2)

(57) [Claims] 1. Excluding a plurality of thin-film resistance elements, a circuit element for driving each of the thin-film resistance elements, a wiring conductor having a plurality of pad portions, formed in a predetermined pattern, and excluding each of the pad portions. A protective film covering each of the thin-film resistance elements, the circuit element and the wiring conductor, and a plurality of bump electrodes made of gold formed on each of the pad portions, provided on a single semiconductor substrate. Characteristic thermal head. 2. A step of dividing a substrate into a plurality of blocks and arranging and forming a large number of thin-film heating elements and circuit elements for each block; and wiring for connecting the thin-film heating elements and circuit elements for each block. A step of forming a conductor and a plurality of pad portions; a step of covering the entire surface of the substrate with a protective film; a step of removing the protective film in a portion corresponding to each pad portion formed on the substrate; A method of manufacturing a thermal head, comprising: a step of forming a bump electrode made of gold on a pad portion; and a step of cutting the substrate into blocks to obtain individual thermal heads.