JPS61141183A - Manufacture of mos semiconductor integrated circuit device - Google Patents
Manufacture of mos semiconductor integrated circuit deviceInfo
- Publication number
- JPS61141183A JPS61141183A JP26393284A JP26393284A JPS61141183A JP S61141183 A JPS61141183 A JP S61141183A JP 26393284 A JP26393284 A JP 26393284A JP 26393284 A JP26393284 A JP 26393284A JP S61141183 A JPS61141183 A JP S61141183A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- diffusion layers
- oxide film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims abstract 2
- 230000005669 field effect Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 3
- 239000002784 hot electron Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002250 progressing effect Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はｂＭｏｓｔｔ界効果トランジスタを構成要素と
するＭＯＳｆｆｉ半導ｆｆ状回路装置に関し、＋
Ｎドープされた多結晶シリコンをゲート電極配線として
用い、電極配線のサイドに酸化膜をもうけたＬＤＤ構造
のＭＯＳ電界効果トランジスタを構成要素とするＭＯＥ
ｌ型半導体集積回路装置の製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a MOSffi semiconductor FF-shaped circuit device having a bMostt field effect transistor as a component, using +N-doped polycrystalline silicon as a gate electrode wiring, MOE whose component is an LDD structure MOS field effect transistor with an oxide film on the side of the electrode wiring.
The present invention relates to a method of manufacturing an l-type semiconductor integrated circuit device.
半導体集積回路装置は、高速化とコストダウンの要求か
ら、微細化及び高集積化が年々めざましく進んでいる。2. Description of the Related Art Semiconductor integrated circuit devices are becoming increasingly finer and more highly integrated year by year due to demands for higher speeds and lower costs.
特にＭＯＳ型半導体集積回路装置においては、目をみは
るものがある。Particularly in MOS type semiconductor integrated circuit devices, there are some remarkable things.
現在％最も多く量産されているＭＯＳ型半導体集積回路
装置は、チャンネル長３μｍの８μデザインルールのも
ので、チャンネル長２μ倶の２μデザインルールのＭＯ
Ｓ型半導体集積回路装置が最近になって量産され始めて
きている。２μルールの次に来るＭＯＳ型半導体集積回
路装置は１．２β〜１．５μルールのものと言われてお
り、種々の問題点をクリアーにして量産にのせようと５
日夜、技術開発が進められている。Currently, the most mass-produced MOS semiconductor integrated circuit devices are those with an 8μ design rule with a channel length of 3μm, and those with a 2μ design rule with a channel length of 2μm.
S-type semiconductor integrated circuit devices have recently begun to be mass-produced. It is said that the MOS type semiconductor integrated circuit device that comes after the 2μ rule will be based on the 1.2β to 1.5μ rule, and efforts are being made to overcome various problems and put it into mass production.
Technology development is progressing day and night.
種々の問題の中で、最も大きな問題として取り挙げられ
ている点は、短チャンネル化によって引き起こされるホ
ットエレクトロンによるｖｔｈ変蛎の問題である。現在
のＭＯ日電界効果トランジスタの構造で、ホットエレク
トロンによるｖｔｈ変動金考慮して、信頼性保証をして
いくとしたら、チャンネル長２μｍ程度が限度である。Among the various problems, the most important one is the problem of VTH variation due to hot electrons caused by the shortening of the channel. In the current MO field effect transistor structure, if reliability is to be guaranteed by taking into account vth fluctuations due to hot electrons, the channel length is limited to about 2 μm.
上記のホットエレクトロンの問題を考慮したトランジス
タ構造として注目をあつめ、検討が進められているもの
にＬＤＤ構造のトランジスタがある。A transistor with an LDD structure is attracting attention and being studied as a transistor structure that takes the above-mentioned hot electron problem into consideration.
従来のＬＤＤ構造のトランジスタについての形成方法と
問題点を第１〜夕図に例を示して説明する。The method of forming a conventional LDD structure transistor and its problems will be explained using examples shown in the first to second figures.
第１図に示すように、Ｐ型車結晶Ｂｉ基板１１上にフィ
ールド酸化膜２ｆｔ選択的に形成し、ゲート酸化膜８ｔ
−形成して、その上に多結晶シリコン層４ｔ−形成した
後、Ｎドープし配線状にホトエツチングをおζなう、さ
らに、１０１〜１０１１乙−程度の通常のソース・ドレ
イン拡散層のイオン打込みよりも低い濃度でリンのイオ
ン打込みをしてＮ拡散層５ｔ−形成し、ＣＶＤＢイｏ、
６を形成する。As shown in FIG. 1, a field oxide film of 2ft is selectively formed on a P-type wheel crystal Bi substrate 11, and a gate oxide film of 8t is selectively formed.
After forming a polycrystalline silicon layer 4t on top of the polycrystalline silicon layer 4t, dope it with N and photoetch it in the shape of a wiring.Furthermore, perform ion implantation of a normal source/drain diffusion layer of about 101 to 1011 By implanting phosphorus ions at a lower concentration than
form 6.
第２図に示すように、異方性のプラズマエツチングによ
ってＣＶＤ８ｚＯ，を全面エツチングすると多結晶シリ
コン層４のサイドの部分のＣｖＤｓｈｏ、膜が残り、サ
イドクールとなる。As shown in FIG. 2, when the entire CVD film is etched by anisotropic plasma etching, the CVD film remains on the sides of the polycrystalline silicon layer 4, forming a side cool.
ｇ８図に示すように％Ｎ拡散層５よりも濃い濃度で（１
０”〜１０”７ｃｍ” ） 、リンの打込みｅＬＮ拡１
散層７を形成する。As shown in figure g8, at a concentration higher than %N diffusion layer 5 (1
0”~10”7cm”), phosphorus implantation eLN expansion 1
A diffused layer 7 is formed.
第４図に示すように、ＣＶＤ’ＰＢＧ８を形成して、ア
ニール’ＴｈＬだ後コンタクトホールを形成しその後、
ＡＬ配線９を形成する。As shown in FIG. 4, after forming CVD'PBG8 and annealing 'ThL, contact holes are formed.
AL wiring 9 is formed.
以上の従来方法でＬＤＤ構造におけるサイドクールを形
成すると１次のような問題点が生じる。When forming a side coolant in an LDD structure using the conventional method described above, the following first-order problem occurs.
Ｃ”１Ｄ８ｉ０ｚ Ｍｔ５０００〜１００００Ａ８度形
成するが、ウェハー内の膜形成ラツキが５チル２０％発
生する。又、ウェハー間でも相当のバラツキが発生する
のと、ウェハーが大口径化すると、バラツキは大きくな
る。これを枚葉式のＲ工Ｅドライエツチャーでエツチン
グすると、エツチングバラツキも加味されて、部分的に
ｃｖＤｓ７ｏ。C"1D8i0z Mt5000~10000A8 degree is formed, but the film formation unevenness within the wafer occurs by 20% per 5 chill. Also, considerable variation occurs between wafers, and as the diameter of the wafer becomes larger, the variation becomes larger. When this is etched with a single-wafer type R-E dry etcher, the etching variation is also taken into account, resulting in a partial cvDs7o.
が残りてしまいトランジスタが形成されないとか、部分
的にはエツチングが早く進み、単結晶シリコン基板をエ
ツチングしてしまい、基板にダメージが入ってしまう。This may result in the transistor not being formed because etching remains, or the etching progresses quickly in some areas, etching the single-crystal silicon substrate and damaging the substrate.
本発明は上記のような問題を解決する所にあり、本発明
の目的は、ＣＶＤ５ｊ０２の膜厚のバラツキやエツチン
グのバラツキによって発生している、部分的に膜が残っ
てしまいトランジスタが形成さ−れなくなるという問題
と、部分的にエツチングが早く進み基板をエツチング及
びダメージを与えるという問題を解決する所にある。The purpose of the present invention is to solve the above-mentioned problems, and an object of the present invention is to prevent the formation of transistors due to partial film remaining due to variations in the film thickness of CVD5J02 and variations in etching. This method solves the problems of the substrate being etched and damaged, and the etching progressing too quickly in some areas.
問題点を解決する手段は、バラツキの多いＣＶＤＥｉ７
０．やＲ工Ｅのエツチング方を用いないで、Ｎドープさ
れた多結晶シリコン配線のサイドを選択酸化する事によ
って、サイドツールを形成する方法である。The solution to the problem is CVDEi7, which has many variations.
0. In this method, a side tool is formed by selectively oxidizing the side of an N-doped polycrystalline silicon interconnection without using the etching method of R or E.
第５図に示すように％Ｆｌｕ単結晶シリコン基板ｌｌ上
にフィールド酸化膜１２ｔ−選択的に形成し、ゲート酸
化Ｊ［１３を形成して、その上に多結晶シリコン層１４
を形成した後、Ｎド、−プして、その上にＢ（３Ｎ４膜
１５を形成する。As shown in FIG. 5, a field oxide film 12t is selectively formed on a %Flu single crystal silicon substrate 11, a gate oxide film 13 is formed, and a polycrystalline silicon layer 14 is formed thereon.
After forming, N-doping is performed, and a B (3N4 film 15) is formed thereon.
第６図に示すように、ホトエツチングにより、ｓｚ３ｍ
４膜と多結晶シリコン層をエツチング除去する。As shown in Figure 6, by photoetching, sz3m
4 film and the polycrystalline silicon layer are removed by etching.
さらに、１０ ” ”−１１１ｌｓ／♂程度の低い濃度
のリンをイオン打込みしてＮ拡散７ａ’１６を形成する
。Further, phosphorus is ion-implanted at a low concentration of about 10''-111ls/♂ to form the N diffusion 7a'16.
第７図に示すようにｓ ＳＳ３”４膜をマスクに、９５
０℃以下の低温でウェット酸化すると、低い濃度のＮ拡
散＃１６上よりもＮドープした多結晶シリコン層の方が
酸化レートが格段に早いので、選択的に多結晶シリコン
配線のサイドに厚い酸化膜が形成される。その上から、
？拡散／ｆＪ１６よりも汲い濃度で（１０” ＝ＩＯ”
／ ｃｍ ” ） 、リンの打込みをし＋
Ｎ拡散層を形成する。As shown in Figure 7, using the SS3''4 film as a mask, 95
When wet oxidized at a low temperature below 0°C, the oxidation rate is much faster on the N-doped polycrystalline silicon layer than on the low-concentration N-diffused #16 layer, so thick oxidation is selectively applied to the side of the polycrystalline silicon wiring. A film is formed. From above,
? Diffusion/fJ16 with pumping concentration (10" = IO"
/cm''), and phosphorus is implanted to form a +N diffusion layer.
第８図に示すように、Ｓ＄３”４膜をエツチング除去し
た後、ＣＶＤＰＳＧ１９ｆ：形成し了ニールをした後コ
ンタクトホールを形成して、そのｋ ％ ＡＬ配線加を
形成する。As shown in FIG. 8, after the S$3''4 film is removed by etching, CVDPSG 19f is formed and annealed, a contact hole is formed, and its k% AL wiring is formed.
以上のような１本発明の方法を用いると、従来問題とな
っていたＣＶＤＢ１０．の膜厚のバラツキやエツチング
のバラツキによって発生していた。When the method of the present invention as described above is used, the conventional problem of CVDB10. This was caused by variations in film thickness and etching.
部分的に膜が残ってしまいトランジスタが形成されなく
なるという問題や、部分的にエツチングが早く進み基板
をエツチング及び基板にダメージを与えるという問題が
なくなり、量産に適したプロセスとなる。又、サイドツ
ールの酸化膜を熱酸化で形成するため、信頼性も高くな
る。This process is suitable for mass production because it eliminates the problem of parts of the film remaining and transistors not being formed, and the problem of parts of the film being etched too quickly and causing damage to the substrate. Furthermore, since the oxide film of the side tool is formed by thermal oxidation, reliability is also increased.
又、本発明′の例では、イオン打込みのイオン種に、リ
ンを用いた例を示したが、このかぎりではなく、砒素等
を用いても良く、併用してもなんらさしつかえない。Furthermore, in the example of the present invention, phosphorus is used as the ion species for ion implantation, but this is not the only option; arsenic or the like may also be used, and there is no harm in using them in combination.
又、本発明の例では１Ｍチャンネル形のＭＯＳＩＣの例
を示したが、相補型のＭＯＳＩＣでも同様である。Further, in the example of the present invention, a 1M channel type MOSIC is shown as an example, but the same applies to a complementary type MOSIC.
第１図〜第４図は、従来方法による製造工程順の断面構
造図である。
第５図〜第８図は、本発明の方法による製造工程順の断
面構造図である。
以 上FIGS. 1 to 4 are cross-sectional structural diagrams in the order of manufacturing steps according to a conventional method. FIG. 5 to FIG. 8 are cross-sectional structural views showing the order of manufacturing steps according to the method of the present invention. that's all
Claims (2)
配線として用い、該電極配線のサイドに酸化膜を形成し
てＬＤＤ構造（ライト、ドープド、ドレイン構造の略、
以後ＬＤＤ構造と略す。）をとるＭＯＳ電界効果トラン
ジスタを構成要素とするＭＯＳ型半導体集積回路装置の
製造方法において、Ｎ＾＋ドープされた該多結晶シリコ
ンを形成した後、Ｓｉ＿３Ｎ＿４膜を形成し、ホトエッ
チにより配線状に該Ｓｉ＿３Ｎ＿４膜、該多結晶シリコ
ンをエッチング形成した後、イオン打込みにより低濃度
で、ソース、ドレイン等の拡散層を形成して、該Ｓｉ＿
３Ｎ＿４膜をマスクに９５０℃以下の低温でウェット酸
化をして、該ゲート電極配線のサイドに該酸化膜を選択
的に形成し、イオン打込みにより高濃度でソース、ドレ
イン等の拡散層を形成して、ＬＤＤ構造のＭＯＳ型電界
効果トランジスタを形成した事を特徴とするＭＯＳ型半
導体集積回路装置の製造方法。(1) N^+ doped polycrystalline silicon is used as the gate electrode wiring, and an oxide film is formed on the side of the electrode wiring to create an LDD structure (abbreviation for light, doped, drain structure).
Hereinafter, it will be abbreviated as LDD structure. ), in which the N^+ doped polycrystalline silicon is formed, a Si_3N_4 film is formed, and a wiring pattern is formed by photoetching. After forming the Si_3N_4 film and the polycrystalline silicon by etching, diffused layers such as sources and drains are formed at low concentration by ion implantation, and the Si_3N_4 film is formed by etching the polycrystalline silicon.
Using the 3N_4 film as a mask, perform wet oxidation at a low temperature of 950°C or lower to selectively form the oxide film on the side of the gate electrode wiring, and form high concentration diffusion layers such as source and drain by ion implantation. A method for manufacturing a MOS semiconductor integrated circuit device, characterized in that a MOS field effect transistor having an LDD structure is formed.
化膜をもうけた事を特徴とする特許請求の範囲第１項記
載のＭＯＳ型半導体集積回路装置の製造方法。(2) A method for manufacturing a MOS type semiconductor integrated circuit device according to claim 1, characterized in that an oxide film is provided between the polycrystalline silicon and the Si_3N_4 film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26393284A JPS61141183A (en) | 1984-12-14 | 1984-12-14 | Manufacture of mos semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26393284A JPS61141183A (en) | 1984-12-14 | 1984-12-14 | Manufacture of mos semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61141183A true JPS61141183A (en) | 1986-06-28 |
Family
ID=17396262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26393284A Pending JPS61141183A (en) | 1984-12-14 | 1984-12-14 | Manufacture of mos semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61141183A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02134256A (en) * | 1988-11-16 | 1990-05-23 | Casio Comput Co Ltd | Thermal head and manufacture thereof |
-
1984
- 1984-12-14 JP JP26393284A patent/JPS61141183A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02134256A (en) * | 1988-11-16 | 1990-05-23 | Casio Comput Co Ltd | Thermal head and manufacture thereof |
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