JPH03108727A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease manufacturing steps, to decrease effects on a substrate and to obtain stabilized transistor characteristics by forming opening parts in both sides of a gate electrode on a semiconductor substrate by utilizing a peripheral etching method, and forming a low-concentration impurity region by a slant-rotation ion implanting method. CONSTITUTION:An opening 16A is formed in the vicinity of a gate electrode 16 by using a peripheral etching method. Impurities are implanted into the opening 16A by using a slant rotation ion implanting method, and a low- concentration impurity region 17 is formed. Then, impurities are implanted by an ion implanting method with said gate electrode 16 as a mask, and a high-concentration impurity region 19 is formed. Furthermore, impurities are implanted by the slant-rotation ion implanting method, and a high-concentration impurity region 21 is formed. For example, resist 15 is formed on a molybdenum silicide film 14. Then the molybdenum silicide film 14 around the resist 15 and a silicon substrate 11 are selectively etched by using the peripheral etching method which is a reactive ion etching method with chlorine gas and oxygen gas as etchant.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device that enables MO8 field effect transistors to be manufactured with excellent reliability and high yield.

(Conventional technology) Conventional LDD (Lightly Doped D
raim) structure transistor, for example, I
EDM83, pages 392-395.

FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing an LDD structure transistor.

First, as shown in FIG. 2(a), a thick field oxide film 2 is selectively formed on the surface of a silicon substrate 1 by the LOCO8 method to perform element isolation.

Next, a thin gate oxide film 3 to serve as a gate insulating film is formed, and polysilicon 4 for forming a gate electrode is formed on the entire surface, and phosphorus is doped using PoCl3 as a diffusion source to impart conductivity.

Next, gate photolithography and anisotropic etching are performed to form the gate electrode 4.

Next, using this gate electrode 4 as a mask, phosphorus P is ion-implanted to form a shallow (N layer) low concentration impurity region 5 (N layer) in the entire source/drain formation region of the silicon substrate 1.

Next, as shown in Figure 2 (bl), 5I was prepared by CVD method.
The O2 film 6 is grown, and then, as shown in FIG. 2(c), the entire surface is etched using RIE (reactive ion etching) to form sidewalls 7 on the side walls of the gate electrode 4.

Next, by ion-implanting arsenic (As) using the side wheels 7 and the gate electrode 4 as a mask, a high concentration impurity region (N+ layer) is formed in a portion of the source/drain forming region away from the gate electrode 4. Form 8 deeply.

Note that although only the formation of an N-channel transistor has been described here, an IC with a 6MO8 structure (integration port 1i
＠), it is necessary to cover the P-channel transistor portion with a resist using photolithography technology when performing ion implantation to form the N− layer and the N+ layer.

(Problem to be Solved by the Invention) However, in the above transistor manufacturing method, in order to form the sidewall 7, CVD is applied to the entire surface of the evaporator.
A 5102 film 6 is grown by the method and etched.

Therefore, the number of process steps is increased by two, resulting in an increase in manufacturing cost and a decrease in yield.

Furthermore, during etching for forming the sidewalls 7, it is difficult to detect the end point, leaving etching residues, and conversely, the field oxide film 2 and the silicon substrate 1 are etched, which has a large effect on the underlying layer.

This causes problems such as leakage current and deterioration of device characteristics. Etching damage during etching for forming the sidewalls 7 causes breakdown voltage failure of the gate oxide film 3, resulting in a decrease in yield and
This led to deterioration of device characteristics.

Furthermore, the dimensions of the sidewall 7 are unstable due to variations in the thickness of the 5IO2 film 6 as well as variations due to etching, resulting in variations in transistor characteristics, deterioration of device characteristics, and reliability. The situation was not good.

This invention solves the problems of the above-mentioned prior art.
The present invention provides a method for manufacturing a semiconductor device that solves the problems of increasing the number of process steps in sidewall formation, affecting the underlying layer, and lowering reliability and yield due to instability of transistor causticity.

(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device in which openings are formed in a semiconductor substrate on both sides of a gate electrode diagonally using a peripheral etching method in which only the periphery of a resist pattern is etched. This method introduces a step of forming a low concentration impurity region by a rotational ion implantation method and a step of forming a high concentration impurity region using the gate electrode as a mask.

(Function) The present invention introduces the above-described steps into a method of manufacturing a semiconductor device, so that openings are formed by selectively etching the semiconductor substrate on both sides of the gate electrode using a peripheral etching method. Impurities are implanted into this opening by an oblique rotational ion implantation method to form a low concentration impurity region in the opening of the semiconductor substrate, thereby eliminating the need for a full-surface etching process. Further, by performing ion etching using the Day 1 electrode as a mask, a high concentration impurity region is formed. This reduces variations in the source-drain distance. Therefore, the above problem can be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. FIG. 1(al) to FIG. 1(dl) are process cross-sectional views of one embodiment.

First, as shown in Figure 1 (,1), a P-type silicon substrate (
100) Form N L layers on 11], IA, and L
After selectively growing a thick field oxide film 12 by the OCOS method, a gate oxide film 13 is formed by 350 layers and a molybdenum silicide film 14 is formed by 3000 layers.

In place of this molybdenum silicide film 14, in the present invention, any material can be used, such as molybdenum or molybdenum polycide, as long as it can be subjected to ferrule etching.

Next, a resist is applied and patterned using photolithography to obtain a resist 15.

Next, as shown in FIG. 1 (bl), the patterned resist 1 is
The molybdenum silicide film 14 and the P-type silicon substrate 11 around the gate electrode 5 are selectively etched to form an opening 16A around the gate electrode 16.

In addition, the Peel ferrule etching method is a method in which chlorine gas is
Must be in the 70% range. Moreover, it is a preferable method to use for materials containing molybdenum.

Next, using the resist 15 and the molybdenum silicide film 14 as a mask, the "P" 30
KeV 5E131ons/cITr with aperture 16A P
A low concentration impurity region (N- layer) 17 is formed by implanting into the surface of the silicon substrate 11.

Next, etching is performed again using the reactive ion etching method used earlier, which uses chlorine gas and oxygen gas as etchants.

As a result, as shown in FIG. 1(C), the resist 15
The portions of the molybdenum silicide film 14 not covered by etching can be etched, and then the resist 15 is removed.

Next, using photolithography technology, the P-channel transistor formation region is covered with a resist 18, and then, using the resist 18 and gate electrode 16 as a mask, As 50KeV8 E 151ons/
cIIr is vertically implanted to form a high concentration impurity region (N+
Form layer 19.

Next, as shown in FIG. 1 (fd), after removing the resist 18, in the same manner as before, the N-channel transistor formation region was covered with a resist 20, and the "B+50KeV4E15ons/ +f
fl is implanted to form a high concentration impurity region (P+ layer) 21.

In addition, 11B+50Ke
VIE141ons/c++r is implanted to form a P-type low concentration impurity region. After that, by normal ion implantation method, "B" 50 KeV 4E151 ons/
By vertically implanting cnr to form a high concentration impurity region, a P-type LDD structure transistor, that is, a transistor with P- around the lower gate and 1 outside thereof can be formed.

(Effects of the Invention) As described in detail above, according to the invention of B, an opening is formed in the semiconductor substrate around the gate electrode using the ferrule etching method without forming a sidewall, and After the low concentration impurity region is formed by the rotational ion implantation method, the high concentration impurity region is formed using the gate electrode as a mask, so the number of manufacturing steps can be reduced by one compared to the sidewall process.

Furthermore, since there is no full-surface etching step that is performed when forming the sidewalls, there is little effect on the underlying layer, such as the field oxide film or the semiconductor substrate.

Furthermore, in order to perform ion implantation to form an N+ layer using the gate electrode as a mask, the north of the N+ layer is implanted.

Variations in the distance between drains are small, and stable transistor characteristics can be obtained.

[Brief explanation of drawings]

1(a) to 1fb) are process cross-sectional views of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. It is a process cross-sectional view of the method. 11...P-type silicon substrate, 13... Gate oxide film,
14... Molybdenum silicide film, 16... Gate electrode, 16A... Opening, 17... Low concentration impurity region, 19.21... High concentration impurity region. Procedural amendment (method) Indication of the case Japanese Patent Application No. 96250 2゜Name of the invention Method for manufacturing semiconductor devices 3゜Relationship with the case by the person making the amendment

Claims (1)

[Claims] (a) A step of forming an opening around the gate electrode using a peripheral etching method and implanting impurities into this opening using an oblique rotational ion implantation method to form a low concentration impurity region. (b) implanting impurities by ion implantation using the gate electrode as a mask to form a high concentration impurity region; (c) implanting impurities by oblique rotational ion implantation;
A method of manufacturing a semiconductor device, comprising: a step of forming a high concentration impurity region;