JPS6097660A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6097660A JPS6097660A JP20551683A JP20551683A JPS6097660A JP S6097660 A JPS6097660 A JP S6097660A JP 20551683 A JP20551683 A JP 20551683A JP 20551683 A JP20551683 A JP 20551683A JP S6097660 A JPS6097660 A JP S6097660A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistor
- region
- base
- resistor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device.
第１図は、抵抗層１，２を有する抵抗層付トランジスタ
３の回路図を示でいる。このような回路は、インバータ
ー、インターフェイス、ドライバーバー等の回路に適用
されている。而して、このような抵抗層付トランジスタ
を有する半導体装置の断面は例えば第２図に示すとうり
であり、その平面図は第３図に示すとうりである。図中
４は、Ｎ形シリコン基板である。シリコン基板４上に【
ま、エピタキシャル層５が形成されている。エピタキシ
ャル層５の所定領域には、ベース領域６が形成され、こ
のベース領域θ内には、所定の拡散深さでエミッタ領域
７が形成されて０る。また、ベース流域６には、これを
貫通する拡散深さでベースコンタクト領域８が形成され
ている。これらの不純物領域６，７．８を含むエピタキ
シャル層５上には、酸化膜９が形成されている。酸化膜
９上には、所定パターンの抵抗層１０が形成されて（Ｘ
る。FIG. 1 shows a circuit diagram of a resistive layer transistor 3 having resistive layers 1 and 2. As shown in FIG. Such circuits are applied to circuits such as inverters, interfaces, and driver bars. The cross section of a semiconductor device having such a transistor with a resistive layer is as shown in FIG. 2, for example, and the plan view thereof is as shown in FIG. 3. 4 in the figure is an N-type silicon substrate. On the silicon substrate 4 [
Well, an epitaxial layer 5 is formed. A base region 6 is formed in a predetermined region of the epitaxial layer 5, and an emitter region 7 is formed within the base region θ with a predetermined diffusion depth. Further, a base contact region 8 is formed in the base region 6 with a diffusion depth penetrating it. An oxide film 9 is formed on the epitaxial layer 5 including these impurity regions 6, 7.8. A resistive layer 10 having a predetermined pattern is formed on the oxide film 9 (X
Ru.
酸化ｌ！９には、エミッタ領域７およびベースコンタク
ト領域８に通じるコンタクトホール１２が形成されてい
る。酸化膜９上には、コンタクトホール１２を介してエ
ミッタ領域７、ベースコンタクト領域８に夫々接続する
と共に抵抗層１０に接続する電極１３．１４が形成され
ている。なお、同図中１５は、ベースパッド電極である
。Oxidation! A contact hole 12 communicating with emitter region 7 and base contact region 8 is formed in 9 . Electrodes 13 and 14 are formed on the oxide film 9 and are connected to the emitter region 7 and the base contact region 8 through the contact hole 12, respectively, and to the resistance layer 10. Note that 15 in the figure is a base pad electrode.
而して、このように構成された半導体装置も微細化する
ことが望まれている。このため抵抗層１０のパターンを
縮小する必要がある。そうすると抵抗層１０の長さしを
長くとれない分だけ、抵抗層１０の幅を狭くしなければ
ならい。しかしながら、抵抗層１０の電流容量には限界
があるため抵抗層１０の幅はある程度より狭くできない
。その結果、それ以上に抵抗層１０の抵抗値を高めるに
は、抵抗層１０のシート抵抗Ｒ８を大きくしなければな
らない。しかしながら、素子の中で局部的に小さな抵抗
値の抵抗層１０を必要とする場合には、第４図に示す如
く、抵抗層１０の長さしを、その両端部からエミッタ電
極１３、およびベースパッド電極１５となる金属層を延
出して著しく短くしなければならない。その結果、これ
らの電極１３．１′５をパターニングる際にサイドエッ
チやオーバーエッチ等の現象が起き、所定の値を有する
抵抗層１２を得ることができず、歩留を著しく低下する
問題があった。Therefore, it is desired that semiconductor devices configured in this manner be also miniaturized. Therefore, it is necessary to reduce the size of the pattern of the resistance layer 10. In this case, since the length of the resistance layer 10 cannot be increased, the width of the resistance layer 10 must be made narrower. However, since there is a limit to the current capacity of the resistive layer 10, the width of the resistive layer 10 cannot be narrower than a certain level. As a result, in order to further increase the resistance value of the resistance layer 10, the sheet resistance R8 of the resistance layer 10 must be increased. However, if a resistance layer 10 with a locally small resistance value is required in the element, the length of the resistance layer 10 is extended from both ends to the emitter electrode 13 and the base, as shown in FIG. The metal layer that will become the pad electrode 15 must be extended and significantly shortened. As a result, phenomena such as side etching and overetching occur when patterning these electrodes 13.1'5, making it impossible to obtain the resistance layer 12 having a predetermined value, resulting in a problem of significantly lowering the yield. there were.
本発明は、所定の小さい値の抵抗値を有する抵抗層を備
えて集積度の向上を達成した半導体装置を提供すること
をその目的とするものである。An object of the present invention is to provide a semiconductor device that is equipped with a resistance layer having a predetermined small resistance value and that achieves an improved degree of integration.
本発明は、素子に接続された抵抗層の近傍に第２抵抗層
を設けたことにより、集積度の向上を達成した半導体装
置である。The present invention is a semiconductor device that achieves an improved degree of integration by providing a second resistance layer near a resistance layer connected to an element.
第５図は、本発明の一実施例の平面図である。 FIG. 5 is a plan view of one embodiment of the present invention.
図中２０は、ベース領域２１を形成した半導体基板であ
る。ベース領域２１には、所“定の拡散深さでエミッタ
領域２２が形成されている。ベース領域２１およびエミ
ッタ領域２２を含む半導体基板２０の表面には、厚さ約
１μｍの酸化膜２３が形成されている。酸化膜２３上に
は、一端部がベース領域２１等で構成された制子に近接
した多結晶シリコンからな４抵抗層２４が略蛇行状に形
成されている。抵抗層２４は、厚つき約３０００乃至５
０００人に設定され、シート抵抗（Ｒｓ）が約１０００
％に設定されている。このシート抵抗Ｒ８の設定は、抵
抗層２４中に例えばボロンイオンを照射条件が加速電圧
４０乃至５ Ｑ、 Ｋ ｅ Ｖ、ドーズ量６乃至８×１
０ｃｆ／Ｌで注入することにより行なわれている。なお
、熱処理は、９００℃の温度で約一時間行なわれている
。また、抵抗層２４のパターニングは、例えばプラズマ
エツチング法により行なわれている。蛇行状の抵抗層２
４の近傍には・、略直線状に第２抵抗層２５が形成され
てト）る。第２抵抗層２５の材質およびシート抵抗の値
は、抵抗層２４と同様に設定されている。また、ベース
領域２１には、ベースコンタクト領域２７が形成さてい
る。20 in the figure is a semiconductor substrate on which a base region 21 is formed. An emitter region 22 is formed in the base region 21 with a predetermined diffusion depth. An oxide film 23 with a thickness of about 1 μm is formed on the surface of the semiconductor substrate 20 including the base region 21 and the emitter region 22. On the oxide film 23, four resistance layers 24 made of polycrystalline silicon are formed in a substantially meandering shape, one end of which is close to a resistor formed of the base region 21 and the like. , about 3000 to 5 thick
000, and the sheet resistance (Rs) is approximately 1000.
It is set to %. The setting of this sheet resistance R8 is such that boron ions are irradiated into the resistance layer 24 under the following conditions: acceleration voltage of 40 to 5 Q, K e V, and dose of 6 to 8×1.
This is done by injecting at 0 cf/L. Note that the heat treatment was performed at a temperature of 900° C. for about one hour. Further, the patterning of the resistance layer 24 is performed by, for example, a plasma etching method. Meandering resistance layer 2
A second resistance layer 25 is formed in the vicinity of point 4 in a substantially straight line. The material and sheet resistance value of the second resistance layer 25 are set similarly to those of the resistance layer 24. Furthermore, a base contact region 27 is formed in the base region 21 .
このように構成された半導体装置３０によれば、第６図
に示す如く、酸化膜２３にエミッタ領域２２およびベー
スコンタクト領域２７に接続するコンタクトホールを開
口した後ち、抵抗層２４および第２抵抗層２５を含む酸
化膜上に例えばアルミニュウムを所定の厚さで堆積する
。次いで、このアルミニュム層に、抵抗層２４および第
２抵抗層２５の所定領域が露出すると共に、エミツータ
領滅２２上には、抵抗層２４および第２抵抗層２５に接
続するエミッタ電極３１が形成され、ベースコンタクト
領域２７上には抵抗層２４に接続し、かつ、抵抗層２４
および第２抵抗層２５０所定領域を覆う接続配線層３２
が形成され、また、抵抗層２４および第２抵抗層２５の
他端部上にベースパッド電極３３を残存するようにパタ
ーニングを施すことができる。つまり、この半導体装置
３０によれば、抵抗層２４と第２抵抗層２５が並設され
ているので、ベースパッド電極３３および接続配線層３
１、エミッタ電極３１の形状を大きくしてエツチング処
理を容易にし、高い精度でパターニングを施すことがで
きる。その結果、サイドエツチング、オーバーエツチン
グの発生を阻止して集積度の向上を達成した半導体装置
を容易に得ることができる。According to the semiconductor device 30 configured in this manner, as shown in FIG. For example, aluminum is deposited to a predetermined thickness on the oxide film including the layer 25. Next, predetermined regions of the resistance layer 24 and the second resistance layer 25 are exposed to this aluminum layer, and an emitter electrode 31 connected to the resistance layer 24 and the second resistance layer 25 is formed on the emitter region 22. , connected to the resistance layer 24 on the base contact region 27, and connected to the resistance layer 24.
and a connection wiring layer 32 covering a predetermined area of the second resistance layer 250.
is formed, and patterning can be performed so that the base pad electrode 33 remains on the other ends of the resistance layer 24 and the second resistance layer 25. That is, according to this semiconductor device 30, since the resistance layer 24 and the second resistance layer 25 are arranged in parallel, the base pad electrode 33 and the connection wiring layer 3
1. The shape of the emitter electrode 31 is enlarged to facilitate the etching process and patterning can be performed with high precision. As a result, it is possible to easily obtain a semiconductor device in which the occurrence of side etching and overetching is prevented and the degree of integration is improved.
以上説明した如く、本発明に係る半導体装置によれば、
所定の小さい抵抗値を有する抵抗層を高い形状精度で形
成して集積度の向上を達成できるものである。As explained above, according to the semiconductor device according to the present invention,
It is possible to improve the degree of integration by forming a resistive layer having a predetermined small resistance value with high shape accuracy.
第１図は、抵抗層付トランジスタの回路図、第２図は、
同回路を有する従′来の半導体装置の断面図、第３図は
、同半導体装置の平面図、第４図は、同半導体装置に抵
抗値の小さい抵抗層を形成した状態を示す平面図、第５
図は、本発明の一実施例の半導体装置の平面図、第６図
は、同半導体装置に抵抗値の小さい抵抗層を形成した状
態を示す平面図でうる。
２０・・・半導体基板、２１・・・ベース領域、２２・
・・エミッタ領域、２３・・・配化膜、２４・・・抵抗
層、２５・・・第２抵抗層、２７・・・ベースコンタク
ト領域、３０・・・半導体装置、３１・・・エミッタ電
極、３２・・・接続配線層、３３・・・ベースパッド電
極。
出願人代理人 弁理士 鈴江武彦
第１問
第４図
ＷＳ図
０Fig. 1 is a circuit diagram of a transistor with a resistive layer, and Fig. 2 is a circuit diagram of a transistor with a resistive layer.
3 is a sectional view of a conventional semiconductor device having the same circuit, FIG. 3 is a plan view of the same semiconductor device, and FIG. 4 is a plan view showing a state in which a resistance layer with a small resistance value is formed in the same semiconductor device. Fifth
The figure is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 6 is a plan view showing a state in which a resistance layer with a small resistance value is formed on the semiconductor device. 20... Semiconductor substrate, 21... Base region, 22...
... Emitter region, 23... Arrangement film, 24... Resistance layer, 25... Second resistance layer, 27... Base contact region, 30... Semiconductor device, 31... Emitter electrode , 32... connection wiring layer, 33... base pad electrode. Applicant Representative Patent Attorney Takehiko Suzue Question 1 Figure 4 WS Figure 0
Claims (1)
素子に直列に接続する占うに前記半導体基板上に形成さ
れた抵抗層と、該抵抗層の近傍にこれと所定間隔で並設
された第２抵抗層とを具備することを特徴とする半導体
装置。A plurality of elements formed in a predetermined region of a semiconductor substrate, a resistor layer formed on the semiconductor substrate connected in series to the elements, and a resistor layer arranged in parallel with the resistor layer at a predetermined interval in the vicinity of the resistor layer. A semiconductor device comprising a second resistance layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20551683A JPS6097660A (en) | 1983-11-01 | 1983-11-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20551683A JPS6097660A (en) | 1983-11-01 | 1983-11-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6097660A true JPS6097660A (en) | 1985-05-31 |
| JPH0557740B2 JPH0557740B2 (en) | 1993-08-24 |
Family
ID=16508162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20551683A Granted JPS6097660A (en) | 1983-11-01 | 1983-11-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6097660A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62181470A (en) * | 1986-02-05 | 1987-08-08 | Toshiba Corp | Transistor with built-in resistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5046272A (en) * | 1973-08-29 | 1975-04-24 | ||
| JPS51151572U (en) * | 1975-05-27 | 1976-12-03 | ||
| JPS5772364A (en) * | 1980-10-24 | 1982-05-06 | Matsushita Electric Ind Co Ltd | Integrated circuit |
-
1983
- 1983-11-01 JP JP20551683A patent/JPS6097660A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5046272A (en) * | 1973-08-29 | 1975-04-24 | ||
| JPS51151572U (en) * | 1975-05-27 | 1976-12-03 | ||
| JPS5772364A (en) * | 1980-10-24 | 1982-05-06 | Matsushita Electric Ind Co Ltd | Integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62181470A (en) * | 1986-02-05 | 1987-08-08 | Toshiba Corp | Transistor with built-in resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0557740B2 (en) | 1993-08-24 |
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