JPS5944861A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to form a thick field insulation film on a p type semiconductor region by selective oxidation by a method wherein the p type semiconductor region is formed in an n type semiconductor substrate, and an n type resistance element is formed in the region. CONSTITUTION:An oxide film 22 of a fixed thickness is formed over the entire surface of the n type semiconductor substrate 21. Next, the p type region 23 is provided at the fixed region of the substrate 21 by means of p type impurity. Further n type impurity is implanted into the p type region 23, resulting the resistance element 24 composed of an n type semiconductor. On the other hand, an oxidation resistant protection film composed of an Si nitride film is formed on the oxide film at the desired region of the substrate 21, and, with the film as the mask, thick oxide films acting as the field insulation films 28 are selectively formed. Thereafter, th base 25, and the emitter 26, and Al wirings 27 are formed at the desired region. As the result, a semiconductor device having no restrictions in wiring and characteristic variation and with less stepwise difference can be obtained.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention particularly relates to a high voltage integrated circuit, and relates to a semiconductor device in which an N-type resistance element is provided in a P-wall region under a field insulation layer, and a semiconductor device thereof. This relates to a manufacturing method.

(b) Conventional technology and problems A cross-sectional structure of the main parts of a conventional high-voltage integrated circuit is not shown in FIG.

In the figure, 1 is an N-type semiconductor 6 (temporary, 2 is a base, 3 is a
is an emitter, 4 is a P-type resistance element (I) + layer), 5 is an oxide film, 6 is PSG 11%, and 7 is an At wiring.

As is clear from the figure, in the high breakdown voltage integrated 1JIL circuit, the PSG film 6 is stacked on top of the field oxide film 5 to form a thick field insulation IIA, and the TF'7 structure is used to provide the field play 1 effect. was commonly used.

However, in the above-mentioned structure, there is a risk of disconnection of the At wiring 70 due to the step difference in the thick field insulating film, and the phenomenon in which charge accumulates at the interface between the oxide film 5 and the P S G lj Mj 6 may affect the characteristics of the semiconductor element. There is a problem that the value fluctuates. In order to solve this problem,
7. As shown in the figure. c structure is possible. In the figure, 11 is an N-type semiconductor substrate, 12 is a vane, 13 is a boron emitter, 1
4 is a P-type resistance element (r'' layer), 15 is an oxidized 11 starch 15'
is the oxide film 15 [X silicon nitride film (3) formed on the N-type semiconductor substrate 11;
An oxidation-resistant f1 preservation film (not shown) such as i N If a thick oxide film is formed on the tentative layer 11 (2) and the oxide film is used as the field insulating film J6, the field isolation NIIQ
16 is generated in the 1R conductor 1 substrate 11 by about 50%, making it possible to form a flat semiconductor substrate surface with fewer steps than the 4'B structure (not shown in FIG. 1). Only Llt
However, the disadvantage of this method is that it is difficult to form a thick field insulating film on the P-type resistor layer 14. In other words, the resistance element J4 made of a P-type impurity such as boron has a high resistance value because the P-type impurity precipitates in the oxidation layer 1, and the formation of the P-type & resistance element 14 having a predetermined resistance value becomes difficult. Very far away. Therefore, in order to prevent a drop in breakdown voltage due to the color tube of the At wiring, there is a problem that must be taken into consideration in the design so that At(j(3@Sho 17) does not cross over the pattern of the P-type resistor system 14.

(c) Purpose of the Invention The present invention solves the above-mentioned problems.
．． - Provides an unrestricted semiconductor device and its manufacturing method.

(()) Structure of the Invention That is, the present invention includes the steps of forming a P-type conductor region on an N-type semiconductor substrate, forming a resistance element made of a conductor layer in the P-type semiconductor region, and then By forming a field insulating film similar to that on the collector region 110 in the P-type half-body region including the N-type resistance region, a field insulating film similar to the field insulating film on the collector region is formed. It is characterized by having a structure including a bow 1 in which an N-type resistance element is housed in a P-type region.

(e) Embodiment of the Invention An embodiment of the invention will be described in detail below with reference to the drawings. FIG. 53 is an essential part 1ti (i-plane view) of a semiconductor device according to an embodiment of the present invention. A P-type region (P-well) 23 is provided using a P-type impurity such as 210 predetermined region Kl+1ill element, and an N-type impurity such as scale or 7 element is implanted into the P-type region 23. Resistance element 2 made of N-type semiconductor (N0 layers)
4 is formed on the desired region of the semiconductor substrate 2] by forming an oxidation-resistant protective film (not shown) made of silicon nitride (SiN). After selectively forming a thick oxide (11) as a mask, the desired area (25.
forming an emitter 26; the base 25 and the emitter 26;
A connection window is provided in the connection window, and the At wiring 2'7 is formed through the connection window. The above-mentioned JV oxide film is field insulation + insulation 2.
'3, but the phosphorus impurity of the N-type resistance element 24 provided in the P-well 2; (5 in2 Since it does not segregate in the film, there is almost no variation in the itt resistance value, and N 4t,g has the desired resistance value.
Formation of a resistive element 24 is possible.

By creating such an i/, it is possible to prevent characteristic fluctuations due to charges at the interface of the evaporated film, and to manufacture highly reliable semiconductor devices with few steps and no disconnections, and (1)
It is possible to eliminate the wiring constraints described in I.

FIGS. 4 to 6 are cross-sectional views of main steps showing an embodiment of the monument and straightening method of the present invention. Also, are the parts of your diagram and the times etc. the same? ,■shi・is 11 times. fr (an N-type semiconductor in FIG. 4), (an oxide film 22 of about 400 (l) is formed on the plate 21 by normal thermal heating, and the oxide film 22 is
A silicon nitride film (Si
N) Pattern 3] is formed, a resist film 32 is applied over the entire surface of the semiconductor substrate 21 including the SiN film 31ζ, and a window for forming a P-type region is formed by patterning a desired shape. Next, using the resist 1lj (32) as a mask, boron impurity ions are implanted into the semiconductor J, l: board 21.
) After forming the mold region 23, the resist film 32 is removed.

Next, as shown in FIG. 5, a P-type region 23 (P-well) of a predetermined depth is formed by a predetermined heat treatment (annealing), and then a resist film 33 is applied over the entire surface and patterned. Using the resist film 33 as a mask, phosphorus impurity is injected into the N-type resistor element-2.
4, the resist film 3 is removed. Then, as shown in FIG.
Using %%:31 as a mask, it is selectively converted to β by, for example, a high-pressure oxidation method, and P-Wale 2 is formed as shown in the figure.
Approximately 25-31im on 3 O) Thick field insulation +1
! , after forming '42B, 1) JL St N 11
5′! :31 is removed. N-type resistor f-sae is 1!1
1 As mentioned above, in this step, impurities are oxidized 11
It is possible to form a resistive element with a predetermined value without segregation in 4 ml 8. Then, in a normal process, 1 is St I'12 II! If a base and an emitter are formed in a predetermined area separated by 31, a connection window is provided to connect to the base and the emitter, and a wiring is formed through the connection window, the present invention can be realized as shown in FIG. A semiconductor device having a +ti structure is manufactured.

(f) Effects of the Invention - As explained, according to the present invention, a P-type semiconductor region (P-ware 1/) is formed in an N-type semiconductor substrate, and an N-type resistance element is formed in the P-well. By doing so, it is possible to form a thick field insulating film by selective oxidation on the P-type semiconductor region, and it is possible to form a highly reliable semiconductor device with no wiring restrictions, no characteristic fluctuations, and few steps. . Note that this example is given as -f':lII of the present invention, and is not intended to limit the scope of the present invention.

[Brief explanation of the drawing]

Figure 1 and 21V+ are the withstand voltages of conventional products! 1 肛i′(
FIG. 3 is a cross-sectional view of the main part of 1f11 according to the present invention.
The main part sectional views of the third embodiment and FIGS. 4 to 6 show the structure of the present invention.
! FIG. 3 is a cross-sectional view of a main part of a process showing an example of a method of transferring the product. In the figure, 21 is an N-type semiconductor group 4) 1ε, 2. l is P
type semiconductor region, and 24 is a resistor element connected to the N type semiconductor layer. 28 indicates a field insulating film. Figure 1 Figure 2 Figure 7 411'! ? J Figure 5 6th flash

Claims (1)

[Scope of claims] 4
A semiconductor device characterized by having 11 structures. (2) forming a P-type hollow body region in an N-type semiconductor substrate, forming a resistance element made of an N-type semiconductor layer in the P-type semiconductor region; 1. A method of manufacturing a semiconductor device, comprising the step of forming a field insulating film similar to a collector region on a P-type semiconductor region.