JPH0213993B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an emphasis device that converts a video signal into a signal having desired amplitude-frequency characteristics while keeping the group delay-frequency characteristics flat.

Conventional configurations and their problems In video tape recorders and the like that record and reproduce video signals, a frequency modulation recording method is common. In a frequency modulation/demodulation system, if the noise on the FM transmission line is white noise, the noise added to the demodulated signal exhibits so-called triangular noise characteristics, in which the noise level increases as the frequency increases. To alleviate this, before frequency modulation, the level of the high range of the input signal is increased (applying so-called emphasis to increase the frequency deviation width), and after frequency demodulation, the level of the high range of the input signal is increased. Signal processing is performed to reduce the level of the signal (so-called day emphasis). However, the band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in the frequency deviation width depending on the amount of emphasis, which limits the S/N ratio of the reproduced signal. It was hot.

Note that this problem occurs not only in video tape recorders, but also in all systems in which video signals are frequency-modulated and transmitted, such as in satellite broadcasting.

Purpose of the Invention The present invention solves the above-mentioned problems of the conventional art, and provides an emphasis device that can use a larger amount of emphasis than the conventional one with the same frequency deviation width as the conventional one, if the same FM transmission path is used. The purpose is to provide

Alternatively, it is an object of the present invention to provide an emphasis device in which the peak value of a waveform is significantly lower than that of the prior art even when the amount of emphasis is the same as that of the prior art.

A further object of the present invention is to provide an emphasis device having arbitrary transfer characteristics including preshoot and overshoot.

Structure of the Invention In order to solve the above object, an emphasis device of the present invention includes: a first transmission circuit that inputs a video signal and transmits the input signal according to a frequency characteristic determined by a transfer characteristic G; a first switch that switches the output signal of the transmission circuit every n (n is any positive integer) horizontal scanning periods according to an external control signal; and a first switch that switches the output signal of the transmission circuit every n horizontal scanning periods according to the control signal; a first memory circuit which sequentially inputs the output signals of the circuit via the first switch and sequentially outputs the inputted signals in reverse time series over the next n horizontal scanning periods; The output signal of the first transmission circuit is sequentially inputted via the first switch over n horizontal scanning periods by an opposite phase signal, and the input signal is inverted over the next n horizontal scanning periods. a second memory circuit that sequentially outputs data in series;
a second switch that outputs one series of signals by switching the output signal of the memory circuit in a phase opposite to that of the first switch; and an output signal of the second switch that is determined by the transfer characteristic G. a second transmission circuit that transmits with frequency characteristics, and an output signal of the second transmission circuit is controlled by an external control signal
a third switch that is switched every horizontal scanning period;
The control signal sequentially inputs the output signal of the second transmission circuit through the third switch over n horizontal scanning periods, and inverts the input signal over the next n horizontal scanning periods. A third memory circuit sequentially outputs signals in series, and an output signal of the second transmission circuit is sequentially inputted via the third switch for n horizontal scanning periods by an antiphase signal of the control signal, and the next A fourth circuit that sequentially outputs the input signals in reverse time series over n horizontal scanning periods.
and a fourth switch that outputs one series of signals by switching the output signals of the third and fourth memory circuits in a phase opposite to that of the third switch.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the description will be made using an emphasis circuit used in a video tape recorder (VTR) as an example of a video signal processing circuit. FIG. 1 shows a conventional emphasis circuit used in VHS type VTRs and the like. In FIG. 1, a video signal applied to input terminal 1 is outputted to output terminal 5 via emphasis circuit 50. The emphasis circuit 50 includes a capacitor (capacitance value C ₁ ) 51,
Resistance (resistance value Rb) 52, resistance (resistance value Ra) 53
It consists of These values are set to, for example, C ₁ ×Rb=1.3 μsec and Rb+Ra/Ra=5.

When a video signal as shown in FIG. 2a is input to the input terminal 1 of such a circuit, the output terminal 5
A signal as shown in FIG. 2b is obtained. In the case of a video tape recorder, the signal shown in Figure 2b is frequency-modulated and recorded on a magnetic tape (not shown), but because there is a limit to the frequency band of the electromagnetic conversion system that is the FM transmission path. , the signal is clipped at the point indicated by the broken line S in FIG. 2b, converted into a signal as shown in FIG. 2c, and frequency modulated. Alternatively, by changing the constants of each part of the emphasis circuit 50 and setting the amount of emphasis (=Rb+Ra/Ra) to 1/2, for example, a signal as shown in FIG. 2d is frequency-modulated. In the case of Fig. 2 c, there is a problem that waveform distortion occurs, and in the case of Fig. 2 d, the effect of emphasis is halved,
There is a problem in that the SN ratio of the reproduced signal decreases by that amount.

FIG. 3 shows an emphasis circuit using an example of the emphasis device of the present invention. In FIG. 3, the video signal applied to the input terminal 1 is supplied to a first transmission circuit 7 having a transfer function G. In FIG.

Note that the amplitude-frequency characteristics of the transmission circuit 7 determine the amplitude-frequency characteristics of the signal processing device according to the present invention. Although the amplitude-frequency characteristic of the transmission circuit 7 may be arbitrary, it is assumed here that it has an emphasis characteristic. The first transmission circuit 7
This is an emphasis circuit 22 as shown in the figure. The emphasis circuit 22 is a capacitor (capacitance value C ₂ )
23, Resistance (resistance value Rc) 24, Resistance (resistance value
Rd) 25. These values are set to, for example, Rc+Rd/Rd=2.5.

In such a circuit, when a video signal as shown in FIG. 2a is inputted, a signal as shown in FIG. 2e is obtained at the output terminal.

On the other hand, the signal whose level is inverted every 1H is CONT
It is added to terminal 115. This signal is obtained, for example, by inputting a horizontal synchronizing signal included in the input video signal to a flip-flop circuit (not shown). In this way, the signal supplied to the CONT terminal 15 is divided into two series. One series is applied to the control terminal 26 of the first switch 8 and the control terminal 28 of the first memory circuit 9, and is inverted by the inverter 17, and is applied to the control terminal 27 of the second switch 11 and the control terminal 28 of the first memory circuit 9.
It is supplied to the control terminal 29 of the second memory circuit 10. The other series is supplied to the control terminal 30 of the third switch 14 and the control terminal 32 of the third memory circuit 19 via a delay circuit 18 composed of, for example, a two-stage mono-multivibrator, and is also supplied to the inverter 22. and the control terminal 31 of the fourth switch 21 and the fourth memory circuit 2
0 control terminal 33. Note that the delay circuit 18 is set to match the delay time of the second transmission circuit 12, which will be described later.

Here, the video signal processed by the first transmission circuit 7 is also switched by the first switch 8 every horizontal scan (every 1H), and is transferred to the first memory circuit 9 and the second memory circuit every 1H. is input to the memory circuit 10 of. First memory circuit 9 and second memory circuit 10
consists of analog memory, for example,
Its storage capacity is 1H minutes. Control terminal 28, 2
When the control signal applied to control terminal 9 is at H level, the memory circuits 9 and 10 sequentially store the input signals, and when the control signal applied to control terminals 28 and 29 is at L level, the memory circuits 9 and 10 sequentially store the input signals. 9 and 10 are for outputting in a time series opposite to the stored time series. Further, the movable piece of the switch 8 is tilted toward the first memory circuit 9 side when the control signal applied to the control terminal 26 is at H level, and is tilted toward the second memory circuit 10 side when the control signal is at L level. As shown in FIG. 2f, the output waveform of the first memory circuit 9 is different from the input waveform [FIG. 2e].
It has a reverse time series with H as a unit. The output signal of the first memory circuit 9 and the output signal of the second memory circuit 10 are applied to a second switch 11. Second
The movable piece of the switch 11 is connected to the output terminal of the first memory circuit 9 when the control signal applied to the control terminal 27 is at the H level, and is connected to the output terminal of the second memory circuit 10 when the control signal is at the L level. Connected. As a result, at the output end of the second switch 11, a continuous signal whose time sequence is opposite to that of the input signal is obtained in units of 1H. This signal whose time series is reversed is supplied to the third switch 14 via the second transmission circuit 12 having the same transfer function G as the first transmission circuit 7. The input signal waveform of the third switch 14 is
Shown in Figure g. This signal is also switched by the third switch 14 every 1H and is input to the third memory circuit 19 and the fourth memory circuit 20.
The output signals of the third memory circuit 19 and the fourth memory circuit 20 are switched every 1H by the fourth switch 21 and converted into one continuous series of signals.
Third memory circuit 19 and fourth memory circuit 2
0 has the same circuit configuration as the first memory circuit 9 or the second memory circuit 10, and the control terminal 3
When the control signals applied to terminals 2 and 33 are at H level, the memory circuits 19 and 20 sequentially store the input signals, and when the control signals applied to control terminals 32 and 33 are at L level, the memory circuits 19 and 20 store the input signals in sequence. The memory circuits 19 and 20 output data in a time series opposite to the stored time series.

Furthermore, the movable pieces of the third switch 14 and the fourth switch 21 are pushed toward the third memory circuit 19 side when the control signals applied to the control terminals 30 and 31 are at H level, and when they are at L level, the movable pieces of the third switch 14 and the fourth switch 21 are It is tilted toward the fourth memory circuit 20 side.

The waveform of the signal output to the fourth switch 21 after undergoing such signal processing is shown in FIG. 2h.

The waveform shown in Fig. 2h has preshoot and overshoot, so even though the amount of emphasis is the same as the conventional example shown in Fig. 1, the waveform whose peak value is lower than the broken line S is can get.

The preshoot and overshoot shown here show exactly symmetrical waveforms.

Note that in the above description, the first, second, third, and fourth memory circuits 9, 10, 19, and 20 are analog memories (for example, charge transfer devices such as charge coupled devices). However, each memory circuit may have an A/D converter at its input end and a D/A converter at its output end, and the memory may be a digital memory composed of a flip-flop circuit or the like.

Furthermore, it has an A/D converter before the input terminal 1, and has first, second, third, and fourth memory circuits 9,
10, 19, and 20 are configured with digital memories composed of flip-flop circuits, etc., the first transmission circuit 7 and the second transmission circuit 12 are configured with non-recursive type digital filters or recursive type digital filters, and the output terminals Even if the configuration has a D/A converter after the D/A converter 5, the same operation is performed.

In addition, in the above explanation, a video signal is used as an input signal, and signals applied to the first, second, third, and fourth memory circuits 9, 10, 19, and 20 or the CONT terminal are all expressed in units of H. However,
Depending on the input video signal, these units may be n×H.
(However, n may be set to any positive integer.)
0, 19, and 20 as n×H).

Furthermore, in the above explanation, the first and second transmission circuits 7 and 12 were explained as emphasis circuits, but as shown in FIG.
A circuit for the purpose of providing overshoot may be used.

Effects of the Invention As described above, the emphasis device of the present invention has a first transmission circuit (corresponding to 7 of the above embodiment).
By arbitrarily selecting the transfer characteristic G of the second transmission circuit (corresponding to No. 12), it is possible to obtain a signal processing device having an arbitrary transfer characteristic including preshoot and overshoot.

As described above, when the emphasis device of the present invention is used as an emphasis circuit for a frequency modulation/demodulation system, by giving the waveform a preshoot and an overshoot, it is possible to maintain the same amount of emphasis as the conventional one and reduce the peak of the waveform. It is possible to realize an emphasis circuit whose value is much lower than the conventional one, and it is possible to obtain effects such as significantly lowering the frequency deviation width than the conventional one without reducing the amount of emphasis.

Alternatively, if the same frequency deviation width as the conventional method is used, it is possible to add more emphasis than the conventional method, and it is possible to obtain the effect that the SN ratio of the reproduced signal can be improved.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram showing an example of a conventional emphasis circuit, FIG. 2 is a signal waveform diagram, FIG. 3 is a schematic block diagram showing an example of the emphasis device of the present invention, and FIG. 4 is a diagram similar to that in FIG. FIG. 1 is a wiring diagram showing an example of the circuit configuration of a transmission circuit of FIG. 7...First transmission circuit, 8...First switch, 9...First memory circuit, 10...Second memory circuit, 11...Second switch, 12...Second transmission Circuit, 14...Third switch, 19...
. . . third memory circuit, 20 . . . fourth memory circuit, 21 . . . fourth switch.

[Claims]

1 comprising an emphasis circuit and a de-emphasis circuit, the emphasis circuit inputting a video signal and transmitting the input signal according to a frequency characteristic determined by a transfer characteristic G; and the first transmission circuit. a first switch that switches the output signal of the transmission circuit every n horizontal scanning periods (n is any positive integer) by an external control signal; a first memory circuit that sequentially inputs output signals through the first switch and outputs the input signals in reverse time series over the next n horizontal scanning periods; and a first memory circuit that sequentially outputs the input signals in reverse time series; n by signal
The output signals of the first transmission circuit are sequentially input through the first switch over a horizontal scanning period, and the input signals are sequentially output in reverse time series over the next n horizontal scanning periods. a second memory circuit; a second switch that outputs one series of signals by switching the output signals of the first and second memory circuits in a phase opposite to that of the first switch; a second transmission circuit that transmits the output signal of the switch with a frequency characteristic determined by the transmission characteristic G, and the de-emphasis circuit transmits a signal obtained based on the output signal of the second transmission circuit. a third transmission circuit that inputs the input signal and transmits the input signal according to the frequency characteristic determined by the transmission characteristic 1/G, and an output signal of the third transmission circuit.

Claims (1)

3 memory circuit, and the output signal of the second transmission circuit is sequentially inputted through the third switch over n horizontal scanning periods by an opposite phase signal of the control signal, and the output signal is inputted over the next n horizontal scanning periods. a fourth memory circuit which sequentially outputs the input signals in reverse time series; and a fourth memory circuit which switches the output signals of the third and fourth memory circuits in opposite phase to the switching of the third switch. and a fourth switch that outputs a series of signals. 2 The switching timing of the first, second, third, and fourth switches and the input/output switching timing of the first, second, third, and fourth memory circuits are performed based on the horizontal synchronization signal of the video signal. An emphasis device according to claim 1, characterized in that: