JPH0213994B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal processing device that converts a signal such as a video signal into a signal with desired frequency characteristics, and is applicable to video tape recorders and transmission systems such as satellite broadcasting. It is useful for use.

Conventional configurations and their problems In video tape recorders and the like that record and reproduce video signals, a frequency modulation recording method is common. In a frequency modulation/demodulation system, if the noise on the FM transmission line is white noise, the noise added to the demodulated signal exhibits so-called triangular noise characteristics, in which the noise level increases as the frequency increases. In order to reduce this, before frequency modulation, the level of the middle and high range of the input signal is increased (so-called emphasis is applied to increase the frequency deviation width), and after frequency demodulation, the level of the middle and high range of the input signal is increased. signal processing to lower the level of the signal (so-called de-emphasis). However, the band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in the frequency deviation width depending on the amount of emphasis, which limits the S/N ratio of the reproduced signal. It was hot.

Note that this problem occurs not only in video tape recorders, but also in all systems that frequency-modulate and transmit video signals, such as satellite broadcasting.

Purpose of the Invention The present invention solves the above-mentioned conventional problems, and provides a signal processing device that enables the use of a larger amount of emphasis than the conventional one, with the same frequency shift width as the conventional one, if the same FM transmission path is used. The purpose is to provide the following.

Alternatively, it is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that of the conventional art even when the amount of emphasis is the same as that of the conventional art.

A further object of the present invention is to provide a signal processing device having arbitrary transfer characteristics including preshoot and overshoot.

Structure of the Invention In order to achieve the above object, an information processing device of the present invention includes an emphasis circuit and a de-emphasis circuit, and the emphasis circuit receives a video signal and transfers the input signal to a frequency determined by a transfer characteristic G. a first transmission circuit that transmits based on the characteristics;
a first switch that switches the output signal of the first transmission circuit every n horizontal scanning periods (n is any positive integer) by an external control signal; a first memory circuit that sequentially inputs the output signal of the first transmission circuit via the first switch and sequentially outputs the input signal in reverse time series over the next n horizontal scanning periods; The output signals of the first transmission circuit are sequentially inputted via the first switch over n horizontal scanning periods by an opposite phase signal of the control signal, and the input signals are inputted over the next n horizontal scanning periods. a second memory circuit that sequentially outputs the signals in reverse time series, and outputs one series of signals by switching the output signals of the first and second memory circuits in an opposite phase to the switching of the first switch. The de-emphasis circuit includes a second switch and a second transmission circuit that transmits the output signal of the second switch with a frequency characteristic determined by the transmission characteristic G, and the de-emphasis circuit transmits the output signal of the second switch. A third transmission circuit inputs a signal obtained based on the signal and transmits the input signal according to a frequency characteristic determined by the transmission characteristic 1/G, and an output signal of the third transmission circuit is inputted from the outside. a third switch that is switched every n horizontal scanning periods by a control signal; a third memory circuit that sequentially outputs the input signals in reverse time series over n horizontal scanning periods; and a third transmission circuit that outputs the input signals over n horizontal scanning periods using an opposite phase signal of the control signal. a fourth memory circuit that sequentially inputs the output signals of through the third switch and sequentially outputs the input signals in reverse time series over the next n horizontal scanning periods;
a fourth switch that outputs one series of signals by switching the output signals of the third and fourth memory circuits in an opposite phase to the switching of the third switch;
and a fourth transmission circuit that transmits and outputs the output signal of the fourth switch with a frequency characteristic determined by the transmission characteristic 1/G.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the explanation will be given using an emphasis circuit used in a video tape recorder (VTR) as an example of a signal processing circuit. FIG. 1 shows a conventional emphasis circuit used in VHS type VTRs and the like. In FIG. 1, a video signal applied to an input terminal 1 is outputted to an output terminal 5 via an emphasis circuit 50. The emphasis circuit 50 includes a capacitor (capacitance value C ₁ ) 51, a resistor (resistance value Rb) 52, and a resistor (resistance value Ra) 53. These values are set to, for example, C ₁ ×Rb=1.3 μsec and Rb+Ra/Ra=5.

When a video signal as shown in FIG. 2a is input to the input terminal 1 of such a circuit, the output terminal 5
A signal as shown in FIG. 2b is obtained. In the case of a video tape recorder, the signal shown in Figure 2b is frequency-modulated and recorded on a magnetic tape (not shown), but because there is a limit to the frequency band of the electromagnetic conversion system that is the FM transmission path. , the signal is clipped at the point indicated by the broken line S in FIG. 2b, converted into a signal as shown in FIG. 2c, and frequency modulated. Alternatively, by changing the constants of each part of the emphasis circuit 50 and setting the amount of emphasis (=Rb+Ra/Ra) to 1/2, for example, a signal as shown in FIG. 2d is frequency-modulated. In the case of Fig. 2 c, there is a problem that waveform distortion occurs, and in the case of Fig. 2 d, the effect of emphasis is halved,
There is a problem in that the SN ratio of the reproduced signal decreases by that amount.

FIG. 3 shows an emphasis circuit 34 using an example of the signal processing device of the present invention, and FIG. 4 shows a de-emphasis circuit 35. In Fig. 3, the video signal applied to input terminal 1 is
The signal is supplied to the first transmission circuit 7 whose transfer function is G. The first transmission circuit 7 is an emphasis circuit 22 as shown in FIG. Emphasis circuit 22
is composed of a capacitor (capacitance value C ₂ ) 23, a resistor (resistance value Rc) 24, and a resistor (resistance value Rd) 25. These values are set to, for example, Rc+Rd/Rd=2.5. In such a circuit, a second
When a video signal as shown in Figure 2a is input, a signal as shown in Figure 2e is obtained at the output end.

On the other hand, the signal whose level is inverted every 1H is CONT
It is added to terminal 15. This signal is obtained, for example, by inputting a horizontal synchronizing signal included in the input video signal to a flip-flop circuit (not shown). In this way, the signal supplied to the CONT terminal 15 is applied to the control terminal 26 of the first switch 8 and the control terminal 28 of the first memory circuit 9, and is inverted by the inverter 17 to be applied to the control terminal 26 of the first switch 8 and the control terminal 28 of the first memory circuit 9. 11 and a control terminal 29 of the second memory circuit 10 .

Here, the video signal processed by the first transmission circuit 7 is also switched by the first switch 8 every horizontal scan (every 1H), and is transferred to the first memory circuit 9 and the first memory circuit every 1H. The signal is input to the memory circuit 10 of No. 2.
First memory circuit 9 and second memory circuit 10
consists of analog memory, for example,
Its storage capacity is 1H minutes. Control terminal 28, 2
When the control signal applied to control terminals 28 and 29 is at H level, the memory circuits 9 and 10 sequentially store the input signals, and when the control signals applied to control terminals 28 and 29 are at L level, the memory circuits 9 and 10 sequentially store the input signals. 9 and 10 are for outputting in a time series opposite to the stored time series. Further, the movable piece of the switch 8 is pushed toward the first memory circuit 9 when the control signal applied to the control terminal 26 is at H level, and pushed toward the second memory circuit 10 when it is at L level. The output waveform of the first memory circuit 9 is similar to that of the second memory circuit 9.
As shown in Figure f, it has an inverse time series in units of H with respect to the input waveform [Figure 2 e]. The output signal of the first memory circuit 9 and the output signal of the second memory circuit 10 are applied to a second switch 11.
The movable piece of the second switch 11 is connected to the output terminal of the first memory circuit 9 when the control signal applied to the control terminal 27 is at the H level, and is connected to the output terminal of the second memory circuit 10 when the control signal is at the L level. Connected to the terminal. As a result, at the output end of the second switch circuit 11, a continuous signal whose time sequence is opposite to that of the input signal is obtained in units of 1H. This signal having an opposite time series is outputted to the output terminal 2 via the first transmission circuit 7 and the second transmission circuit 12 having the same transfer function G. The signal output to the output terminal 2 is an emphasized video signal in the sense of the present invention. In a VTR (not shown), after frequency modulating the emphasized video signal,
Recording is performed on a magnetic tape (not shown) via a magnetic head (not shown).

During reproduction of a VTR (not shown), a reproduced signal is obtained by scanning a recorded magnetic tape (not shown) with a magnetic head (not shown). By passing this reproduced signal through a frequency demodulator (not shown), a demodulated signal as shown in FIG. 2g is obtained. Such a signal is supplied to the input terminal 6 of the de-emphasis circuit 35 shown in FIG.
The signal supplied to the input terminal 6 is supplied to the third switch 14 via the third transmission circuit 3. Here, the third transmission circuit 3 has the first transmission characteristic.
is set to be the reciprocal of the transmission circuit 7. As a result, the input signal waveform of the third switch 14 becomes as shown in FIG. 2f. This signal is also switched every 1H by the third switch 14.
The signal is input to the third memory circuit 19 and the fourth memory circuit 20. The output signals of the third memory circuit 19 and the fourth memory circuit 20 are transmitted to the fourth switch 2.
1, it is switched every 1H and converted into a continuous signal. The third memory circuit 19 and the fourth memory circuit 20 have the same circuit configuration as the first memory circuit 9 or the second memory circuit 10, and the control signals applied to the control terminals 32 and 33 are at H level. At this time, the memory circuits 19 and 20 sequentially store the input signals, and when the control signals applied to the control terminals 32 and 33 are at L level, the memory circuits 19 and 20 store the stored time series. outputs in reverse chronological order.

Furthermore, the movable pieces of the third switch 14 and the fourth switch 21 are pushed toward the third memory circuit 19 side when the control signals applied to the control terminals 30 and 31 are at H level, and when they are at L level, the movable pieces of the third switch 14 and the fourth switch 21 are It is tilted toward the fourth memory circuit 20 side.

The waveform of the signal output to the fourth switch 21 after undergoing such signal processing is shown in FIG. 2e.
The output signal of the fourth switch 21 is outputted to the output terminal 5 via the fourth transmission circuit 4. Similarly to the third transmission circuit, the fourth transmission circuit 4 is set so that its transmission characteristic is a reciprocal of that of the first transmission circuit 7 (or second transmission circuit 12). As a result, a video signal having a waveform similar to that shown in FIG. 2a is obtained at the output terminal 5.

The waveform shown in Fig. 2g has preshoot and overshoot, so even though the amount of emphasis is the same as the conventional example shown in Fig. 1, the waveform whose peak value is lower than the broken line S is can get.

The preshoot and overshoot shown here show exactly symmetrical waveforms.

Note that in the above description, the first, second, third, and fourth memory circuits 9, 10, 19, and 20 are analog memories (for example, charge transfer devices such as charge coupled devices).
However, each memory circuit may have an A/D converter at its input end and a D/A converter at its output end, and the memory may be a digital memory composed of a flip-flop circuit or the like.

Furthermore, an A/D converter is provided before the input terminal 1, the first and second memory circuits 9 and 10 are configured with digital memories constituted by flip-flop circuits, etc., and the first transmission circuit 7 and the The same operation can be achieved even if the second transmission circuit 12 is configured with a non-recursible digital filter or a recursible digital filter and a D/A converter is provided after the output terminal 5. A similar configuration is also possible for the de-emphasis circuit 35.

In addition, in the above explanation, a video signal is used as an input signal, and signals applied to the first, second, third, and fourth memory circuits 9, 10, 19, and 20 or the CONT terminal are all expressed in units of H. However,
Depending on the input video signal, these units may be n×H.
(However, n may be set to any positive integer). Along with this, the first, second, third,
The capacity of each of the fourth memory circuits 9, 10, 19, and 20 is assumed to be n×H.

Further, in the above description, the emphasis circuit was explained, but it may also be used in a circuit for the purpose of providing preshoot or overshoot, as shown in FIG. 2g.

Effects of the Invention As described above, the signal processing device of the present invention can arbitrarily set the transfer characteristic G of the first transmission circuit (corresponding to 7 in the above-mentioned embodiment) and the second transmission circuit (corresponding to 12 in the same). Depending on the selection, signal processing with arbitrary emphasis characteristics including preshoot and overshoot can be obtained.

As described above, when the signal processing device of the present invention is used as an emphasis circuit for a frequency modulation/demodulation system, by providing waveform preshoot and overshoot, it can have the same amount of emphasis as the conventional one, and It is possible to realize an emphasis circuit in which the peak value of the waveform is much lower than in the past, and it is possible to obtain effects such as the frequency deviation width to be much lower than in the past without reducing the amount of emphasis.

Alternatively, if the same frequency deviation width as the conventional method is used, it is possible to add more emphasis than the conventional method, and it is possible to obtain the effect that the SN ratio of the reproduced signal can be improved.

Furthermore, the output signal of the emphasis circuit is further passed through a circuit that reverses the time series so that the time series of the signal is the same as the input signal, so that the output signal is transferred to the signal transmission path (in a VTR, the FM modulator, recording amplifier, tape head system, etc.). , which shows a transmission path consisting of a regenerative amplifier and an FM demodulator), the present invention reverses the time sequence of the signal in the de-emphasis circuit, although the time sequence of the signal is reversed in the signal transmission path. Since it is equipped with a circuit, the circuit that reverses the time series,
A total of two sets, one set for the emphasis circuit and one set for the de-emphasis circuit, is required, which has the effect of reducing the circuit scale.

[Brief explanation of drawings]

Figure 1 is a wiring diagram showing an example of a conventional emphasis circuit, Figure 2 is a signal waveform diagram, Figures 3 and 4 are
Each figure is a schematic block diagram showing an example of the signal processing device of the present invention, and FIG. 5 is a wiring diagram showing an example of the circuit configuration of the first transmission circuit in FIG. 3... Third transmission circuit, 4... Fourth transmission circuit, 7... First transmission circuit, 8... First switch, 9... First memory circuit, 10... Second transmission circuit. Memory circuit, 11... second switch, 12... second transmission circuit, 14... third switch, 19...
. . . third memory circuit, 20 . . . fourth memory circuit, 21 . . . fourth switch.

[Claims]

1. A data slicing circuit that slices and extracts a data pulse signal superimposed on a predetermined horizontal scanning period of a television signal, which includes means for clamping the data pulse signal and applying a direct current bias to the output signal from the clamping means. means for limiting the lower limit voltage at a voltage, means for detecting a peak having a discharge time constant sufficiently smaller than the horizontal period, means for voltage dividing the output signal from the peak detecting means, and means for voltage dividing the output signal from the voltage dividing means at one side. A data slicing circuit characterized in that it includes a reference input and a voltage comparator to which the output signal of the clamping means is applied to the other comparison input.

Claims (1)

a third switch that switches the output signal of the third transmission circuit every n horizontal scanning periods according to an external control signal; a third memory circuit which sequentially outputs the input signals in reverse time series over the next n horizontal scanning periods; a fourth memory circuit that sequentially inputs the output signals of the transmission circuits through the third switch and sequentially outputs the input signals in reverse time series over the next n horizontal scanning periods;
a fourth switch that outputs one series of signals by switching the output signals of the third and fourth memory circuits in an opposite phase to the switching of the third switch;
and a fourth transmission circuit that transmits and outputs the output signal of the fourth switch with a frequency characteristic determined by the transmission characteristic 1/G. 2. According to claim 1, the transfer characteristic G of the first and second transmission circuits is an emphasis characteristic, and the transfer characteristic 1/G of the third and fourth transmission circuits is a de-emphasis characteristic. signal processing device.