JPH022356B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an emphasis circuit that processes frequency characteristics of an input video signal or the like.

Conventional configurations and their problems In video tape recorders and the like that record and reproduce video signals, a frequency modulation recording method is common. In frequency modulation and demodulation systems, if the noise in the FM transmission line is white noise, the noise added to the demodulated signal increases as the frequency increases.
It exhibits a so-called triangular noise characteristic in which the noise level also increases. In order to reduce this, before frequency modulation, the levels of the middle and high frequencies of the input signal are increased (so-called emphasis), and after frequency demodulation,
Signal processing is performed to reduce the levels of the mid and high frequencies (so-called de-emphasis). but,
The band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the amount of increase in frequency deviation width due to emphasis, which causes the problem of limiting the S/N ratio of the reproduced signal. It was hot. Note that this problem occurs not only in video tape recorders (VTRs), but also in all systems that frequency-modulate and transmit video signals, such as satellite broadcasting.

Figure 1 shows a conventional emphasis circuit used in VHS VTRs and the like. In FIG. 1, a video signal applied to an input terminal 1 is outputted to an output terminal 5 via an emphasis circuit 50. The emphasis circuit 50 includes a capacitor (capacitance value C ₁ ) 51, a resistor (resistance value R _b ) 52, and a resistor (resistance value R _a ) 53. Their values are
For example, C ₁ ×R _b = 1.3μsec, (R _a +R _b )/R _a = 5
is set to .

When a video signal as shown in FIG. 2a is input to such a circuit, a signal as shown in FIG. 2b is obtained at the output terminal. In the case of a video tape recorder, the signal shown in Figure 2b is frequency-modulated and recorded on a magnetic tape (not shown), but because there is a limit to the frequency band of the electromagnetic conversion system that is the FM transmission path. , the signal is clipped at the point indicated by the broken line S in FIG. 2b, and the signal is frequency-modulated as shown in FIG. 2c. Alternatively, by changing the constants of each part of the emphasis circuit 50 and setting the emphasis amount (=R _b +R _a /R _a ) to 1/2, the frequency is modulated to create a signal as shown in FIG. 2d. .

However, in the case of Fig. 2c, there is a problem that waveform distortion occurs, and in the case of Fig. 2d, the effect of the emphasis is reduced to 1/2, and the reproduced signal is affected accordingly.
There is a problem that the signal-to-noise ratio decreases.

Purpose of the Invention The present invention solves the above-mentioned problems of the conventional art, and provides an emphasis circuit that enables the use of a larger amount of emphasis than the conventional one with the same frequency deviation width as the conventional one, provided the same FM transmission line is used. The purpose is to

Alternatively, it is an object of the present invention to provide an emphasis circuit in which the peak value of the waveform is significantly lower than that of the conventional art even when the amount of emphasis is the same as that of the conventional art.

A further object of the present invention is to provide an emphasis circuit having arbitrary transfer characteristics including preshoot and overshoot.

Another object of the present invention is to compensate for the phase characteristics of a transmission circuit and to make the phase change of a processed signal zero in real time.

Configuration of the Invention The emphasis circuit of the present invention includes a first switch, a first signal processing circuit, a second signal processing circuit,
It consists of five parts: a second switch and a control signal generation circuit. The first switch is switched every T time to distribute the input signal to the first signal processing circuit and the second signal processing circuit. The first signal processing circuit includes a third switch, a first transmission circuit, a fourth switch, a first memory circuit, and a second memory circuit. The first and second memory circuits are
Signals are sequentially input over T time, and the input signals are output in reverse time series over the next T time. The third switch is closed only during a period when a signal is output from the first memory circuit, and connects the first memory circuit and the first transmission circuit. At this time, the movable piece of the first switch is leaning toward the second signal processing circuit. The fourth switch is switched every T time and is alternately connected to the first memory circuit and the second memory circuit. The second signal processing circuit includes a fifth switch, a second transmission circuit, a sixth switch, a third memory circuit, and a fourth memory circuit. The operation of each part of the circuit is delayed by T time with respect to the first signal processing circuit.

That is, the third switch and the fifth switch operate in opposite phases, and the fourth switch and the sixth switch operate in opposite phases. Further, writing and reading of the first and fourth memory circuits are performed in the same phase, the second memory circuit operates in the opposite phase to the first memory circuit, and the second memory circuit and the third memory circuit operate in the same phase. It works. The second switch switches the first switch when the second memory circuit is in the read state for a time T.
At the next time T, it falls to the side of the second signal processing circuit and is connected to the fourth memory circuit which is in the read state. The control signal generation circuit is configured to generate two signal sequences, one that is inverted every time T, and the other that is repeatedly inverted with an opposite phase to this signal, and supply them to each part of the circuit.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows an emphasis circuit using an embodiment of the emphasis circuit of the present invention. In FIG. 3, a video signal applied to the input terminal 1 is applied to the first signal processing circuit 2 and the second signal processing circuit 3 via the first switch 6, and is applied to the first signal processing circuit 2 and the second signal processing circuit 3 via the second switch 7. and is output to the output terminal 5. A signal whose level is inverted every 1H is applied to the control terminal 4. This signal can be used, for example, to convert an input synchronization signal into a flip-flop circuit (not shown).
It can be obtained by inputting . The signal supplied to the control terminal 4 and inverted every 1H is divided into two series.

One series is the control terminal 1 of the first switch 6.
9, the control terminal 20 of the second switch 7 , the control terminal 22 of the fourth switch 9 , the control terminal 23 of the fifth switch 10 , the control terminal 25 of the first memory circuit 14 , the control terminal 25 of the fourth memory circuit 17 It is input to the control terminal 28. The other series is inverted by the inverter 18 and is connected to the control terminal 21 of the third switch 8, the sixth
The signal is input to the control terminal 24 of the switch 11, the control terminal 26 of the second memory circuit 15, and the control terminal 27 of the third memory circuit 16.

Here, the video signal applied to input terminal 1 is
The signal is switched by the first switch 6 every horizontal scan (every 1H) and is input to the first transmission circuit 12 and the second transmission circuit 13 . The output signal of the first transmission circuit 12 is input to the fourth switch 9, switched every 1H, and input to the first memory circuit 14 and the second memory circuit 15. First memory circuit 14
The second memory circuit 15 is composed of, for example, an analog memory, and has a storage capacity of 1H. When the control signals applied to the control terminals 25 and 26 are at H level, the memory circuits 14 and 1
5 stores the input signals sequentially, and controls the control terminal 2.
When the control signals applied to 5 and 26 are at L level, the output is in a time series opposite to the stored time series. The output signal of the first memory circuit 14 is input to the third switch 8. When the signal is output from the first memory circuit 14, the control terminal 21 of the third switch 8 is at H level, and the third switch 8 is closed, so that the signal is output from the first memory circuit 14.
is input again to the transmission circuit 12 of. The time series of the signals input again is the reverse time series. Also, at this time, the control terminal 19 of the first switch 6 is at L level, so the movable piece of the first switch 6 is tilted toward the second signal processing circuit 3. Therefore, no signal from input terminal 1 is input. The output signal of the first transmission circuit 12 is input again to the fourth switch 9. Since the control terminal 22 of the fourth switch 9 is at the L level, the movable piece of the fourth switch 9 is tilted toward the second memory circuit 15 side.
Moreover, since the control terminal 26 of the second memory circuit 15 is at H level at this time, the output signal of the fourth switch 9 is stored in the second memory circuit 15. When the input of 1H worth of signals to the second memory circuit 15 is completed, the control terminal 26 of the second memory circuit 15 becomes L level, and the second switch 7
is output to. Control terminal 20 of second switch 7
becomes H level, and the movable piece of the second switch 7 falls to the second memory side, so the second switch 7
The input signal to is output to the output terminal 5. At this time, since the control terminal 19 of the first switch 6 becomes H level, the input signal from the input terminal 1 is input to the first signal processing circuit 2. The signal passing through the second signal processing circuit 3 is sent to the first signal processing circuit 2.
Since there is a delay of 1H, the output signal appearing at the output terminal 5 is switched by the second switch 7 and becomes a continuous signal. Furthermore, the time series of the output signal is the same as the time series of the input signal to the input terminal 1.

Here, the feature of the present invention is that the input signal passes through the first and second transmission circuits 12 and 13 twice. In the first pass, positive time series, 2
The second pass is a negative time series. Therefore, the signal flow is shown in FIG. 5.

The input signal to the first transmission circuit 61 is x(n), the output signal of the transmission circuit 61 is f(n), the output signal of the first time series inversion circuit 62 is a(n), and the output of the transmission circuit 63 Let b(n) be the signal, y(n) be the output signal of the second time series inversion circuit 64, and h(n) be the unit impulse responses of the transmission circuits 61 and 63, respectively. The z transformation of each signal is expressed as X(z), F(z), A(z),
Assuming B(z), Y(z), and H(z), F(z)=H(z)X(z) A(z)=F(z ^-1 )=H(z ^-1 )X( z ^-1 ) B(z) = H(z) A(z) = H(z) H(z ^-1 )X(z ^-1 ) Y(z) = B(z ^-1 ) = H(z ^{- 1} ) _{H (} z) (z ^-1 )H(z) When written in terms of Fourier transform, it becomes H _eq (e ^jw )H | (e _jw ) | ² , and the phase change is zero. This zero-phase characteristic is desirable in video signal processing, and can be achieved with the circuit configuration shown in FIG. 3. In particular, in the configuration shown in FIG.
However, in Figure 3, the signal passes through the same circuit twice, so the phase characteristics of the transmission circuit are completely canceled out, and it is possible to accurately achieve zero phase. realizable. Further, the gain of the system shown in FIG. 5 is the square of that in the case of one stage of transmission circuit. Therefore, if the required gain is G, then the gain of one stage of the transmission circuit in the system shown in FIG. 5 must be √G.

First transmission circuit 12 and second transmission circuit 13
is an emphasis circuit 30 as shown in FIG. The emphasis circuit 30 includes a capacitor (capacitance value C ₂ ) 31, a resistor (resistance value R _c ) 32, and a resistor (resistance value R _d ) 33. For these values, since the same signal passes through the first or second transmission circuit twice, the amount of emphasis is squared as described above. Therefore, for the conventional example shown in FIG. 1, for example, R _c +R _d /R _d =√5 is set.

As a result of the emphasis, a signal as shown in FIG. 2e is input to the first memory circuit 14. The input signal to the second memory circuit 15 is as shown in FIG. 2f. Therefore, the output terminal 5 shown in FIG.
A signal as shown in Fig. 2g appears. The waveform in Figure 2g has preshoot and overshoot, so even though the amount of emphasis is the same as the conventional example shown in Figure 1, a waveform with a peak value lower than the broken line S is obtained. It will be done.

In addition, in the above explanation, the first, second, third, and fourth
Each of the memory circuits 14, 15, 16, and 17 is an analog memory (for example, a charge transfer device such as a charge coupled device), but each memory circuit has an AD converter at the input end, and the output A DA converter may be provided at the end, and the memory may be a digital memory composed of a flip-flop circuit or the like. Further, an AD converter is provided before the input end of the first switch 6, and the first, second, third, fourth memory circuits 14, 15,
16 and 17 are digital memories composed of flip-flop circuits, etc., and the first transmission circuit 12
The same operation can be achieved even if the second transmission circuit 13 is configured with a digital filter and a DA converter is provided after the second switch. Furthermore,
An AD converter is provided before the input terminal 1, and first, second, third, fourth memory circuits 14, 15, 16,
17 is a digital memory composed of a flip-flop circuit, etc., the first transmission circuit 12 and the second transmission circuit 13 are composed of a nonrecursive type digital filter or a cursive type digital filter, and D/A conversion is performed after the output terminal 5. The structure with a container also operates in a similar manner.

In addition, in the above explanation, the video signal was used as the input signal, so all the signals applied to the first, second, third, and fourth memory circuits 14, 15, 16, 17 or the control terminal 4 are Although H is used as a unit, the units may be set to any time depending on the input signal.

In addition, in the above explanation, the emphasis circuit was explained, but as shown in FIG. .

Effects of the Invention As described above, the emphasis circuit of the present invention passes a signal through the transmission circuit once in a positive time series,
Next, by passing the signal through the same transmission circuit in reverse time sequence and outputting it, it is possible to continuously adjust the phase characteristics of the transmission circuit to zero phase in real time, which is particularly useful in video signal processing. be. Furthermore, since the same transmission circuit can be used twice, the circuit configuration becomes simpler.

Furthermore, as described above, when the emphasis circuit of the present invention is used as an emphasis circuit for a frequency modulation/demodulation system, by giving the waveform a preshoot and an overshoot, it can have the same amount of emphasis as the conventional one, and It is possible to realize an emphasis circuit in which the peak value of the waveform is much lower than in the past, and there is an effect of reducing the frequency deviation width much more than in the past without reducing the amount of emphasis. Alternatively, if the same frequency shift width as before is used, it is possible to add more emphasis than before and improve the S/N ratio of the reproduced signal.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram showing an example of a conventional emphasis circuit, FIG. 2 is a signal waveform diagram, FIG. 3 is a schematic block diagram showing an embodiment of the emphasis circuit of the present invention, and FIG. A wiring diagram showing an example of the circuit configuration of the first transmission circuit, and FIG. 5 is a block diagram explaining the concept used to realize zero-phase characteristics in the present invention. 2, 3... Signal processing circuit, 6, 7, 8, 9, 1
0,11...Switch, 12,13...Transmission circuit, 14,15,16,17...Memory circuit, 2
9...Control signal generation circuit.

Claims (1)

[Claims] 1. First and second switches that switch input signals, third and fourth switches that switch input signals, and a transfer function G.
a first transmission circuit having a frequency characteristic that increases the level of medium and high frequencies of an input signal;
and a second memory circuit, fifth and sixth switches for switching input signals, and frequency characteristics determined by the same transfer function G as the first transmission circuit. a second signal processing circuit comprising a second transmission circuit having a second transmission circuit and third and fourth memory circuits; and a control signal generating means for controlling switching of the first to sixth switches. Each of the first, second, third, and fourth memory circuits receives a signal over a time T determined by the control signal generated from the control signal generating means, and receives the input signal over the next time T. is configured to output in reverse time series, the input signal is switched every T time by the first switch and distributed to the first and second signal processing circuits, and the input signal is distributed to the first and second signal processing circuits. The input signal is stored in the first memory circuit by switching the fourth switch via the first transmission circuit for a first T time, and this stored signal is stored in the first memory circuit for a next T time. The information is read out in the reverse chronological order from when it was stored, passes through the first transmission circuit again via the third switch, and is stored in the second memory circuit by switching the fourth switch. From the second signal processing circuit,
T from the signal transmitted to the first signal processing circuit
After the time-delayed signal is processed in the same way as in the first signal processing circuit, it is output from the fourth memory circuit via the second switch, and the signal processed signal is output from the fourth memory circuit. the first and second
An emphasis circuit characterized in that the signals are output alternately from the signal processing circuit, converted into one series of signals, and outputted.