JPS61182385A - Signal processor - Google Patents

Abstract

PURPOSE:To avoid unnecessary waveform change to an output signal by passing through a signal once to a transmission circuit at a positive time series, outputting the signal through the same transmission line at the opposite time series next and switching the processing at the center of a horizontal synchronizing signal when a continuous signal is processed while being sectioned. CONSTITUTION:An H synchronization signal detection circuit 17 detects an H synchronizing signal timing from a signal inputted from an input terminal 1 and a control signal generating circuit 18 generates a control signal (a) at the center of the horizontal synchronizing signal. The output signal of the 1st transmission circuit 11 is shown in a signal (b). A signal inputted to the 1st switch 12 is switched at each time H by using the control signal (a) and inputted to the 1st memory circuit 13 and the 2nd memory circuit 15. A signal written in the 1st memory circuit 13 over the period H is started to be read by the control signal (a) and read in the opposite time series to the written time series over the next H period and inputted to the 2nd switch 14.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device for processing the frequency characteristics of an input signal in video equipment or the like.

Conventional technology In recent years, new media have been developed for video equipment, and home-use V
TR, video disks, fiber optic cables, broadcasting satellites, etc. appeared. In order to take advantage of the characteristics of these new media, there is an increasing demand for higher image quality and higher definition for individual video equipment. 2. Description of the Related Art VTRs that record and reproduce video signals have conventionally used a recording method that utilizes frequency modulation and demodulation.

If the noise on the FM transmission path is white noise, the noise added to the demodulated signal exhibits so-called triangular noise characteristics in which the noise level increases as the frequency increases. In order to reduce this, before frequency modulation, the level of the middle and high frequencies of the input signal is increased (so-called emphasis is applied to increase the frequency deviation width), and after frequency demodulation, the middle and high range levels of the input signal are increased. Signal processing is performed to lower the level of the area (so-called de-emphasis). However, the band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in frequency deviation width due to the amount of emphasis, which limits the S/N ratio of the reproduced signal. There was a problem. Please note that this problem is VT
This problem occurs not only in R but also in all systems that transmit frequency modulated video signals, such as satellite broadcasting, and is an issue that must be solved in order to achieve high image quality and definition. There is.

FIG. 4 is a wiring diagram of a conventional emphasis circuit used in VH8 type VTRs and the like. In FIG. 4, the video signal applied to the input terminal 1 is transmitted to the emphasis circuit 5.
It is output to output terminal 5 via o. Emphasis circuit 6
0 is a capacitor (capacitance value C1) sl, a resistor (resistance value R
h)52. It is composed of a resistor (resistance value Ra) 53. Their values are set to, for example, C1xRb=1.3 (microseconds) (Ra+Rb)/Ra=5.

When a video signal as shown in FIG. 6(,) is input to such a circuit, a signal as shown in FIG. 5(b) is obtained at the output terminal.

Problems to be Solved by the Invention In the case of a VTR, a signal as shown in FIG. 5(b) is frequency-modulated and recorded on a magnetic tape (not shown). Since there is a limit to the frequency band, the signal is clipped at the point shown by the broken line S in FIG. 5(b), and the signal is frequency-modulated as shown in FIG. 6(c). Alternatively, the constant of the emphasis circuit 6o may be changed to generate a signal as shown in FIG. 6(d), for example, to perform frequency modulation. In the case of FIG. 5(C), there was a problem of waveform distortion, and in the case of FIG. 5(d), there was a problem of a decrease in the emphasis S/N ratio.

In view of the above-mentioned problems, an object of the present invention is to provide a signal processing device that makes it possible to use a larger amount of emphasis than before with the same frequency shift width as before, provided the same FM transmission line is used. . Alternatively, it is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that of the conventional art with the same amount of emphasis as the conventional one. Furthermore,
The object of the present invention is to provide a signal processing circuit having arbitrary transfer characteristics with preshoot and overshoot. In addition, it compensates for the phase characteristics of the transmission circuit,
It is an object of the present invention to provide a signal processing device that can reduce the phase change of a processed signal to zero in real time.

Means for Solving the Problems In order to solve the above problems, the signal processing device of the present invention includes:
A first transfer circuit having a transfer function of G, a first switch, a first memory circuit, and a transfer function of nH from the first switch.
A second switch that operates with a time delay, a second transmission circuit having the same transfer function G as the first transmission circuit, a second memory circuit, an H-sink signal detection circuit, and a center of the H-sink. A control signal generation circuit that generates a control signal is provided, and the signal processed by the first transmission circuit is transmitted to the first memory circuit and the second transmission circuit by a first switch that is switched at the center of the H sync signal every nH time. 2
The signals that are sequentially input to the first memory circuit and written to the first memory circuit over an nH period are read out over the next nH period in the reverse chronological order of the writing time, and
The signal written to the second memory circuit during the nH period of reading of the memory circuit is read out in the reverse time series in the next nH period, and the second switch is switched nH time later than the first switch. It is configured to be input to the second transmission circuit as one series of signals by the switch and processed, and the switching timing of the first switch and the writing and reading of the first memory circuit and the second memory circuit are controlled. The switching timing and the switching timing of the second switch are provided from the control signal generation circuit at the center of the H sync signal every nH time based on the H sync timing generated by the H sync detection circuit. It is.

Effect: By adopting the above-described configuration, the present invention allows a signal in the nH interval to pass through a transmission circuit having the same transfer characteristic in the forward time and in the reverse time. The signal flow is shown in Figure 2. The input signal to the first transmission circuit 61 is x(
n), the output signal of the transmission circuit 61 is f(n), the output signal of the first time series reversal circuit 62 is a(,), the transmission circuit 63
Let b(n) be the output signal of , and h(n) be the unit impulse responses of the transmission circuits 61 and 63, respectively. The two transformations of each signal are X(z), F(z), A(z), B(z
), then F (z) = H (z) X (z) A (z) = F (z-' ) = H (z-' )
z-' ) B (z) = H(z) A(z) = H(z)
H(z-')
H(z)H(z). However, the output signal of the system shown in FIG. 2 has a time series that is opposite to the time series of the input signal. If you want to obtain a signal in the same time series as the input signal, use the second
A time series reversal circuit may be connected to the output end of the system shown in the figure.

When the equivalent impulse response of the system shown in FIG. 2 is expressed by Fourier transform, Heq (e i'')=l H(e'') 12, and the phase change is zero. This zero-phase characteristic is desirable in video signal processing, and the above equation shows that it can be achieved by adopting the configuration shown in FIG. The gain of the system shown in FIG. 2 is the square of the one-stage transmission circuit. Therefore, if the required gain is iG, the gain of one stage of the transmission circuit of the system shown in FIG. 2 must be G2. When the system shown in FIG. 2 is used as an emphasis circuit, if all the signals shown in FIG. 3(a) are input, a signal shown in FIG. 3(d) is obtained. The signal in FIG. 3(d) has a waveform with preshoot and overshoot, so even though the amount of emphasis is the same as the conventional example shown in FIG. 4, its peak value is indicated by the broken line S. A lower waveform is obtained.

This figure shows an example diagram. Note that since an emphasis circuit will be described here as an example of the signal processing device 10, the signal processing device 10 will be referred to as an emphasis circuit 10 hereinafter. Now, consider the case where the signal shown in FIG. 3 (,) is input to the input terminal 1. Here, n = 1
The following is the explanation.

The H tank signal detection circuit 17 detects the H sync timing from the signal input to the input terminal 1.

According to the output of the H sync signal detection circuit 17, the control signal generation circuit 18 generates a third signal at the center of the H sync.
Generate a control signal as shown in the figure (,). 1st
The output signal of the transmission circuit 11 is as shown in FIG. 3(b). The signal input to the first switch 12 is switched by the control signal at the center of the H sink every H time, and the signal is switched between the first memory circuit 13 and the second memory circuit 1.
5 is input. The signal written in the first memory circuit 13 over the H period starts reading by the control signal, and is read out over the next H period in reverse chronological order with respect to the writing time sequence and input to the second switch 14. be done. The signal written to the second memory circuit 16 during the H period when the signal is being read from the first memory circuit 13 starts to be read by the control signal,
The signals are read out in reverse chronological order over the next H period and input to the second switch 14. The second switch 14 selects the signals alternately outputted from the first memory circuit 13 and the second memory circuit 15 every H time periods according to the control signal, and selects the signals that are outputted alternately from the first memory circuit 13 and the second memory circuit 15 every H time periods, and outputs a series of signals as shown in FIG. 3(C). Outputs the signal.

The signal that has passed through the second transmission circuit 16 appears at the output terminal 2 with a waveform as shown in FIG. 3(d).

Here, consider the case where the signal time series is reversed at a location other than the center of the H sink. If reversal is performed at a point other than the center of H sync, the signal level will generally fluctuate every 1H, so
The output signal of the second switch 14 becomes a discontinuous signal at switching point P in FIG. 3C. Therefore, when reverse time axis emphasis is performed by the second transmission circuit 16,
As shown in FIG. 3(f), an unnecessary differential waveform is generated at the switching point. In order to avoid this, it is necessary to perform the reversal at a signal portion where the turning point does not become discontinuous after the time series reversal, or where the discontinuity falls within a tolerance value. This condition is that at least the signal level at the current time and after 1H time are the same level.

That is, the reversal may be performed at the tip of the H sink, the back pouch, the front pouch, etc. of the H sink. Among these, the H sink center point where the waveform change caused by the first transmission circuit 11 is the least is desirable.

Note that although n=1 in the above description, n≧2 may also be used. Further, although two systems of memory circuits are used, the same effect can be obtained even if three or more systems are used.

Further, the first and second memory circuits 13.15 can be realized by analog memories (for example, charge transfer devices such as charge coupled devices), but AD (analog-digital) is provided at the input terminal of each memory circuit. ) converter and a DA (digital-to-analog) converter at the output end, and the memory may be a digital memory composed of a flip-flop circuit or the like.

Further, an AD converter is provided before the input end of the first transmission circuit 11, and the first. The second memory circuits 13 and 15 are digital memories composed of flip-flop circuits, etc., and the first. The same operation can be achieved even if the second transmission circuits 11 and 16 are configured with digital filters and a DA converter is provided after the second transmission circuit 16. Furthermore, an AD converter is provided before the input terminal 1, and the first . The second memory circuits 13 and 15 are digital memory circuits composed of flip-flop circuits, etc., and the first. Second transmission circuit 11.
Even if 16 is configured with a non-recursive digital filter or a recursive digital filter and a DA converter is provided after the output terminal 2, the same operation will be achieved.

Furthermore, in the above description, H sink detection was performed from the signal before the first transmission circuit 11;
1, the input of the second transmission circuit 16, or the output of the second transmission circuit 16 to perform H sink detection, the same operation is performed.

Furthermore, in the above explanation, the video signal was used as the input signal, so the first. Second memory circuit 13.15 1st. The operations of the second switches 12 and 14 are performed in units of periods based on H, but these units may be set to any time depending on the input signal. Also, in the above explanation, it was explained as an emphasis circuit, but the third
As shown in Figure (d), it may be used in a circuit intended to provide preshoot or overshoot. Furthermore, in the above explanation, an output signal in reverse time series is obtained with respect to the input signal, but it is also possible to further reverse the time series of the output signal from the above circuit and convert it into an output in the same series as the input signal. do not have.

Effects of the Invention As described above, the signal processing device of the present invention passes a signal once through a transmission circuit in a positive time series, and then passes it through the same transmission circuit in a reverse time series and outputs it. This has the effect of making the phase characteristic of the transmission circuit zero phase, and is particularly useful for video signals.

In addition, since switching is performed at the center of the H sink when processing continuous signals in sections, unnecessary waveform changes are not caused to the output signal.

Furthermore, as described above, when the signal processing device of the present invention is used as an emphasis circuit for a frequency modulation/demodulation system, it can have the same amount of emphasis as the conventional one by having a waveform 1 pre-cut and an overshooter. However, it is possible to realize an emphasis circuit in which the peak value of the waveform is significantly lower than that of the conventional one, and there is an effect of significantly reducing the frequency deviation width than the conventional one without reducing the amount of emphasis. Alternatively, if the same frequency shift width as before is used, it is possible to add more emphasis than before, and the SNN of the reproduced signal can be completely improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the signal processing device of the present invention, FIG. 2 is a block diagram explaining the concept used to realize zero-phase characteristics in the present invention, and FIG. 3 is the same as that of FIG. FIG. 4 is a wiring diagram showing an example of a conventional emphasis circuit, and FIG. 6 is a signal waveform diagram of each part of the illustrated embodiment. 11...First transmission circuit, 12...First switch, 13...First memory circuit, 1
4...Second switch, 15...Second switch
memory circuit, 16...second transmission circuit, 17
...H sink signal detection circuit%18...
Control signal generation circuit, 10...signal processing device. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure No. 41!1 5th cause

Claims (1)

[Claims] A first transmission circuit whose transfer function is G, a first switch, a first memory circuit, and a transfer function of nH from the first switch.
(where n: any positive integer, H: horizontal scanning period); a second switch that operates with a time delay; a second transmission circuit having the same transfer function G as the first transmission circuit; 2
a memory circuit, an H sync signal (horizontal synchronization signal) detection circuit, and a control signal generation circuit that generates a control signal at the center of the H sync, and the signal processed by the first transmission circuit is A signal that is sequentially input to the first memory circuit and the second memory circuit by the first switch that switches at the center of the H sync signal every time, and is written to the first memory circuit over an nH period. is read out over the next nH period in the reverse chronological order to the write time, and the signal written to the second memory circuit during the nH period of reading of the first memory circuit is read out over the next nH period. is read out in reverse time series, and is input to the second transmission circuit as one series of signals by the second switch, which is switched nH times later than the first switch, and is processed. and the switching timing of the first switch,
The writing and reading switching timing of the first memory circuit and the second memory circuit, and the switching timing of the second switch are set at every nH time based on the H sink timing generated by the H sink detection circuit. A signal processing device characterized in that a sync signal is provided from the control signal generation circuit at the center thereof.