JPS5844875A - Afc circuit - Google Patents

Abstract

PURPOSE:To decrease the effect of a ghost signal component and other noise components, by executing AFC operation based on a horizontal synchronizing signal and a burst signal. CONSTITUTION:A video signal from an input terminal IN is applied to a synchronizing separation circuit 31 and a band pass filter 32, and a horizontal synchronizing signal and a burst signal are separated. The signals are inputted to phase detectors 35, 36 and the phase of them is compared with an output frequency- dividing an output of a voltage controlled oscillator 40 at a frequency divider 41. The output of the detectors 35, 36 is summed at an adder 38 after being through low pass filters 37 and 39 respectively. The voltage controlled oscillator 40 is controlled with the output of the adder 38 to form the AFC loop.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AFC (automatic frequency control) circuit that controls the oscillation frequency in a television receiver, etc. This relates to an AFC circuit.

2. Description of the Related Art Horizontal oscillation circuits in television receivers and the like use an AFC circuit to control the oscillation frequency. In this case, the AFCu path compares the phase of the horizontal synchronizing signal separated from the television signal and the phase of the output of the oscillation circuit, and controls the oscillation frequency based on the comparison result. In this case, since the phase of the synchronization signal is used as the reference phase, the synchronization signal separation means is in focus.

FIG. 1 shows a conventional AP'C circuit, in which a horizontal synchronizing signal 8N is separated from a video signal BP by a synchronizing separation circuit 11. This separated horizontal synchronization signal EK is supplied to one input terminal of the phase detector 12. The other input terminal of the phase detector 12 is supplied with an equal signal obtained by frequency-dividing the output of the direct voltage controlled oscillator VCQ13 by the divider 14.

The phase detector 12 receives a synchronization signal S.

A phase comparison is made between the output of the frequency divider 14 and the output of the frequency divider 14. A voltage based on the result of this phase comparison is supplied to the VCO 13, and an AFC operation is performed.

The synchronous separation circuit 11 of this conventional AFC circuit has two transistors Ql+ and Q12, and the video signal Bp from the input terminal IN is supplied to the base of the Q-th transistor via the capacitor Ctx. Suppose now that a video signal of negative polarity arrives. At this time, the transistor Q++ clamps the tip of the horizontal synchronizing signal SI at a predetermined voltage, and the transistors Q and 12 are connected to the front six transistors Q.
, 11 are turned off when their collector currents decrease.

FIG. 2 shows how the video signal S/
The horizontal synchronizing signal 8z (second
) is the signal S of the output terminal OUT in the AFC loop.
Indicates a state in which synchronization with O is achieved. In this case, noise components superimposed on the horizontal synchronization signal F3H and ghost signal components due to transmission distortion are not considered, but jitter actually occurs due to these influences.

That is, if we explain this by assuming that a positive ghost signal component is superimposed on the synchronization signal part as shown in Figure 3 α, the superimposed ghost signal part is separated as a horizontal synchronization signal (as shown in Figure 3 ), the phase of the output signal SO is shifted by Δφ from the normal phase ψO, and when a negative ghost signal component is superimposed, a similar synchronously separated output is obtained, and the phase of the output signal SO is normal. ts'l phase ψ0. Note that such a shift becomes a problem particularly when a ghost signal component whose delay time is up to the pulse width of the horizontal synchronizing signal sH is superimposed.

In this way, in the conventional AlI'C circuit, the horizontal synchronizing signal 8M is separated with the leading end of the incoming horizontal synchronizing signal SJF being clamped.
When a noise component such as a ghost cancellation signal component is mixed into the signal, the AFC operation is performed at a phase different from the original phase. This causes VCOl 3 in the AFC loop to have a constant phase error, or the horizontal synchronization signal EJ
When separating x, even the picture signal part is separated, causing problems such as jitter, and further problems such as synchronization disturbance. It goes without saying that the desired operation cannot be obtained even if an AI'C circuit with such a drawback is used in a horizontal oscillation circuit.In addition, such a drawback is that the signal obtained by AF (41) operation cannot be used as a reference pulse. This also poses a big problem in systems that operate predetermined circuits as a simulator.

Here, for reference, an example of the system as described above will be explained using FIG. 4. The system shown in Figure 4 is C0D.
This is a ghost removal device that removes ghost signal components from a television signal using a transversal filter having a tapped analog delay line constituted by a (1!L load coupling element), an LC circuit, or the like.

In the figure, IN is a video signal input terminal, and OUT is a video signal output terminal. Video No. 4N Pi' input from input terminal IN! ,
) The ghost signal component is eliminated in the ranceversal filter 21, and the ghost signal component is led out to the output terminal OUT. The transversal filter 21 detects a video signal including a ghost signal component. It has a function of canceling the ghost signal component by adding a signal of opposite polarity to the ghost No. 1 component. That is, the transversal filter 21 has a tapped analog delay line, and each tap of the tapped analog delay line is provided with a weighting circuit for generating a ghost cancellation signal. An analog memory is provided corresponding to each weighting circuit. Digital data converted into analog signals stored in each storage section (corresponding to each tap) of the tap gain memory section 28 (described later) is written into each analog memory.

This analog quantity serves as a weighting coefficient in the weighting circuit.

In this way/to eliminate the ghost signal component, the ghost signal component and the regular video signal date? phase difference with
It is necessary to know the loss width of the ghost signal component. This is detected as follows.

The output video (i) of the transversal filter 2 is input to a subtractor 22. This subtractor 22 inputs the video signal S
It has the function of differentiating P.

The output of this differentiator 22 is applied to one input terminal of a comparator 23 and compared with a reference level. The output (0#.1) of the comparator 23 is input to the buffer register 24. Here, the buffer register 24 introduces and stores the output of the comparator 24 for a predetermined period from the leading edge of the vertical synchronization signal. In this case, in the differentiator 22,
A differential pulse is generated at the leading edge of the vertical synchronization signal of the original television signal and the ghost signal component. Therefore, the data stored in the buffer register 24 is the ghost signal component and the regular video No. 4i S? shows the phase difference between The data stored in the buffer register 24 is read out cyclically during the vertical synchronization signal period, and is applied to one input terminal of the correlator 25. The output of the digital differentiator 27 is input to the other input terminal of the correlator 25 . video signal s
p is input to a waveform integrator 26, the leading edge portion of the vertical synchronization signal is waveform integrated, and its digital data is stored within this waveform integrator 26. This waveform integrator 26
The digital data is input to the correlator 25 via the differentiator 27 in synchronization with the data read timing of the buffer register 24 .

The correlator 25 has a function of detecting a distortion signal, and detects the digital difference device 27 according to the output of the buffer register 24.
Cumulatively add the outputs of . Then, the polarity of the cumulatively added result is determined and 0 or l is output. The output of the correlator 25 is written into a corresponding storage section of the tap gain memory section 28 in accordance with the phase difference between the leading edge of the vertical synchronization signal and the ghost signal component. For example, in the case of a positive polarity ghost, this calculation adds 1", and in the case of a negative polarity ghost, 1" is added.
The data in each storage section of the tap gain memory section 28 is rewritten every l vertical scanning period. □ The tap gain memory section 28 corresponds to a plurality of taps of the transversal filter 21. The data in each memory section is incremented by -1 or +1 depending on the output (0 or 1) of the correlator 25.The data in each memory section of the tap gain memory section 28 is as follows: It is input to the corresponding analog memory of the transversal filter 21 via a digital-to-analog converter (hereinafter referred to as a D/A converter) 29. At this time, the tap gain memory section 2
From 8, data to remove positive polarity ghosts,
The polarity data that identifies the data that should be used to remove negative polarity ghosts is also read out, and the transversal filter 28
is applied to the control terminal of Note that the data in each analog memory of the transversal filter 21 is rewritten every l horizontal scanning period.

The above operation is returned to sb, and the tap gain memory section 28
When the data in each storage section of 2 is condensed to a certain value, a value that can sufficiently eliminate the ghost signal, the output of the correlator 28 becomes either 1'' or 'O'', and the output of the tap gain memory is The data oscillates across the least significant bit or bits+.

A timing pulse generator 30 generates timing pulses for obtaining the data read timing of the buffer register 24, the data read timing of the tap gain memory section 28, etc. described above. This tie wave generator 30 is generally an AFCl as mentioned above.
A signal is generated in synchronization with a synchronization signal separated from the input video signal, and this signal is used as a reference pulse to obtain the timing pulse as described above. Therefore, as described above, if the circuit 170 does not operate normally due to the incorporation of ghost signal components, problems such as the inability to remove the ghost signal components from the video signal P arise.

In view of the above points, it is an object of the present invention to provide a 170 circuit that is less affected by ghost signal components and other noise components.

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

First, the present invention stabilizes the AFC operation. [In order to do this, phase detection is performed on the horizontal synchronization signal S separated by the synchronization separation circuit and the frequency-divided output of the VCO output. ANC loop 1 that controls the video signal Sp
A loop is provided which extracts a burst signal, detects the deviation, performs phase detection on the pulse obtained by frequency-dividing the output of the VCO, and controls the VCO with this detected output. It is characterized by this.

FIG. 5 is a circuit diagram showing a typical embodiment of the present invention. In the figure, the video signal E3F (
(see FIG. 6 α) is supplied to the synchronous separation circuit 31 and also to the 3.58 MHz band pass filter BPF 32.

The synchronization separation circuit 31 separates the synchronization signal SE (see FIG. 6) from the video signal Bp. Only the burst signal component passes through the BPil' 32, and the output of the B and P.F 32 is detected by the detector 33, mainly the burst signal. Detector 3
For example, 3 is a envelope 1 line detector, or a burst signal with a phase of 1800 -
It may also be an arithmetic detector that performs detection by multiplication with the subcarrier.The output terminal of the detector 33 is
A pulse always occurs during the burst signal period, but it is not determined to be 0 during the picture period. The detected output of the detector 33 is compared with a threshold level vr by a comparator 34 having an appropriate threshold level vr.

The output pulse PO of this comparator 34 is shown in FIG. 6C.

The output of the synchronous separation circuit 31 and the output of the comparator 34 are respectively supplied to the eleventh and second phase detectors 35 and 36 as reference phase signals. The output of the phase detector 35 is supplied to one input terminal of an adder 38 through a first low-pass filter 37 . The output of the phase detector 36 is supplied to the other input terminal of the adder 38 via a second low-pass filter 39. The output of adder 38 is supplied to VCO 40 as a control voltage. The output of the VCO 4Q is frequency-divided by the divider 41 and supplied to the phase detector 2 35, 36. The frequency-divided output P1 supplied to the phase detector 35 is shown in FIG. 6d, and the frequency-divided output P3 supplied to the phase detector 36 is shown in FIG. 6f. In addition, the phase detectors 35 and 36 each further use the branch output P11P3 to receive a pulse P2 (sixth pulse) generated from a ROM (not shown).
(see Figure 6), P4 (see Figure 6g) are also provided.

In such a configuration, an AFC looper consisting of phase detector 35 → filter 37 → adder 38 → VCO 40 → frequency divider 41 → phase detector 35, and phase detector 36 - →
Filter 39 → Adder 38 → VCO 40 → Frequency divider 41-
→It has two AFC loops (1) and (2) consisting of the phase detector 36.

卆The operation in the above configuration will be explained. - First, the frequency divider 41
−? Pulse P 11P 2 generated by ROM,
Are Ps and P4 video signals S? When synchronized with , as shown in FIG. 6, the rising edge of the pulse PI is one position before the center of the horizontal synchronizing signal S, and the pulse P 2 rl: Horizontal synchronizing signal SI period 3 and before and after that. -L n level, otherwise H”
level. Further, the rising portion of the pulse P3 rises near the center of the pulse Pa period, and the pulse P4 becomes ``L'' level during the pulse Pa period and before and after it.
Otherwise, it will be @H# level. The phase of the pulse P1 is detected by the phase detector 35 with respect to the horizontal synchronizing signal 8I.

The phase of the pulse P3 and the pulse Po are detected by the phase detector 36.

The phase detectors 35 and 36 are configured, for example, as shown in FIG. In the figure, Q+''-Q, sf are transistors, R1-,,f (3 is a resistor, and C+.

C2 is a capacitor, Kl, I! i2 is a constant voltage source, and 10B is a power supply. Transistors Qs, Q4,
The base of Qz has input terminals III, IN2, and N3 is provided. The collectors of transistors Q+ and Q2 have output terminals 0U.
TI and 0UT2 are provided. FIG. 8 shows the detection characteristics of the phase detection circuit constructed in this way. In the figure, the vertical axis indicates the phase difference θ between the video signal Hp and the frequency-divided output, the characteristic curve α is the detection characteristic in the phase detector 35, and the characteristic curve β is the characteristic curve in the phase detector 36. It is.

Now, let us consider the periods during which AFC loops E and AFC operate as non-feedback loops, that is, the T1 period in the characteristic curve α and the T2 period in the characteristic curve β. By making the DC detection sensitivity of the phase detector 36 larger than that of the phase detector 35 and further adjusting the bands of the low-pass filters 37 and 39 appropriately, the open gain characteristic of the AFC Rouguet can be changed to the one shown by the dashed line in FIG. If the open gain characteristics of the AFC loops 1 and 2 are set as shown by the dotted line in FIG. Note that in FIG. 9, the vertical axis shows the gain G, and the horizontal axis shows the frequency f. It can be seen from this composite oven gain characteristic that the negative feedback loop period is approximately - around the intersection frequency.
It is stable with a slope of 20 db/d.

In addition, the composite oven gain characteristic depends on the AFC loose loop in the high range, and on the AEI'O loop in the low range. Therefore, the initial pull-in operation is performed by the horizontal synchronizing signal sx
The steady state phase error or low frequency performance depends on the burst signal.

Therefore, as explained and explained in FIG. 3, the separated synchronization signal 8I becomes thinner due to the superposition of ghost signal components, etc.
Even if the phase of the pulses P1 to P4 or the output of VC040 deviates from the normal state, the horizontal synchronization signal Eg
If it is pulled in to a certain extent by using , it will now depend on the parstoig number, so no phase shift will occur. In this case, the pulse P obtained by detecting the burst signal
Assuming that the OO width is shifted and narrowed due to the superposition of ghost signal components, etc., first, using Fig. 3, the horizontal synchronization signal S,
As explained in the case where a ghost signal component is superimposed on the signal, a stationary error etc. 6 occurs, but even if the ghost signal component is superimposed, if the pulse PO does not become thinner, no phase shift will occur due to the control action of the ANC loop (2).

Here, the reason why the pulse Po is not biased even if a ghost signal component is added will be explained. Figure 1O (here, B
The signal passing through PF32 has a BPF32 of 3°58MH.
Since it has a narrow band pass characteristic of 2, its lIO'' level does not change even due to AFL, ghost signal components, etc. as shown in Figure 1O.
.

If the signal obtained by shifting the phase of the carrier signal locked to the burst signal by the automatic phase control APC means is wt, then the output obtained by multiplying both signals by the detector 33 using, for example, a multiplicative detector is TA (-cts 2
sat+focus θ], and when the 2wt component is blocked by a low-pass filter (not shown), the output A of the detector 12.

The force becomes a halus with an amplitude of ■, as shown in Figure 10. When this pulse is compared by a comparator 34 using an appropriate threshold level Vr, the comparison result is a pulse 'pO' shown in FIG. 6C.

Next, when a ghost signal component with a short delay time is included, B
The output of the PF 32 is a signal obtained by adding the burst ghost signal of FIG. 11 to the burst signal of FIG. 11 α. In this case, depending on the phase of the burst ghost signal, the output of the detector 33 becomes books as shown in FIG. 11a, d, -. FIG. 11G shows when the burst ghost signal is in opposite phase to burst No. 41, FIG. 11d shows when the burst ghost signal is in the same phase as the burst signal, and FIG.
indicates when the burst ghost signal has a phase difference of 2 and 3 from the burst signal.

Here, if the amplitude level of the burst ghost signal is made m (<1) times the amplitude level A of the burst signal, the detected burst ghost signal will be -2 AnL at maximum, but since it is a multiplication output, the detected letter burst ghost The amplitude level of the signal is smaller than -2-A except when it is in the opposite phase and in the same phase, and this is usually more common.

Furthermore, in this case, since the 0'' level is not convenient, there is no need to clamp and separate it like the horizontal synchronizing signal, and by cutting at an appropriate threshold level Vr with the comparator 34, the information can be set to an appropriately small value, for example, τ. If it is below, the width will not become narrower due to shifting to one side.

As described in detail above, according to this embodiment, the horizontal synchronization signal BH separated by the synchronization separation circuit and the output of the VCO are frequency-divided and the nine-frequency output is phase-detected. extracts a burst signal from the video signal SP, performs phase detection on the pulse obtained by detecting this and the frequency-divided output obtained by dividing the output of the yco,
Since the configuration includes an AFC loop that controls the VCO using this detection output, it causes the most steady phase error compared to the conventional AFC circuit that only separates the horizontal synchronization signal S and performs AP'C operation. 9 AFC is not only able to reliably eliminate stationary phase errors even when a ghost signal component of the delay time up to the pulse width of the horizontal synchronization signal sr, which is easy to cause, is mixed in, but also is always stable even when other noise components are mixed in. can perform actions.

According to the present invention, it is possible to provide an APC circuit that is less affected by ghost signal components and other noise components.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional AFC circuit, and Figure 2 is a circuit diagram showing a conventional AFC circuit.
Figure 3 is a No. 41 waveform diagram to explain the shortcomings of Figure 1. Figure 4 is a signal waveform diagram to explain the operation of the figure.
A fifth circuit diagram showing an example of a system that operates a predetermined circuit using a signal obtained by the operation as a reference pulse.
The figure is a circuit diagram showing an embodiment of the AFC circuit according to the present invention,
Fig. 6 is a signal waveform diagram for explaining the operation of Fig. 5, Fig. 7 is a circuit diagram showing a specific circuit configuration of the phase detector in Fig. 5, and Fig. 8 is a phase detection characteristic diagram of Fig. 7. , FIG. 9 is an open gain characteristic diagram of FIG. 5, and FIGS. 10 and 11 are signal waveform diagrams for explaining the operation of FIG. 5. 31...Synchronization separation circuit 32...Band Pannu filter 0 3φ...Detector 34...Comparator 35.36...Phase detector 3.7.39...Low pass filter 38...・Adder 40... Voltage control token 41... Frequency divider Applicant's agent Patent attorney Takehiko Suzue Figure 1 11 Figure 3 Part 4 Figure 280

Claims (1)

[Claims] a sync separation circuit for separating a sync signal from an input video 1'# signal; a burst signal detection means for detecting a burst signal from the input video signal; a second phase detector to which the detected output of the detector is supplied to one input terminal; an adder that adds the detected outputs of the eleventh and second phase detectors; and a voltage controlled oscillator whose output is supplied as a control signal and whose output is supplied to the other input ends of the first and second phase detectors.