JPS61182386A - Signal processor - Google Patents

Abstract

PURPOSE:To obtain a signal whose time base is restored completely by passing through a signal to a transmission line once at a positive time series, outputting the signal through the same transmission circuit at the opposite time series next and applying time base inverting processing. CONSTITUTION:The 1st control signal generating circuit 18 generates a control signal A after a time (a) from the trailing of an H synchronizing signal. The signal (b) processed by the 1st transmission circuit 1 is inputted to the 1st switch 12, switched at each time H by the control signal A and inputted to the 1st and 2nd memory circuits 13, 15. The signal written in the 2nd memory circuit 15 at the period H when the signal is read from the 1st memory circuit 13 is read at the opposite time series over the next H period and inputted to the 2nd switch 14. Further, the 2nd control signal generating circuit 26 generates a control signal B at a time (H-a) from the trailing of the horizontal synchronizing signal. Similar signal processing is applied. As a result, a signal (e) is obtained at an output terminal 2.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device for processing the frequency characteristics of an input signal in video equipment.

Conventional technology In recent years, new media have been developed for video equipment, and home-use V
TR, video disc, optical 7 fiber cable, broadcasting satellite, etc. appeared. In order to take advantage of the characteristics of these new media, there is an increasing demand for higher image quality and higher definition for individual video equipment. 2. Description of the Related Art VTRs that record and reproduce video signals have conventionally used a recording method that utilizes frequency modulation and demodulation.

If the noise on the FM transmission path is white noise, the noise added to the demodulated signal exhibits so-called triangular noise characteristics in which the noise level increases as the frequency increases. In order to reduce this, before frequency modulation, the level of the middle and high range of the input signal is increased (so-called emphasis is applied to increase the frequency deviation width), and after frequency demodulation, the level of the middle and high range of the input signal is increased. Signal processing is performed to lower the level (so-called de-emphasis). However, the band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in frequency deviation width due to the amount of emphasis, which limits the S/N ratio of the reproduced signal. There was a problem. Please note that this problem is VT
This problem occurs not only in R but also in all systems that transmit frequency modulated video signals, such as satellite broadcasting, and is an issue that must be solved in order to achieve high image quality and quality. There is.

FIG. 4 is a wiring diagram of a conventional effect system circuit used in VH8 type VTRs and the like. In FIG. 4, the video signal applied to the input terminal 1 is transmitted to the emphasis circuit 6.
0 and is output to the output terminal 6. Enf 1 cis circuit 6
o is a capacitor (capacitance value C1) 51, a resistor (resistance value R
h) 52 and a resistor (resistance value Ra) 53.

Those values are, for example, C1×Rb=1.3 (microseconds), (Ra+Rh)/
Ra=5 is set.

When a video signal as shown in FIG. 2(a) is input to such a circuit, a signal as shown in FIG. 2(b) is obtained at the output terminal.

Problems to be Solved by the Invention In the case of a VTR, a signal as shown in FIG. 5 is frequency-modulated and recorded on a magnetic tape (not shown).
Since the frequency band of the electromagnetic conversion system, which is the FM transmission path, is limited, the signal is clipped at the point shown by the broken line S in Figure 5 (Figure 6 (c)) and frequency modulated. Alternatively, frequency modulation is performed to create a signal as shown in Figure 6(d).In the case of Figure 6(c), there is a problem of waveform distortion; In some cases, there was a problem in that the emphasis SN ratio decreased.

In view of the above-mentioned problems, an object of the present invention is to provide a signal processing device that makes it possible to use a larger amount of emphasis than before with the same frequency shift width as before, provided the same FM transmission line is used. It is something.

Alternatively, it is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that in the conventional art, with the same amount of enfuss as in the conventional art.

A further object of the present invention is to provide a signal processing device having arbitrary transfer characteristics with preshoot and barshoot. Another object of the present invention is to provide a signal processing device that can compensate for the phase characteristics of a transmission circuit and zero out the phase change of a processed signal in real time.

Means for Solving the Problems In order to solve the above problems, the signal processing device of the present invention is configured such that a first signal processing circuit and a second signal processing circuit are connected in series; The first signal processing circuit includes a first transmission circuit having a transfer function G1, a first switch,
n H(
However, n: any positive integer, H: horizontal scanning period) A second switch that operates with a time delay, a second transmission circuit that has the same transfer function 01 as the first transmission circuit, and H
The second signal processing circuit 40 includes a sync signal (horizontal synchronization signal) detection circuit and a first control signal generation circuit that generates a signal delayed by α time from the end of the H sync. A third transmission circuit that is G2, a third switch, a third memory circuit, a fourth switch that operates with nH from the third switch, a fourth memory circuit, and a third transmission circuit. A fourth transmission circuit having the same transfer function G2 as the circuit, a second H sync signal detection circuit, and a second control signal that generates a signal with a time delay of (H-α) from the falling edge of the H sync signal. It is equipped with a generation circuit,
The signal input to the first signal processing circuit passes through the first transmission circuit and is transmitted from the end of the H sync signal to α at every nH time.
is input to the first memory circuit and the second memory circuit sequentially by the first switch which switches after the time nH.
The signal written to the first memory circuit over the period is read out over the next nH period in the reverse chronological order to the time of writing, and is written to the second memory circuit during the nH period of reading from the first memory circuit. The written signal is read out in reverse time series in the next nH period, and the nH
A second switch that switches with a time delay is input to the second transmission circuit as one series of signals, and the switching timing of the first switch and the switching timing of writing and reading of the first memory circuit and the second memory circuit are input to the second transmission circuit. , the switching timing of the second switch is determined based on the H sink timing generated by the first H sink detection circuit, every nH time after α time from the end of the H sink,
The signal is configured to be given from the first control signal generation circuit, and the signal input to the second signal processing circuit is
Via the third signal processing circuit, the third memory circuit and the fourth memory circuit are sequentially connected to the third memory circuit and the fourth memory circuit by the third switch which is switched after (H-a) time from the end of the H sink signal every nH time. The signal inputted and written to the third memory circuit over the nH period is read out over the next nH period in the reverse time sequence to the time of writing, and during the nH period of reading from the third memory circuit, the signal is The signals written in the memory circuit are read out in reverse time series in the next nH period,
The fourth switch, which switches nH time later than the third switch, inputs one series of signals to the fourth transmission circuit, and determines the switching timing of the third Sakai switch, the third memory circuit, and the fourth memory circuit. The switching timing between writing and reading and the switching timing of the fourth switch are determined by the second H.

Based on the H sync timing generated by the sync detection circuit, the control signal is applied from the second control signal generation circuit every nH time (H-α) after the fall of the H sync signal.

Effect: By adopting the above-described configuration, the present invention allows a signal in the nH interval to pass through a transmission circuit having the same transfer characteristic in the forward time and in the reverse time. The second diagram shows the signal flow.
It will look like the figure. The input signal to the first transmission circuit is I(n
), the output signal of the first transmission circuit is f(n), the output signal of the first time series inversion circuit is a(nλ), the output signal of the second transmission circuit is b(n), the output signal of the third transmission circuit is The output signal is a(n)
, the output signal of the second time series inversion circuit is d(n), the output signal of the fourth transmission circuit is e(n), and the first . Let the unit impulse response of the second transmission circuit be ql(n), and let the unit impulse response of the third transmission circuit be ql(n). The unit impulse response of the fourth transmission circuit is 92 (
n), the two transformations of each signal are x(z), F(z),
A(z), B(z).

Ca)IDa)tEa), h(n), q(n) 2
Let G1(z) and G2(z) be the transformations, then F(z)=C1(z)X(z) A(z)=F(z-')=C1(z-')X(
z-')B(z)=C1(z)A(z)=C1
(z)G1 (z-')X(z-') C(z) =C2(z),]lJ'z)=C2(z)G
1 (z)G1(z-')Xa-')D(z)=C
(z)=C2a)G1a)G1a)Xa)
E(z)=C2(z)D(z)=C2(z)G2(z-
' ) G1 (z-' ) G1 (z) (z) =C1(z)G1 (z-1)G2(z-')G2(
z). Expressing the equivalent impulse response of the system in Figure 2 using Fourier transform, we get Geq(elo>= l G1 <e i Town G2(e
l')12, and the phase change is zero. This zero-phase characteristic is desirable in video signal processing, and the above equation shows that it can be achieved by adopting the configuration shown in FIG. When using the system shown in Figure 2 as an emphasis circuit,
If you input a signal like the one shown in Figure 3 (Xu), you will get a signal like the one shown in Figure 3 (→).

Figure 3 (→) has a waveform with preshoot and overshoot, so the amount of emphasis is
Although the waveform is the same as the conventional example shown in the figure, a waveform whose peak value is lower than the broken line S is obtained.

Embodiment An embodiment of the signal processing device of the present invention will be described below. FIG. 1 is a block diagram of the apparatus 1o of the same embodiment. Note that since an emphasis circuit will be described here as an example of the signal processing device 10, the signal processing device 1o will be hereinafter referred to as an emphasis circuit 1o. Now, consider the case where the signal shown by (-) in FIG. 3 is input to the input terminal 1. Here, the following explanation will be given assuming n=1. Also,
The gains of the third transmission circuit 19 and the fourth transmission circuit 24 are assumed to be 1. The signal is 1st. Since the signal is processed by the second transmission circuit 11.16, the gain of the first signal processing circuit 3o is the square of the gain of the first transmission circuit. Therefore, when the gain of the entire signal processing device 1o is G, the second signal processing circuit 4
If the gain of 0 is 1, then the first H sync signal detection circuit 17 detects the H sync timing. According to the output of the first H sync signal detection circuit 17, the first control signal generation circuit 18 generates the control signal A at time α after the falling edge of the H sync signal. First transfer circuit 1
The signal processed in 1 becomes like a god in Figure 3 (1).
is input to the switch 12. The signal input to the first switch is switched at every H time by the control signal A, and is input to the first and second memory circuits 13 and 15. The signal written in the first memory circuit 13 over the H period starts reading by the control signal A, and is read out over the next H period in reverse chronological order with respect to the writing time sequence, and is read out to the second switch 14. is input. During the H period when the signal is being read from the first memory circuit 13, the signal written to the second memory circuit 15 is read out in reverse chronological order over the next H period and is sent to the second switch 14. is input. second switch 14
is the first memory circuit 13 according to the control signal A.
and the signals alternately output from the second memory circuit 16 every H period, and output a series of signals as shown in FIG. 3(C). The signal passing through the second transmission circuit 16 is transmitted as shown in FIG.
d), which is input to the second signal processing circuit 4o. The second H sync signal detection circuit 25 detects the H sync timing from the signal input to the second signal processing circuit 4o. According to the output of the H sync signal detection circuit 25, the second control signal generation circuit 26
Control signal B is generated at time (H-α) from the fall of the sync signal. Below, control signal B
Accordingly, signal processing similar to that of the first signal processing circuit 3o is performed. As a result, a signal as shown in FIG. 3(e) is obtained at the output terminal 2. If the generation timing of the control signal B in the second signal processing circuit 4o is not at the time after the fall of the H sink (H-α), the signal in FIG. 3 (=) is
Signals from other H periods are mixed into the H period. That is, it is not possible to obtain a complete emphasis signal corresponding to the input signal shown in FIG. 3(-). In addition, the timing of the time series reversal in the first signal processing circuit 30 is set so that the switching point P in FIG. , for example, near the center of the H sync signal. Also, the first
The input signal to the H sync signal detection circuit 1 of 1 used the signal before the first transmission circuit 11, but the first transmission circuit 1
The output signal of the first switch 14, the output signal of the second switch 14, or the output signal of the second transmission circuit 16 may be used. Similarly, the input signal to the second H sync signal detection circuit used the input signal of the third transmission circuit 19, but the output signal of the third transmission circuit 19, the output signal of the fourth switch 22,
Alternatively, the output signal of the fourth transmission circuit 24 may be used. Further, although the entire signal processing device 10 has been described as an emphasis circuit, the first signal processing circuit 3o
It is also possible to use the second signal processing circuit 4o as an emphasis circuit and the second signal processing circuit 4o as a de-emphasis circuit. That is, when it is desired to obtain an inverse time series emphasis waveform, it is sufficient to simply use the first signal processing circuit 30. When the second signal processing circuit 4o is used as a de-emphasis circuit, the gains of the third transmission circuit 19 and the fourth transmission circuit 24 are set to In the above explanation, in order to set the gain of the entire system of the signal processing device 1o to G,
The same operation is performed even if the gain of the first and second transmission circuits 11.16 is 02, and the gain of the third and fourth transmission circuits 19.24 is 1.

Also, the second. The gain of the fourth transmission circuit 16.24 is G7''
1. Even if the gain of the third transmission circuit is set to 1, the same operation is performed.

Note that although n=1 in the above description, n≧2 may also be used. Further, although two systems of memory circuits are used, the same effect can be obtained even if three or more systems are used.

Also, 1st. Second. Third. Fourth memory circuit 13°15
．． 21.23 is analog memory (for example, charge
Charge/transfer/coupled devices, etc.
Each memory circuit has an AD (analog/digital) converter at the input end, a DA (digital/analog) converter at the output end, and the memory consists of a flip-flop circuit, etc. It may also be a digital memory. Also, 1st. The third transmission circuit 11.19 has an AD converter at the input end, and
The memory circuits 13 and 15 of the first, second, . Third.
The fourth transmission circuit 11, 1a, 19.degree. 24 is constituted by a digital filter, and the second. A configuration in which a DA converter is provided after the fourth transmission circuit 16.24 also operates in a similar manner.

Furthermore, an AD converter is provided before input terminal 1, and the first
．． 2nd゜3rd. Fourth memory circuit 13, 15, 21.2
3 is a digital memory composed of a flip-flop circuit, etc.; Second. Third. Fourth transmission circuit 11.
Even if 16, 19, and 24 are configured with non-recursive digital filters or recursive digital filters, and a DA converter is provided after the output terminal 2, the same operation will be achieved.

Furthermore, in the above explanation, the video signal was used as the input signal, so the first. Second. Third. 4th memory circuit 13, 15, 21.23, 1st degree, 2nd degree. Third. Although the operations of the fourth switches 12, 14, and 20° 22 are performed in units of periods based on H, each unit may be set to any time depending on the input signal. Furthermore, in the above explanation, the emphasis circuit was explained as an emphasis circuit, but it may also be used in a circuit for the purpose of giving a preshoot or overshoot, as shown in FIG. On the other hand, although an output signal in reverse time series is obtained, the output signal from the above circuit may be further reversed in time series and converted into an output in the same series as the input signal.

Effects of the Invention As described above, the signal processing device of the present invention can improve transmission by passing a signal through a transmission circuit once in a positive time series, and then passing it through the same transmission circuit in a reverse time series and outputting it. This has the effect of making the phase characteristic of the circuit zero phase, and is particularly useful for video signals.

Also, by performing the time axis reversal process as described above,
At the output terminal 2, a signal whose time axis is completely restored is obtained.

Furthermore, as described above, when the signal processing device of the present invention is used as an emphasis circuit of a frequency modulation/demodulation system,
By adding preshoot and overshoot to the waveform, it is possible to create an emphasis circuit that has the same amount of emphasis as before, but with a significantly lower peak value of the waveform than before, without reducing the amount of emphasis. This has the effect of significantly reducing the frequency deviation width compared to the conventional method.

Alternatively, if the same frequency shift width as before is used, more emphasis than before can be added, and the SN ratio of the reproduced signal can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the signal processing device of the present invention, FIG. 2 is a block diagram explaining the concept used to realize zero-phase characteristics in the present invention, and FIG. 4 is a wiring diagram showing an example of a conventional emphasis circuit, and FIG. 6 is a signal waveform diagram of FIG. 4. 11...first transmission circuit, 12...first switch, 13. ...first memory circuit,
14... Second switch, 15... Second memory circuit, 16... Second transmission circuit, 1
7...First H sync signal detection circuit, 18...
...First control signal generation circuit, 19...
...Third transmission circuit, 20...Third switch, 21...Third memory circuit, 22...
...Fourth switch, 23...Fourth memory circuit, 24...Fourth transmission circuit, 26...
・Second H sync signal detection circuit, 26...second
control signal generation circuit, 30...first signal processing circuit, 4°...second signal processing circuit,
10...Signal processing device. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4 Figure 5

Claims (1)

[Claims] The first signal processing circuit and the second signal processing circuit are configured to be connected in series, and the first signal processing circuit has a first transmission circuit having a transfer function of G1 and a first switch. ,
A first memory circuit, a second switch that operates with a time delay of nH (where n: any positive integer, H: horizontal scanning period) than the first switch, and the same as the first transmission circuit. a second transmission circuit having a transfer function G1 of Further, the second signal processing circuit includes a third transmission circuit having a transfer function G2, and a third signal processing circuit having a transfer function G2.
a switch, a third memory circuit, a fourth switch that operates nH later than the third switch, a fourth memory circuit, and the same transfer function G2 as the third transmission circuit.
a second H-sync signal detection circuit; and a second control signal generation circuit that generates a signal with a (H-a) time delay from the end of the H-sync signal; The signal input to the first signal processing circuit passes through the first transmission circuit and is switched to the first signal by the first switch, which is switched after time a from the end of the H sync signal every nH time. The signal that is sequentially input to the memory circuit and the second memory circuit and written to the first memory circuit over the nH period is, over the next nH period,
The signal is read out in the reverse time sequence to the writing time, and the signal written to the second memory circuit during the nH period of reading from the first memory circuit is read out in the reverse time sequence during the next nH period. is input to the second transmission circuit as one series of signals by the second switch, which is switched nH time later than the first switch, and the switching timing of the first switch and the first memory circuit are and the switching timing between writing and reading of the second memory circuit, and the switching timing of the second switch,
Based on the H sync timing generated by the first H sync detection circuit, the control signal is applied from the first control signal generating circuit at a time a after the end of the H sync every nH time, and The signal input to the second signal processing circuit passes through the third signal processing circuit and then passes through the third signal processing circuit.
The signal is sequentially input to the third memory circuit and the fourth memory circuit by the third switch, which is switched after (H-a) time from the end of the H sync signal every H time, and n
The signal written to the third memory circuit over the H period is read out over the next nH period in a time sequence opposite to the time of writing, and during the nH period of reading from the third memory circuit, the signal is written to the fourth memory circuit. The signals written in the third memory circuit are read out in reverse time series in the next nH period, and
The fourth switch, which is switched nH time later than the switch, is input to the fourth transmission circuit as one series of signals, and the switching timing of the third switch, the third memory circuit, and the fourth The writing and reading switching timing of the memory circuit and the switching timing of the fourth switch are determined based on the H sync timing generated by the second H sync detection circuit.
A signal processing device characterized in that the second control signal generation circuit is configured to provide the control signal from the second control signal generation circuit at (H-a) time after the fall of the H sink every H time.