JPS61182673A - Signal processing device - Google Patents

Abstract

PURPOSE:To compensate in real time a phase characteristic of a transmission channel and to reduce phase change after processing to zero by passing the signals for the nH domain through the transmission circuit of the same transmission characteristics for the normal time and the reverse time. CONSTITUTION:The input signals are supplied through the 1st transmission circuit 11 to a switch SW12 and changed each period H and inputted into the 1st, 2nd memory circuits 13, 15. The signals written in the circuit 13 for the period H are read by the reverse time series corresponding to the write time series during the next period H. Similar writing and reading is performed in the circuit 15 during the period H different from that of the circuit 13. Hence, the addresses produced by an addresser 17 are used in common with the circuits 13, 15. The signals inputted into SW14 are selected after each period H so as to be outputted through the 2nd transmission circuit 16. In such a way, the phase characteristic of the transmission circuit can be reduced to zero phase.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal processing device for processing the frequency characteristics of a signal input to video equipment or the like.

Conventional technology In recent years, new media have been developed for video equipment, and home-use V
TRs, video discs, fiber optic cables, broadcasting satellites, etc. appeared. In order to take advantage of the characteristics of these new media, there is an increasing demand for higher image quality and higher definition for individual video equipment. 2. Description of the Related Art VTRs that record and reproduce video signals have conventionally used a recording method that utilizes frequency modulation and demodulation.

If the noise on the FM transmission line is white noise, demodulation,
The noise added to the signal exhibits so-called triangular noise characteristics, in which the noise level increases as the frequency increases.

In order to reduce this, before frequency modulation, the level of the middle and high range of the input signal is increased (so-called emphasis is applied to increase the frequency deviation width), and after frequency demodulation, the level of the middle and high range of the input signal is increased. Signal processing is performed to lower the level (so-called de-emphasis). However, the band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in frequency deviation width due to the amount of emphasis, which limits the S/N ratio of the reproduced signal. There was a problem. In addition, this problem is V
This is a problem that occurs not only in TR but also in all systems that frequency-modulate and transmit video signals, such as satellite broadcasting, and is an issue that must be solved in order to achieve high image quality and definition. There is.

FIG. 4 is a wiring diagram of a conventional emphasis circuit used in VH8 type VTRs and the like. In FIG. 4, the video signal applied to input terminal 1 is as follows.

The signal is output to the output terminal 6 via the emphasis circuit 6o.

Enf1sis circuit 501j, capacitor (capacitance value c1
) 51, resistance (resistance value Jlb) 52, resistance (resistance value R&
)53. Their values are, for example, C, XRb=1.3 (microseconds), (R& + R
b)/Ra=6.

When a video signal as shown in FIG. 6(e) is input to such a circuit, a signal as shown in FIG. 6(b) is obtained at the output terminal.

Problems to be Solved by the Invention In the case of a VTR, a signal as shown in FIG. 5(b) is frequency-modulated and recorded on a magnetic tape (not shown). In order to limit the frequency band, the signal is clipped at the point indicated by the broken line S in FIG. 6(b), and the signal is frequency-modulated as shown in FIG. 6(c). Alternatively, by changing the constants of each part of the emphasis circuit 60, for example, a signal as shown in FIG. 5(d) is generated and frequency modulated. In the case of Fig. 6(c), there is a problem that waveform distortion occurs, and Fig. 5((i)
), the problem arises that the effect of emphasis becomes W, and the S/N ratio of the reproduced signal decreases by that amount.

In view of the above-mentioned problems, an object of the present invention is to provide a signal processing device that makes it possible to use a larger amount of emphasis than before with the same frequency shift width as before, provided the same FM transmission line is used. It is something.

Alternatively, it is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that of the prior art with the same amount of emphasis as the prior art.

A further object of the present invention is to provide a signal processing device having arbitrary transfer characteristics with preshoot and overshoot. Another object of the present invention is to provide a signal processing device that can compensate for the phase characteristics of a transmission circuit and zero out the phase change of a processed signal in real time.

Means for Solving the Problems In order to solve the above problems, the signal processing device of the present invention includes a first transmission circuit whose transfer function is G.

a first switch, a first memory circuit, a second switch that operates with a time delay of nH (where n: any positive integer, H: horizontal scanning period) than the first switch; a second transmission circuit having the same transfer function G as the first transmission circuit; a second memory circuit; and an addresser that supplies a common address to both the first memory circuit and the second memory circuit. The signal processed by the first transmission circuit is transmitted to the first transmission circuit which is switched every nH time.
A key person is input to the first memory circuit and the second memory circuit by a switch of
The signal written to the second memory circuit is read out over the next nH period in the reverse chronological order to the time of writing, and the signal written to the second memory is read out over the next nH period in the nHH period of reading from the first memory circuit. The nHH period is read out in reverse chronological order, and is input to the second transmission circuit as one series of signals by the second switch, which is switched every nH time, and is processed. The address of the second memory circuit and the address of the second memory circuit are determined by a common addresser, and when the address count increases, the first memory circuit writes and the second memory circuit reads, and when the address count decreases, the first The structure is such that a memory circuit performs reading and a second memory circuit performs writing.

Effect: By adopting the above configuration, the present invention allows a signal in the nH section to pass through a transmission circuit having the same transfer characteristic in the forward time and in the reverse time.

The signal flow is shown in Figure 2. The input signal to the first transmission circuit 61 is x (n), the output signal of the transmission circuit 61 is f (n), the output signal of the first time series inversion circuit 62 is a (n), the output of the transmission circuit e3 The signal is b(n
), and the unit impulse responses of the transmission circuits 61 and 63 are respectively h (n). The two transformations of each signal are expressed as X(z
), F(z), A(Z), B(z).

F (z) = H (z) X (z) Mu (Z) = F (
Z"') = H (Z-') X (Z"") B (z)
= H(z)mu(Z) =H(z)u(z-")x(z-') In other words, 2 of the equivalent in/4 Luss response of the entire system in Figure 2
Letting the transformation be Heq(z), Heq(z-'
) = B(z) / X(z-”) = H(z-
') becomes H(z). However, the output signal of the system shown in FIG. 2 has a time series that is opposite to the time series of the input signal. If a signal is obtained in the same time series as the input signal, a time series inversion circuit may be connected to the output end of the system shown in FIG.

Expressing the equivalent impulse response of the system in Figure 6 using Fourier transform, Heq(e”) = l H(6”)! 2, and the phase change is zero. This zero-phase characteristic is desirable in video signal processing, and can be achieved with the circuit configuration shown in FIG. 2. Further, the gain of the system shown in FIG. 2 is the square of the gain in the case of one stage of transmission circuit. Therefore, if the required gain is G, the gain of one stage of the transmission circuit of the system shown in FIG. 6 must be 02.

When the system shown in FIG. 2 is used as an emphasis circuit, when a signal as shown in FIG. 3e) is inputted, a signal as shown in FIG. 3(d) is obtained.

The signal in FIG. 3(d) has a waveform with preshoot and overshoot, so even though the amount of emphasis is the same as the conventional example shown in FIG. 4, its peak value is as shown by the broken line S. A waveform with low υ is obtained.

Embodiment An embodiment of the signal processing circuit of the present invention will be described below. FIG. 1 is a block diagram of a signal processing device 1o of the present invention. In order to explain an emphasis circuit as an example of the signal processing device 1o, the signal processing device 10 will be hereinafter referred to as an emphasis circuit 10. Now, consider the case where the signal shown in FIG. 3 (2L) is input to input terminal 1.

Here, the following explanation will be given assuming %n=1.

A signal input to the input terminal 1 is input to the first switch 12 via the first transmission circuit 11 .

The output signal of the first transmission circuit 11 is as shown in FIG. 3('b). The signal input to the first switch 12 is H
The first memory circuit 13 and the second memory circuit are switched at each time.
It is input to the memory circuit 16 of. First memory circuit 13
The signal written over the next H period is read out in reverse chronological order with respect to the writing time sequence over the next H period and input to the second switch 14 . First memory circuit 13
The signals written in the second memory circuit 16 during the H period in which the signals are being read from are read out in reverse chronological order over the next H period and input to the second switch 14 .

Here, writing to the first memory circuit 13 and reading from the second memory circuit 16, and reading from the first memory circuit 13 and writing to the second memory circuit 16 are performed simultaneously. Therefore, the first memory circuit 13 and the second memory circuit 16 share the address generated by the addresser 17. That is, writing to the first memory circuit 13 and reading from the second memory circuit 16 are performed when the address count of the addresser 17 is rising (or falling), and when the address count of the addresser 17 is falling (or rising), the first memory circuit 13 is written and the second memory circuit 16 is read. The first memory circuit 13 is read and the second memory circuit 15 is written. The signal input to the second switch 14 is selected at every H time, and the signal input to the second switch 14 is selected at every H time.
It is output as a series of signals as shown in Figure (0). Second
The signal output through the transmission circuit appears at the output terminal 2 with a waveform as shown in FIG. 3(d).

Note that in the above description, n=1, but yl>2 may also be used. Further, although two systems of memory circuits are used, the same effect can be obtained even if three or more systems are used.

Also, 1st. The second memory circuit 13.15 can be realized with an analog memory (for example, a charge transfer device such as a charge coupled device), but with an AD (Analog-to-Digital) converter at the input end of each memory circuit. DA (digital-analog) at the output end
It has a converter, and the memory may be a digital memory composed of a flip-flop circuit or the like.

Further, an AD converter is provided before the input end of the first switch 12. The second memory circuit 1316 is a digital memory composed of a flip-flop circuit or the like, and the first. A similar operation can be achieved even if the second transmission circuit 1116 is configured with a digital filter and a DMU converter is provided after the second transmission circuit 16. Furthermore, an AD converter is provided before the input terminal 1, and the first . Second memory circuit 131
5 is a digital memory composed of a flip-flop circuit, etc.; Even if the second transmission circuit 1116 is configured with a non-recursive digital filter or a recursive digital filter, and a DM converter is provided after the output terminal 2, the same operation is achieved.

Furthermore, in the above explanation, the video signal was used as the input signal, so the first. Second memory circuit 13.16%
1st. Although the second switches 12 and 14 operate in units of periods based on H, these units may be set to any time depending on the input signal. Also, in the above explanation, it was explained as an emphasis circuit, but the third
As shown in Figure (1), it may be used in a circuit for the purpose of providing preshoot or overshoot.Also,
In the above explanation, an output signal in reverse time series is obtained with respect to the input signal, but it is also possible to further reverse the time series of the output signal from the above circuit and convert it into an output in the same series as the input signal. do not have.

Effects of the Invention As described above, the signal processing device of the present invention can improve transmission by passing a signal through a transmission circuit once in a positive time series, and then passing it through the same transmission circuit in a reverse time series and outputting it. This has the effect of making the phase characteristic of the circuit zero phase, and is particularly useful for video signals.

・Also, 1st. For the second memory circuit 13.15,
Since a common address outputted from one addresser 17 is used, it has the advantage of simplifying the circuit configuration.

Furthermore, as described above, when the signal processing device of the present invention is used as an emphasis circuit of a frequency modulation/demodulation system,
By adding preshoot and overshoot to the waveform, it is possible to create an emphasis circuit that has the same amount of emphasis as before, but with a waveform peak value that is significantly lower than before, without reducing the amount of emphasis. The effect of significantly lowering the frequency deviation width than before can be seen. Or, if we use the same frequency deviation width as before,
It is possible to add more emphasis than conventionally, and it is possible to improve the S/N ratio of the reproduced signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the signal processing device of the present invention, and FIG. 2 is a block diagram illustrating the concept used to realize zero-phase characteristics in the present invention. Signal waveform diagram FIG. 4 is a wiring diagram showing an example of a conventional emphasis circuit. FIG. 5 is a signal waveform diagram of FIG. 4. 11...First transmission circuit, 12...First switch %13...First memory circuit 1
4. Old... second switch, 16... second memory circuit, 16... second transmission circuit, 10...
...Signal processing device. Name of agent: Patent attorney Toshio Nakao and one other person #!
Figure 3

Claims (1)

[Claims] A first transmission circuit whose transfer function is G, a first switch, a first memory circuit, and a transfer function of nH from the first switch.
(where n: any positive integer, H: horizontal scanning period); a second switch that operates with a time delay; a second transmission circuit having the same transfer function G as the first transmission circuit; 2
and an addresser that supplies a common address to both the first memory circuit and the second memory circuit, and the signal processed by the first transmission circuit is transmitted every nH time. A signal that is sequentially input to the first memory circuit and the second memory circuit by the first switch that is switched and written to the first memory circuit over an nH period is not input during writing over the next nH period. The signals written in the second memory during the nH period of reading from the first memory circuit are read out in the reverse time sequence during the next nH period, and the signals are read out in the reverse time series at every nH time. The second switch is configured to input one series of signals to the second transmission circuit and process them, and the address of the first memory circuit and the address of the second memory circuit are common. The first memory circuit writes and the second memory circuit reads when the address count increases, and the first memory circuit reads and the second memory circuit writes when the address count decreases. A signal processing device characterized by: