JPS60235533A - Signal processing unit - Google Patents

Abstract

PURPOSE:To use an emphasis amount more than conventional amounts by passing a signal once through a transmission circuit in a positive time series and outputting the signal through the same transmission circuit in the opposite time series next to bring the phase characteristic of the transmission circuit to zero phase. CONSTITUTION:The period of an input signal to be processed in this unit covers an (nH+alpha+beta) period from a time alpha to a time beta before nH period and the input signal passes twice through the 1st, 2nd and 3rd transmission circuits 6, 7, 8. The time series is the positive time series when the 1st input signal passes and a negative time series at the 2nd passing. When the signal of the same time series as the time series of the input signal is desired to be obtained, a time series inverting circuit has only to be connected to the output terminal of the system in the figure. It is difficult to realize a complete zero phase depending on the difference of the characteristic between transmission circuit 61 and 62 through the constitution in the figure, but the signal passes twice through the same circuit, the phase characteristic of the transmission circuit is cancelled and the zero phase is realized accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device that processes the frequency characteristics of an input signal such as a video signal.

Conventional configuration and its problems In video tape recorders (hereinafter referred to as VTRs) that record and reproduce video signals, in the frequency modulation and demodulation system, if the noise in the FM transmission line is white noise, then
The noise level added to the demodulated signal increases as the frequency increases. It exhibits so-called triangular noise characteristics. In order to reduce this, before frequency modulation, the level of the middle and high range of the input signal is increased (so-called emphasis is applied to increase the frequency deviation width), and after frequency demodulation, the level of the middle and high range of the input signal is increased. Signal processing is performed to lower the level (so-called de-emphasis). However, F.M.
The band of the transmission path is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in the frequency deviation width due to the amount of emphasis, and as a result, the SN of the reproduced signal
There was a problem that the ratio was limited. Incidentally, this problem occurs not only in VTRs but also in all systems that frequency-modulate and transmit video signals, such as satellite broadcasting.

Figure 1 is a wiring diagram of a conventional emphasis circuit used in Vf (S type VTRs, etc.). In Figure 1,
A video signal applied to the input terminal 1 is outputted to the output terminal 6 via an emphasis circuit 60. The emphasis circuit 6o includes a capacitor (capacitance value C1) 51, a resistor (resistance value Rh) s2, and a resistor (resistance value Ra) 63. Their values are, for example, C1xRb = 1.3 p sec, (Ra + R1)
) / Ra=5.

When a video signal as shown in Fig. 2) is input to such a circuit, a signal as shown in Fig. 2(b) is obtained at the output terminal.

In the case of a VTR, the signal shown in Figure 2(b) is frequency-modulated and recorded on a magnetic tape (not shown), but there is a limit to the frequency band of the electromagnetic conversion system that is the FM transmission line. , the signal is clipped at the point indicated by the broken line S in FIG. 2(b), and the signal is frequency-modulated as shown in FIG. 2(c). Alternatively, the constants of each part of the emphasis circuit 6o may be changed, for example, the emphasis amount<-Rp;, ft
By setting a2) to an apricot, a signal as shown in FIG. 2(d) is generated and frequency modulated. In the case of Fig. 2(c), there is a problem of waveform distortion;
In the case of d), the effect of the emphasis becomes i, and there is a problem that the S/N ratio of the reproduced signal decreases by that amount.

OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems and
If it is a transmission line, with the same frequency deviation width as before,
It is an object of the present invention to provide a signal processing device that can use an amount of emphasis greater than that of the conventional art. or,
It is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that of the prior art with the same amount of emphasis as the conventional one. A further object of the present invention is to provide a signal processing device having arbitrary transfer characteristics with preshoot and overshoot. Also,
It is an object of the present invention to provide a signal processing device capable of compensating the phase characteristics of a transmission circuit and zeroing out the phase change of a processed signal in real time.

Configuration of the Invention The signal processing device of the present invention includes a first switch, a first transmission circuit having a transfer function of G, a first memory circuit, and a signal processing device that is connected to the first switch by nH (where n: arbitrary). a second switch that operates with a time delay (H: horizontal scanning period), a second transmission circuit having the same transfer function G as the first transmission circuit, and a second memory circuit; a third switch that operates 2 nH later than the first switch; a third transmission circuit having the same transfer function G as the first transmission circuit; a third memory circuit; and a fourth switch. and the first. Second. The third memory circuit stores (nH
+α+β) period, and the next (n
The input signal is configured to be output in reverse time series over a period of f(+a+β), the first switch is connected to the input terminal side for a period of (nH+α+β), and the input signal is In the first (nH+α+β) period, it is stored in the first memory circuit via the first transmission circuit, and in the next (nH+a+β) period, it is read out from the first memory circuit in reverse time series, A signal that passes through the first switch, is input to the fourth switch, and is delayed by nH time from the signal from the first memory circuit is read out from the second memory circuit and is input to the fourth switch. 2. from the signal from the first memory circuit. The signal delayed by nH time is read out from the third memory circuit and input to the fourth switch, and the signal delayed by the first . Second. The output signal of the third memory circuit is configured to be switched by a fourth switch every nH period and output as one series of signals.

DESCRIPTION OF THE EMBODIMENTS The present invention will be described below based on the illustrated embodiments. FIG. 3 shows a block diagram of a signal processing device 34 of the present invention.

Note that since an emphasis circuit will be described here as an example of the signal processing device 34, the signal processing device 34 will be referred to as an emphasis circuit 34 hereinafter. Now, consider the case where the signal shown in FIG. 4 0) is input to the input terminal 1. Now, if n = 1, the signal that passes through the first transmission circuit 6 through the first switch 3, which is closed for (nH + α + β) period and then opened for the next (7) (2n H - α - β) period, is as follows.
The result will be as shown in FIG. 4(b). Through a second switch 4 which operates with a delay of nH wait time from the first switch 3,
The signal passing through the second transmission circuit 7 becomes as shown in FIG.
A signal like that shown in FIG. 4, which is delayed by 2 nH from b), is output. The signal of FIG. 4(b) is stored in the first memory circuit 9 for a period of (n)(+α+β), and the signal of FIG.
The signal is output over a period of nH+a1β) in a time series opposite to that when it was stored, resulting in a waveform as shown in FIG. 4 (-). Similarly, the second memory circuit 1o and the third memory circuit 11 output signals as shown in FIG. 4(f) and (cr), respectively.

The signals in FIGS. 4(e) and 4(f) r(q) are the signals of the first. Second. When passing through the third transmission circuits 6, 7.8, the waveforms are as shown in FIG. 4(h) and (Il'(7)). When output as one series of signals, one series of signals having a bristle overshoot appears at the output terminal 2, as shown in FIG. 4(k).

Here, the feature of the present invention is that the period of the input signal to be processed is n
This is a point that spans a period (nH+a+β) from time α before the H period to time β after the H period, and a point where the input signal passes through the first, second, and third transmission circuits 6, 7.9 twice.

When the input signal passes through the input signal for the first time, it becomes a positive time series, and when it passes through the input signal for the second time, it becomes a negative time series. Therefore, the signal flow is shown in FIG. 5. The input signal to the first transmission circuit 61 is x(n), and the output signal of the transmission circuit 61 is f(n)
), the output signal of the first time series reversal circuit 62 as a(n),
Let the output signal of the transmission circuit 63 be b (n), and the transmission circuit 6
Let each unit impulse response of 1.63 be h (n). The two transformations of each signal are X(z) and F(z)
, A(z), B(z), then F(z)
= H(z)
)=H(z-1)X(z')B(z)-I
I (z) A (z)-H(z) H(z-') X
(z-') That is, if the Z transformation of the equivalent impulse response of the entire system in Fig. 5 is Heq(z""), then Heq(
z=) = B(z)/X (z-') -H(z-
')f((z).However, the output signal of the system in Figure 5 has a time series that is opposite to the time series of the input signal.We want to obtain a signal that is in the same time series as the time series of the input signal. In this case, a time series reversal circuit may be connected to the output end of the system shown in FIG.

When the equivalent impulse response of the system in Figure 6 is expressed by Fourier transform, Heq(e''') = If ((e''') I2, and the phase change is zero. This zero phase characteristic is used in video signal processing. This is desirable, and can be achieved with the circuit configuration shown in FIG. 3. In particular, with the configuration shown in FIG. Although it is difficult, in Figure 3, the signal passes through the same circuit twice, so the phase characteristics of the transmission circuit are canceled out, and zero phase can be achieved accurately.Also, the gain of the system in Figure 6 is determined by the transmission circuit. The first stage is L7''19. Therefore, if the required gain is G, the gain of the first stage of the transmission circuit of the system shown in FIG. 6 must be small. 1st. 2nd.
Third transmission circuit 6. 8 is an emphasis circuit 3° as shown in FIG. The emphasis circuit 30 includes a capacitor (capacitance value C2) 31, a resistor (resistance value Re) 32,
It is composed of a resistor (resistance value Rd) s3. These values indicate that the same signal is the first. Second. Third transmission circuit 6.7.8
Since it passes through twice, the amount of emphasis is squared as described above. Therefore, in contrast to the conventional example shown in FIG. 1 where Rc+Rd is set, -Rd-=6 is set. As a result of the emphasis, a signal as shown in Fig. 4 (-) is input to the first switch 3, and after signal processing, when it reaches the fourth switch 12, a signal as shown in Fig. 4 (h) is input. becomes. The signal in Figure 4 (h) has a waveform with preshoot and overshoot, so even though the amount of emphasis is the same as the conventional example shown in Figure 1, its peak value is lower than the broken line S. A waveform is obtained. However, in the waveform of FIG. 4(g)), unnecessary waveform changes appear in the pre-β period and the post-α period of the β period. This separates the continuous signal into
This is to perform emphasis processing as a signal of the (nH+α+β) period, and by switching the fourth switch 12 so as to remove the β period before and the α period after the nβ period and extract only the signal of the nβ period. A signal as shown in Figure 4 (g)) can be obtained.

Note that although n=1 in the above description, n≧2 may also be used. Further, although three transmission circuit systems are used, the same effect can be obtained even if four or more transmission circuits are used.

Also, 1st. Second. The third memory circuit 9, 10゜11 is an analog memory (for example, charge coupled memory).
A charge transfer device such as a device, etc.) is used, but an AD (analog
The memory may be a digital memory composed of a flip-flop circuit or the like. Also, 1st. Second. Third switch 3,4゜6
has an AD converter before the input end of the first. 2nd, 3rd
The memory circuits 9, 10, and 11 of the memory circuits 9, 10, and 11 are digital memories constituted by flip-flop circuits, etc. Second. Even if the third transmission circuits 6, 7.8 are configured with digital filters and a DA converter is provided after the fourth switch 12, the same operation is achieved. Furthermore, an AD converter is provided before the input terminal 1, and the first . Second. Third memory circuit 9
゜10.11 is a digital memory composed of a flip-flop circuit, etc., and the first. Second. Third transmission circuit 6
, 7.8 may be configured with non-recursive digital filters or recursive digital filters, and a DA converter may be provided after the output terminal 6, and the same operation will be achieved.

Furthermore, in the above explanation, the video signal was used as the input signal, so the first. Second. Third memory circuit 9,1
0.11 or 1st. Second. 3rd and 4th switch 3
, 4, and 5.12 are all based on periods based on H, such as H and H+a+β, but depending on the input signal, these units may be set to any time. In the explanation, it has been explained as an emphasis circuit, but it may also be used in a circuit for the purpose of providing preshoot or overshoot, as shown in FIG. 4(k). Furthermore, in the above explanation, an output signal in reverse time series is obtained with respect to the input signal, but it is also possible to further reverse the time series of the output signal from the above circuit and convert it into an output in the same series as the input signal. do not have.

Effects of the Invention As described above, the signal processing device of the present invention can improve transmission by passing a signal through a transmission circuit once in a positive time series, and then passing it through the same transmission circuit in a reverse time series and outputting it. This has the effect of making the phase characteristic of the circuit zero phase, and is particularly useful for video signals.

In addition, when processing continuous signals in sections, processing is performed for the period (nH + α + β) from time a before the nβ period to time β after the nβ period, so the β period and β period near the discontinuous part of the signal are avoided and output. This eliminates unnecessary waveform changes to the output signal.

Furthermore, by performing the above processing in three series, it is possible to perform the task of dividing a continuous signal into segmented signals, processing them, and then outputting them again as continuous signals in real time.

Furthermore, as described above, when the signal processing device of the present invention is used as an emphasis circuit of a frequency modulation/demodulation system,
By adding preshoot and overshoot to the waveform, it is possible to realize an emphasis circuit that has the same amount of emphasis as the conventional one, and the peak value of the waveform is significantly lower than the conventional one, without reducing the amount of emphasis. This has the effect of significantly reducing the frequency deviation width compared to the conventional method. Or, if we use the same frequency deviation width as before,
It is possible to add more emphasis than before and improve the reproduced signal.

[Brief explanation of the drawing]

Figure 1 is a wiring diagram showing an example of a conventional emphasis circuit.
FIG. 2 is a signal waveform diagram of FIG. 1, FIG. 3 is a block diagram of main parts showing an example of the signal processing device of the present invention, FIG. 4 is a signal waveform diagram of each part of FIG. A block diagram illustrating the concept used to realize zero-phase characteristics in the present invention,
FIG. 6 is a wiring diagram showing an example of an emphasis circuit used in the present invention. 3...First switch, 4...Second switch, 6...Third switch, 6...
・First transmission circuit, 7...Second transmission circuit, 8
...Third transmission circuit, 9...First memory circuit, 1o...Second memory circuit, 11.
...Third memory circuit, 12...Fourth switch, 34... Signal processing device. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 1. = Figure 4 Figure 4

Claims (1)

[Claims] a first switch, a first transmission circuit whose transfer function is G, a first memory circuit, and a nH
(where n: any positive integer, H: horizontal scanning period); a second switch that operates with a time delay; a second transmission circuit having the same transfer function G as the first transmission circuit; 2
a third switch that operates 2 nH later than the first switch, a third transmission circuit having the same transfer function G as the first transmission circuit, and a third memory circuit. , a fourth switch, and the first switch. Second. The third memory circuit sequentially inputs signals over a period of (nH+a+β) from time α before to time β after each nH period, and reverses the input signal over the next (nH+a+β) period. The first switch is configured to output in time series, and the first switch is configured to output (nH+
α+β) period input terminal side, and the input signal is stored in the first memory circuit via the first transmission circuit in the first (nH+a+β) period, and then during the next (nH+a+a) period.
+β) period, the signal is read out from the first memory circuit in reverse time series, passes through the first switch, is input to the fourth switch, and similarly, the signal from the first memory circuit A signal delayed by 2nH time from the signal from the first memory circuit is read out from the second memory circuit and input to the fourth switch, and a signal delayed by 2nH time from the signal from the first memory circuit is read out from the third memory circuit. input to the fourth switch; Second. A signal processing device characterized in that the output signal of the third memory circuit is configured to be switched by a fourth switch every nH period and output as one series of signals.