JPS59221126A - Signal processng device - Google Patents

Abstract

PURPOSE:To lower the peak value of waveform without decreasing amount of emphasis by providing a pre-shoot and an overshoot to the waveform when a signal processing device is used for an emphasis circuit of the frequency modulator demodulator system. CONSTITUTION:A video signal applied to a signal processing circuit 3 is inputted to the 1st and 2nd memory circuits 9, 10 at each 1H by the 1st switch 8, a continuous signal having inverse time series to that of an input signal is extracted by the 2nd switch circuit 11 and applied to the 3rd switch 14 via the 2nd transmission line 12 having the same transfer function as that of the 1st transmission line 7. This signal is switched at each 1H by a switch 14, inputted to the 3rd and 4th memory circuits 19, 20, where the signal is switched at each 1H by the 4th switch 21, converted into a continuous signal and applied to an adder circuit 4. The adder circuit 4 adds a waveform (e) of the 1st transmission line 7 and an output waveform (h) from the switch 21, and the result is divided to 1/2 and a waveform (i) is obtained.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a signal processing device that converts signals such as video values into signals having desired frequency characteristics, and is applicable to video tape recorders, satellite broadcasting, etc. It is useful for use in transmission systems.

Conventional configurations and their problems In video tape recorders and the like that record and reproduce video signals, a frequency modulation recording method is common. In a frequency modulation/demodulation system, if the noise on the FM transmission line is white noise, the noise added to the demodulated signal exhibits so-called triangular noise characteristics, in which the noise level increases as the frequency increases. In order to reduce this, before frequency modulation, the level of the middle and high range of the input signal is increased (by applying an emphasis to increase the frequency deviation width), and after frequency demodulation, the level of the middle and high range of the input signal is increased. It performs processing that lowers the level of high frequencies (so-called de-emphasis). However, since the band of the FM transmission path is limited by the electromagnetic conversion system, there is a limit to the increase in frequency deviation width depending on the amount of emphasis, which limits the S/N ratio of the reproduced signal. was there.

Note that this problem is not limited to video tape recorders.
This problem occurs in all systems that transmit video signals using frequency modulation 1 to 1, such as satellite broadcasting.

Purpose of the Invention The present invention C solves the above-mentioned conventional problems and
It is an object of the present invention to provide a signal processing device that can use a larger amount of emphasis than the conventional one with the same frequency shift width as the conventional one if the M transmission line is used.

Alternatively, it is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that in the conventional art with the same amount of emphasis as in the conventional art.

A further object of the present invention is to provide a signal processing device having arbitrary transfer characteristics including a print and an overpass.

[Structure of the Invention] - In order to achieve the object described above, the present invention provides a first signal processing circuit and a second signal processing circuit whose input signals are manually input, and which adds the output values of these signal processing circuits. The first signal processing circuit has a configuration in which a 4XT time delay line and a first transmission circuit whose transfer function is G are connected in series, and a second signal processing The circuit includes a first switch, a first memory circuit, a second memory circuit,
a second switch, a second transmission circuit having the same transfer function G as the first transmission circuit, a third switch, a third memory circuit, a fourth memory circuit, and a fourth transmission circuit; the first switch; Second. 3. Each of the fourth memory circuits is a memory circuit configured to input a signal to Illα over a time T, and output the input signal in reverse time series over the next time T. , the signal input to the second signal processing circuit is switched by the first switch 97 times every hour and is alternately input to the first memory circuit and the second memory circuit,
The output values of these first and second memory circuits +ju are switched by the second switch in an opposite phase to the switching of the first switch, converted into one series of signals, and then converted into one series of signals. Via a transmission circuit, the signal is switched by f and 7J every hour by the third switch circuit, and is alternately input to the third memory circuit and the fourth memory circuit,
The output signals of these third and fourth memory circuits are switched by the fourth switch in a phase opposite to the switching of the third switch, and the output signals converted into one series of signals are converted into one series of signals. This circuit is configured to borrow the output of the second signal processing circuit.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. The explanation will be given using an emphasis circuit used in a video tape recorder ("/TR) as an example of a signal processing circuit. Figure 1 shows a conventional emphasis circuit used in a VH3 type VTR, etc. Yes. 1st
In the figure, a video signal applied to an input terminal 1 is outputted to an output terminal 5 via an emphasis circuit 50. Emphasis circuit 60 includes a capacitor (capacitance value CI) e; 1° resistance (ill; resistance value Rb) s2. Resistance (resistance value RIL)
It consists of 53. Their values are, for example, Cl
X Rb = 1.3, czselc, u=
It is set to 6.

a There is.

When a video signal as shown in FIG. 2 (2L) is input to the input terminal 1 of such a circuit, the second
A signal as shown in Figure (b) is obtained. In the case of a video tape recorder, the signal shown in Figure 2 (1) is frequency modulated and recorded on a magnetic tape (not shown).
Since the frequency band of the electromagnetic conversion system, which is the FM transmission line, is limited, the signal is clipped at the point indicated by the broken line S in Figure 2(b), making the signal as shown in Figure 2(C). Frequency modulation. Alternatively, by changing the constants of each part of the emphasis circuit 50 and setting the emphasis amount (=Ra) to 7, for example, frequency modulation is performed to a signal as shown in FIG. 2 ((1). In the case of Fig. 2 (C), there is a problem that waveform distortion occurs, and in the case of Fig. 2 (d), the emphasis effect is 7, and the S/N ratio of the J raw signal decreases by that amount. There is a problem with doing so.

FIG. 3 shows an emphasis circuit using an example of the signal 6 processing device of the present invention. In FIG. 3, the video value applied to the input terminal 1 is applied to the first trust processing circuit 2 and the second signal processing circuit 3, and the output signals of these are added by the addition circuit 4. After that, it is output to the output terminal 5 (in order to adjust the output level, the adder circuit 4 includes a function of setting the addition result to 7). The signal input to the first signal processing circuit 2 is delayed by 4H through a 4H delay line (H indicates 1 horizontal scan) 6, and the signal is transmitted to the first transmission circuit 7 whose transfer function is G. supplied to The first transmission circuit 7 is an emphasis circuit 22 as shown in FIG. The emphasis circuit 22 is a capacitor (capacitance value 02)
23. Resistance (resistance value Re) 24°Resistance (resistance value R4) 2
It consists of s. These values are set to, for example, the same value Rc4-Rd= as in the conventional example shown in FIG.

R(1) When a video signal as shown in FIG. 2(a) is input to such a circuit, signals f and lJ as shown in FIG. 2 (tel) are outputted to the output terminal 5.

On the other hand, a signal whose level is inverted every 1H is applied to the C0NT terminal 16 of the second signal processing circuit 3. This signal can be obtained, for example, by inputting a horizontal synchronizing signal whose size is equal to the input video value to a Frisogge flop circuit (not shown).

In this way, the signal supplied to the C0NT terminal 15 is 2
Divided into series. One series has a first switch 80
Control terminal 26 and control terminal 28 of first memory circuit 9
and is inverted by the inverter 17 and supplied to the control terminal 27 of the second switch 11 and the control terminal 29 of the second memory circuit 100. The other series is
For example, the control terminal 30 of the third switch 14 is
The signal is supplied to the control terminal 32 of the third memory circuit 19, inverted by the inverter 22, and supplied to the control terminal 31 of the fourth switch 21 and the control terminal 33 of the fourth memory circuit 20. Note that the JM delay circuit 18 is set to match the delay time of the second transmission circuit 12, which will be described later.

Here, the video signal applied to the second signal processing circuit 3 is processed by the first switch 8 for one horizontal scanning period; (1H4
σ) and is input to the first memory circuit 9 and the second memory circuit 10 at 1H4. The first memory circuit 9 and the second memory circuit 10u are composed of analog memories, for example, and have a storage capacity of 1l-1:1H. The control signal applied to the control terminals 28°29 is H.
When the control signal is at the L level, the memory circuits 9 and 1o sequentially store the input signals, and when the control signal applied to the control terminals 28 and 29 is at the L level, the memory circuits 9 and 1o store the input signals in sequence. It outputs a time series that is the opposite of the stored time series. In addition, the movable piece of the switch 8 is connected to the control terminal 26
When the control signal applied to is at H level, it is pushed toward the first memory circuit 9 side, and when it is at L level, it is pushed toward the second memory circuit 10 side.

The output waveform of the first memory circuit 9 is as shown in FIG.
As shown in f, for the input waveform [Fig. 2(a)],
It has a reverse time series with H as the funeral position. The output signal of the first memory circuit and the output signal of the second memory circuit are applied to the second switch 11. The movable piece of the second switch 11 is connected to the output terminal of the first memory circuit 9 when the control value applied to the control terminal 27 is at H level, and is connected to the output terminal of the first memory circuit 9 when the control value is at L level. Connected to the output terminal.

As a result, the output terminal of the second switch circuit 11 has 1
Continuous values whose time series is opposite to that of the input signal are recorded in units of H. This signal whose time series is reversed is supplied to the third switch 14 via the first transmission circuit 7 and the second transmission circuit 12 having the same transfer function G. Third switch 14
The input signal waveform of is shown in FIG. 2(g). This signal is switched every 1H by the third switch 14 and is input to the third memory circuit 19 and the fourth memory circuit 20.

Output signals from the third memory circuit 19 and the fourth memory circuit 20! 3 is switched every 1H by the fourth switch 21, converted into a continuous signal, and supplied to the adder circuit 4 as an output signal of the second signal processing circuit. The third memory circuit 19 and the fourth memory circuit 2Q have the same circuit configuration as the first memory circuit 9 or 10, and when the control signals applied to the control terminals 32 and 33 are at H level,
-1- The memory circuits 19 and 20 sequentially store the inputted beliefs, and when the control values applied to the control terminals 32 and 33 are at L level, the memory circuits 19 and 20
outputs a time series that is opposite to the stored time series.

Unfortunately, when the control signals applied to the control terminals 30 and 31 are at H level, the movable pieces of the third switch 14 and the fourth switch 21 are pushed to the third memory circuit 19 side, and when the control signals are at L level, they are pushed to the third memory circuit 19 side. is tilted toward the fourth memory circuit 20 side.

The waveform of the signal output to the fourth switch 21 after undergoing such signal processing is shown in FIG. 2(h).

As mentioned above, the adder circuit 4 adds the waveform shown in FIG. 2(6) and the waveform shown in FIG. 2(h), and the output terminal 6 has a second A waveform as shown in Figure (1) is obtained.

The waveform shown in Fig. 2 (1) has a preshoot, an oversight, and -1. Therefore, although the amount of emphasis is the same as the conventional example shown in Fig. 1, its peak value is A waveform lower than the broken line S is obtained.

In addition, in the above explanation, the first. Second. The third and fourth memory circuits 9, 10, 19.20 are analog memories ('
For example, it is a charge transfer device such as a charge coupled device), but each memory circuit has an A/D converter at the input end and a D/D converter at the output end.
It has an A converter, and the memory may be a digital memory composed of a flip-flop circuit or the like. Further, an A/D converter is provided before the input end of the first switch 8, and the first switch 8 has an A/D converter before the input end of the first switch 8. Second. Third. Fourth memory circuit 9°IQ, 1
9.20 is a digital memory made up of a flip-flop circuit, etc., the second transmission circuit 12 is made up of a digital filter, and after the output end of the fourth switch 21, a D
A configuration including a /A converter also operates in a similar manner.

Furthermore, it has an A/11: converter before input terminal 1, and 4J! The fl line extension 6 is configured with a digital memory, and the first
．． Second. Third. Fourth memory circuit 9,10°19.20
The first transmission circuit 12 and the second transmission circuit 12 are constructed of a non-recursible digital filter or a recursible digital filter, and the output terminal 5 is A configuration including a D/A converter also operates in a similar manner.

In addition, in the two consecutive explanations, the video signal was used as the input value, so the 4H delay line 6. 1st゜2nd. Third
．． Fourth memory circuit 9, 10, 19°20 or 1l-
Although all the signals applied to the iCONT terminal are expressed in units of H, these units may be set to any time depending on the human signals.

In the above explanation, it was explained as an emphasis, but as shown in Figure 2 (h), it is a pudding 1.
, it may be used in a circuit for the purpose of providing an oversheet.

"Effects of the Invention" As mentioned above, the signal processing device of the present invention has a transmission characteristic G of the first transmission circuit (corresponding to 7 in the above-mentioned embodiment) and the second transmission circuit (corresponding to 12 in the same embodiment). By choosing arbitrarily, a trust processing device having arbitrary transmission characteristics with precoat and oversheet can be obtained.

'' As mentioned above, when the signal processing device of the present invention is used as an emphasis circuit in a frequency modulation/demodulation system, the same amount of emphasis as in the conventional method can be achieved by making the waveform have purinet and overshoot. It is possible to realize an emphasis circuit in which the peak value of the waveform is significantly lower than before, and the frequency deviation width can be significantly lowered than before without reducing the amount of emphasis. .

Alternatively, if the same frequency deviation width as the conventional method is used, it is possible to add more emphasis than the conventional method, and it is possible to obtain the effect that the S/N ratio of the generated signal can be improved.

[Brief explanation of drawings]

Figure 1 is a wiring diagram showing an example of a conventional emphasis circuit.
Fig. 2 is a signal waveform diagram, Fig. 3 is a schematic block diagram showing an example of the trust processing device of the present invention, and Fig. 4 is a wiring diagram showing an example of the circuit configuration of the first transmission circuit in Fig. 3. It is. 2...First signal processing circuit, 3...Second
Borrow processing circuit, 4... Addition circuit, 6...
・4H delay line, 7...first transmission circuit, 8...
...First switch, 9...First memory circuit, 1o...Second memory circuit, 11...
Second switch, 12...Second transmission circuit, 1
4... Third switch, 19... Third memory circuit, 20... Fourth memory circuit, 21
...Fourth switch. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure ``'-'1) Figure 2

Claims (2)

[Claims] (1) A first signal processing circuit and a second signal processing circuit to which input signals are respectively input;
The first signal processing circuit includes a series connection circuit of a 4XT time delay line and a first transmission circuit whose transfer function is G. The second signal processing circuit includes a first switch, a first memory circuit, a second memory circuit, a second switch, and a transfer function G that is the same as that of the first transmission circuit. a second transmission circuit having a second transmission circuit, a third switch, a third memory circuit, a fourth memory circuit, and a fourth switch; Second. Third. Each of the fourth memory circuits is configured to sequentially input signals over a period of time T, output the inputted signals in reverse time sequence over the next period of time, and output the inputted signals in reverse time sequence, and the second signal The signal input to the processing circuit is switched every 7 hours by the first switch, and is input to the first memory circuit and the second memory circuit, and the signal is input to the first and second memory circuits. The output signal of the memory circuit is outputted by the second switch in an opposite phase to the switching of the first switch.
After being converted into one series of signals, the signals are passed through the second transmission circuit, and then switched every 7 hours by the third switch circuit to the third memory circuit and the fourth memory circuit. and the outputs of the third and fourth memory circuits are switched by 9 times by the fourth switch in an opposite phase to the switching of the third switch and converted into one series of signals. 1. A signal processing device characterized in that the signal processing device is configured to use the signal as an output signal of a second trust processing circuit. (2) The input (L+) is the video signal, the delay time 4XN of the delay line is 4XH (however, H is the horizontal scanning period), and each of the 1st, 2nd, 3rd, and 4th memory circuits Scope (1) of the Patent Claims is characterized in that the system is configured to sequentially input signals over 1H time, and output the input signals in reverse time sequence over the next 1H time. The credit processing device described in Section 1.