JP2535262B2 - Pre-emphasis circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video emphasis circuit during VTR or FM transmission by digital signal processing, and more particularly to suppressing waveform deterioration after de-emphasis due to clipping of video data after emphasis. The present invention relates to a pre-emphasis circuit to be obtained.

[0002]

2. Description of the Related Art When a video signal is FM-modulated and recorded / reproduced on / from a recording medium such as a magnetic tape, due to the demodulation principle of the FM signal, a noise component with a frequency component in the vicinity of a carrier has a smaller output than a carrier frequency. It is conventionally known that so-called “triangular noise” occurs in which the output level increases in proportion to the distance. Therefore, noise reduction means called "video emphasis" is generally used in actual VTRs and the like. The means and operation will be described with reference to FIGS. 2 and 3 as well.

FIG. 2 is a block system diagram of a typical VTR (information recording / reproducing apparatus) 1. The recording side is as shown in the figure.
LPF (low-pass filter) 2, AGC (automatic gain control circuit)
17, pre-emphasis circuit 10, clip circuit 2
5, a clamp circuit 6, an FM modulator 7, an HPF (high-pass filter) 8, a recording amplifier (amplifier) 9, etc., and a reproducing preamplifier (preamplifier) 11, 12 and a switcher 13, an HPF 14, a limiter on the reproducing side. 15, FM demodulator 16,
The de-emphasis circuit 20, the LPF 3, the output amplifier 18, and the like. The pair of video heads H _1, H provided on the rotary drum D to which the magnetic tape T is attached
₂ is for both recording and reproducing, and the rotary transformer RT is also for recording and reproducing. The pre-emphasis circuit 10 is constituted by connecting a capacitor C and two resistors R _{A and} R _B as shown in FIG. 4 (A), and has an emphasis characteristic as shown in FIG. 4 (B). ing.

In such a configuration, the high frequency component is emphasized by the pre-emphasis circuit 10 before the FM modulation by the FM modulator 7 during recording {see FIGS. 3 (A) and (B)},
During reproduction, after being demodulated by the FM demodulator 16, the high-frequency component is suppressed by the de-emphasis circuit 20 to suppress noise in the high frequency region. This method is SN
Although it has a great effect on the improvement of the ratio, since the high frequency band of the video signal is emphasized and recorded, at the rising portion of the waveform where a large amount of high frequency components are gathered at the time of reproduction, where the waveform sharply changes from black to white, F
The so-called "reversal" phenomenon in which the M signal waveform does not cross zero easily occurs. Therefore, a clip circuit 2 that removes an excessive spike portion after (pre) emphasis during recording
5 is used so as not to increase the amount of transient frequency displacement {see FIGS. 3 (B) and 3 (C)}. However, as shown in FIG. 3D, the waveform in which a part of the high-frequency component is lost by the clipping circuit 25 cannot be restored even if it is de-emphasized, and the waveform deteriorates.

Therefore, instead of the pre-emphasis circuit 10 having the configuration shown in FIG. 4 (A), the clipping circuit 24 is provided in the feedback (negative feedback) loop of the operational amplifier 26 as shown in FIG. 5 (A). And a de-emphasis circuit 21 to reduce the deterioration of the waveform.
This is being done more than ever before. The output of the pre-emphasis circuit 10 in this case has a waveform to which a signal component for reducing the waveform deterioration is added immediately after clipping as shown by the solid line in FIG. The broken line in FIG. 5 (B) is shown in FIG. 4 (A).
7 is an output waveform of the conventional configuration shown in FIG.

[0006]

In the conventional pre-emphasis circuit 10 shown in FIG. 5 (A), if feedback processing similar to analog signal processing is attempted to be performed by digital signal processing, it takes one clock period. It is difficult to realize a circuit capable of real-time processing because the calculation within {in the case of real-time digital signal processing of a video signal is usually several tens of nanoseconds or less} is complicated and large-scale. Therefore, for digitization, an output equivalent to that of the circuit of FIG. 5 (A) was obtained, and development of an open loop processing method with only partial feedback was desired.

[0007]

The pre-emphasis circuit of the present invention applies an emphasis circuit for emphasizing video data (emphasizing edges of signal pulses) and white and dark clips to the emphasized video data. A first clipping circuit, and a first delay circuit for delaying the emphasised video data by the same time as the time required for signal processing in the clipping circuit,
A subtracter that outputs the difference between the output of this delay circuit and the output of the clip circuit, a table for data conversion that gives a predetermined input / output characteristic to the output of this subtractor, and a high frequency component of the output of this table A low-pass filter for attenuating, a low-pass filter and a subtractor, a second delay circuit for delaying the output of the first clip circuit by the same time as the signal processing time in the table, the delay circuit and the low-pass filter The above problem is solved by including an adder that adds the outputs of the filter and a second clip circuit that applies a white clip and a dark clip to the output of the adder.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the pre-emphasis circuit of the present invention will be described with reference to FIG. FIG. 1 shows an open loop pre-emphasis circuit 3 of the present invention.
2 is a block system diagram of 0, in which 27 is an emphasis circuit, 22 and 23 are clip circuits, 31 and 32 are delay circuits, 28 is a subtractor, 29 is a table, 4 is an LPF, 34
Is an adder. It is desirable that the clip circuits 22 and 23 have the same clip level.

The emphasis circuit 27 has an input / output characteristic equivalent to that of the circuit of FIG. 4 (A) and performs digital signal processing. Specifically, for example, one clock delay line (delay circuit) CD ₁ , addition This is configured by connecting the units 35 and 36 and the multipliers 43 to 45 as shown in FIG.
Alternatively, the 4-clock delay line 33, the 1-clock delay line (delay circuit) CD _{2 to} CD ₅ , the adders 37 to 41, and the multiplier 46
7 to 51, these may be connected as shown in FIG. In both FIGS. 6 and 7, the input terminals A to
An arbitrary coefficient for multiplication is supplied from I, and the transfer function of the emphasis circuit 27b shown in FIG. 7 has substantially the same configuration as that of the emphasis circuit 27a shown in FIG.

As is clear from both figures, both configurations are provided with a feedback portion, but calculations of this degree are possible with current IC manufacturing technology. By the way, if the emphasis circuit 27a can perform one multiplication and one addition operation within the broken line within one clock period, the other parts are open loops, so that data can be latched as necessary, so that the realization is realized. It's easy. Also, the emphasis circuit 27b
In the configuration, since the multiplication within the broken line may be performed within 4 clock periods for one data, it can be realized more easily than the emphasis circuit 27a by performing parallel processing or pipeline processing.

As shown in FIG. 8, the clipping circuits 22 and 23 of FIG. 1 output x or y respectively when data having a value greater than or equal to a certain value x or less than y is input, and between x and y. In that case, it is constituted by a ROM table that outputs the same value as the input, or a logic gate such as a circuit as shown in FIG. In FIG. 9, 53 and 54 are magnitude comparators, 55 is a control circuit, and Sw is a changeover switch controlled by the control circuit 55. The operation logic of the control circuit 55 is shown in FIG.

The table 29 of FIG. 1 is a circuit composed of a ROM table or logic gate having the input / output characteristics shown in FIG. The LPF 4 may have a simple structure such that a simple LPF including a resistor R and a capacitor C as shown in FIG. 12 is converted into a digital signal. Also,
The delay circuit 31 has a function of correcting the data delay of the clipping circuit 22, and the delay circuit 32 includes the subtractor 28 and the table 2.
9 and the function of correcting the data delay due to the LPF 4.

The pre-emphasis circuit 3 having the above configuration
The operation of 0 will be described with reference to the signal waveform diagram (timing chart) of FIG. However, since the actual circuit performs digital signal processing, the actual output of each constituent circuit is a numerical value such as a binary system. Therefore, for convenience of explanation, FIG. 13A to FIG. 13J show the outputs of the respective constituent circuits which are D / A converted and analog-displayed.

When a rectangular wave as shown in FIG. 13A is supplied to the input terminal In1, the rising edge and the falling edge are emphasized by the emphasis circuit 27 as shown in FIG. Is clipped by the clipping circuit 22 (that is, the upper side is a white clip and the lower side is a dark clip) as shown in FIG. 7C, and then supplied to the negative input terminal of the subtractor 28. The delay circuit 31 is connected to the positive input terminal of the subtractor 28.
In this case, the signal to be emphasized whose timing is adjusted is supplied as shown in (D) of FIG.
, A signal equivalent to that removed by the clip circuit 22 is output.

Such a signal is subjected to the non-linear correction of the input / output characteristic shown in FIG. 11 in the table 29 at the next stage {see (F) in the figure}, and then the high frequency component is removed by the LPF 4, and the adder is added. 34. From the other input terminal of the adder 34, the clipped signal whose timing is adjusted by the delay circuit 32 as shown in FIG. 7H is supplied, so the adder 34 adds the added signal as shown in FIG. Is output. By clipping this signal with the clipping circuit 23,
The signal shown in FIG. 5J, that is, the signal shown in FIG. 5 is obtained.

By the way, in the case of the main emphasis used in the VHS system or S-VHS (both are registered trademarks) type VTR, the time constant of the LPF 4 is set to about 0.3 μs, and the input / output characteristics of the table 29 are shown in FIG. By making it non-linear as described above, an emphasis output with waveform deterioration compensation similar to that of the analog pre-emphasis circuit shown in FIG. 5A is obtained. Although the input / output characteristic of the table 29 is preferably non-linear as shown in FIG. 11, it may be configured with a linear characteristic of y = kx (k is an appropriate constant) for the sake of simplification of the circuit.

In the above description, the pre-emphasis circuit of the present invention is applied to the VTR, but the present invention is not limited to this, and can be applied to, for example, an apparatus for transmitting with a cable TV or a broadcasting apparatus. .

[0018]

Since the pre-emphasis circuit of the present invention is constructed as described above, it has various excellent features as follows. (1) The same compensation effect as the output of the pre-emphasis circuit, which is used for analog signal processing and compensates for waveform reproduction by clipping, can be obtained. (2) The configuration is suitable for digital signal processing, and can be easily integrated into an IC. (3) A circuit that does not require adjustment due to digitization and that does not change in characteristics due to characteristic variations, changes over time, changes in temperature, etc. can be obtained. (4) Since an ultra-high-speed arithmetic circuit is not required, power consumption can be saved, the yield when integrated into an IC can be increased, and mass production is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a pre-emphasis circuit of the present invention.

FIG. 2 is a typical block diagram of a VTR in which the circuit of the present invention is used.

FIG. 3 is a signal waveform diagram for explaining the reason why the circuit of the present invention is necessary.

FIG. 4 is a typical circuit diagram of a conventional pre-emphasis circuit and its emphasis characteristic diagram.

FIG. 5 is a block diagram of another conventional example of the pre-emphasis circuit and its output waveform diagram.

FIG. 6 is a block diagram of an example of an emphasis circuit that constitutes the circuit of the present invention.

FIG. 7 is a block diagram of another example of the emphasis circuit which constitutes the circuit of the present invention.

FIG. 8 is a clip characteristic diagram of a clip circuit that constitutes the circuit of the present invention.

FIG. 9 is a specific circuit configuration diagram of a clip circuit that constitutes the circuit of the present invention.

FIG. 10 is a logic diagram for explaining the operation of a control circuit that constitutes a clip circuit.

FIG. 11 is an input / output characteristic diagram of a table forming the circuit of the present invention.

FIG. 12 is a typical circuit diagram of a conventional LPF.

FIG. 13 is a signal waveform diagram for explaining the operation of each part of the circuit of the present invention.

[Explanation of Codes] 2-4 LPF (Low-pass Filter) 10,30 Pre-emphasis circuit 22-25 Clip circuit 27, 27a, 27b Emphasis circuit 28 Subtractor 29 Table 31-33, CD _1- CD ₅ Delay circuit 34 to 41 Adder 43 to 51 Multiplier 53, 54 Magnitude comparator 55 Control circuit Sw changeover switch

Claims (1)

(57) [Claims] 1. A pre-emphasis circuit for emphasizing A / D-converted video signal data by digital signal processing, and an emphasis circuit for emphasis of the video data, and a white clip and a dark for the emphasized video data. A first clip circuit that clips, a first delay circuit that delays the emphasized video data by the same time as the time required for signal processing in the clip circuit, and a difference between the output of the delay circuit and the output of the clip circuit. , A table for data conversion that gives a predetermined input / output characteristic to the output of the subtractor, a low-pass filter that attenuates high-frequency components of the output of the table, and the low-pass filter. For the same time as the signal processing time in the converter, the subtractor and the table. Second delay circuit for delaying the output of the clipping circuit, an adder for adding the outputs of the second delay circuit and the low-pass filter, and a white clip and a dark clip for the output of the adder. A pre-emphasis circuit, comprising: a second clipping circuit to be applied.