JPH04284727A - Signal processor - Google Patents

Abstract

PURPOSE:To avoid an undesired waveform change by sending a signal in a positive time series to a transmission circuit, making the phase of the signal zero through the same transfer characteristic in an opposite time series and implementing the signal processing for a period being twice the impulse response time alpha of the transmission circuit or over. CONSTITUTION:When a rectangular continuous pulse is given to an input terminal 20 and a transmission circuit 1 is used to emphasize the pulse, an overshoot is caused. The signal is inputted to storage means 2-4, in which the signal is stored for twice the impulse response time alpha of the transmission circuit 1. Then the stored signal is inputted to a storage means 8 via a transmission circuit 5 whose transfer characteristic G is the same as that of the circuit 1. The signal is stored over a prescribed period and then read in an opposite time series to the time series of the signal to be stored and the signal is inputted to a switch 11. Similarly, the signal is processed in the storage means 3, 4 and the switch 11 and the switch 11 selects any of 3 series of signals at each time a and the selected signal is outputted as one series signal to an output terminal 21. The output signal appearing at the output terminal 21 has an emphasis waveform having a pre-shoot and an overshoot and does not strike on a prescribed clip level and no reproduction waveform distortion after FM modulation is not caused.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for processing the frequency characteristics of an input signal such as a video signal or an audio signal.

0002

[Prior Art] In video tape recorders and the like that record and reproduce video signals, in a frequency modulation/demodulation system, if the noise on the FM transmission line is white noise, the noise added to the demodulated signal will increase in noise level as the frequency increases. It exhibits an increasing so-called triangular noise characteristic. In order to alleviate this, the level of the medium and high range of the input signal is increased before frequency modulation (so-called emphasis is applied to increase the frequency deviation width), and the level of the medium and high range is increased after frequency demodulation. Signal processing is performed to lower the signal (so-called de-emphasis). However, since the band of the FM transmission line is limited by the electromagnetic conversion system, there is a limit to the increase in frequency deviation width due to the amount of emphasis, which causes the problem of limiting the S/N ratio of the reproduced signal. Ta. Note that this problem occurs not only in video tape recorders but also in all systems in which video signals are frequency modulated and transmitted, such as satellite broadcasting.

FIG. 4 shows a conventional emphasis circuit. In FIG. 4, a video signal applied to an input terminal 50 is subjected to emphasis processing and outputted to an output terminal 54. The conventional emphasis circuit in FIG. 4 has a capacitor 51 (capacitance value C
), resistance 52 (resistance value Rb), resistance 53 (resistance value Ra)
It consists of When a signal as shown in FIG. 5(a) is input to such a circuit, a signal as shown in FIG. 5(b) is obtained at the output terminal 53. In the case of a video tape recorder, the signal shown in Figure 5(b) is frequency-modulated and recorded on a magnetic tape, but since there is a limit to the frequency band of the electromagnetic conversion system, which is the FM transmission line,
Frequency modulation is performed by clipping at levels as shown by broken lines S1 and S2 in FIG. 5(b)). For this reason, there is a problem that the frequency demodulated signal causes waveform distortion, and to prevent it from being clipped, the emphasis amount (Ra + Rb) / Ra is reduced to 1/2.
In this case, the effect of the emphasis becomes 1/2, and the SN ratio of the reproduced signal decreases accordingly.

0004

These problems are significant in all systems involving frequency modulation in signal transmission. In other words, when the amount of emphasis for improving SN in frequency modulation is increased, the waveform reproducibility deteriorates due to clipping, and when the amount of emphasis is decreased to improve the waveform reproducibility, the amount of SN improvement also decreases. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal processing device that eliminates the above-mentioned drawbacks, uses a sufficient amount of emphasis, and obtains good waveform reproducibility.

[0006]

[Means for Solving the Problems] In order to solve the above problems, the signal processing device of the present invention divides the signal passing through the first transmission circuit whose transmission characteristic is G into three series, and stores the signal in the first storage means. , is input into the second storage means and the third storage means,
After the signal input to the first storage means is stored for a period at least twice as long as the impulse response duration α of the first transmission circuit, the signal is stored in a time series opposite to the time series in which it was stored. It is read out, inputted into the fourth storage means via a second transmission circuit having the same transfer characteristic G as the first transmission circuit, and stored after being stored for at least a period of α. The signal input to the second storage means, which is read out in the reverse chronological order and input to the switch, and which operates a time α time later than the first storage means, is stored for a period of at least twice α. After being stored over a period of time, the data is read out in a time series opposite to the stored time series, and is transferred to a fifth storage means via a third transmission circuit having the same transfer characteristic G as that of the first transmission circuit. After being inputted and stored for at least an α period, it is read out in a reverse chronological order to the stored time sequence and input to the switch, and operates further a time later than the second storage means. The signal input to the third storage means is stored for a period at least twice as long as α, and then read out in a time series opposite to the stored time series and sent to the first transmission circuit. is inputted into the sixth storage means through a fourth transmission circuit having the same transfer characteristic G as , and after being stored for at least a period of α or more, it is read out in a time series opposite to the stored time series. The signal is input to the switch, and the switch is configured to switch the three series of signals at every α time and output them as one series of signals to the output terminal.

[0007]

[Operation] By adopting the above-described configuration of the present invention, the conventional problems are solved, and if the same FM transmission line is used, it is possible to use a larger amount of emphasis than before with the same frequency shift width as before. Make it. Alternatively, it is possible to realize a signal processing device in which the peak of the waveform is significantly lower than that of the conventional one with the same amount of emphasis as the conventional one. Furthermore, it is possible to provide a signal processing device having arbitrary transfer characteristics with preshoot and overshoot. Furthermore, it is possible to compensate for the phase characteristics of the transmission circuit and make the phase change of the processed signal zero in real time.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the signal processing apparatus of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a signal processing device of the present invention. Moreover, (FIG. 3) is a waveform diagram showing signal waveforms of each part of the signal processing device of FIG. 1. In FIG. 1, a signal input to the input terminal 20 is input to the first transmission circuit 1 whose transfer characteristic is G. Input end 2
For example, a signal as shown in FIG. 3(a) is input to 0. The output signal of the first transmission circuit 1 has a waveform with overshoot if the first transmission circuit is an emphasis circuit, as shown in FIG. 3(b). The signal passing through the first transmission circuit 1 is divided into three series, which are stored in the first storage means 2,
The information is input to the second storage means 3 and the third storage means 4. The signal input to the first storage means 2 has a duration of at least 2 of the impulse response duration α of the first transmission circuit 1.
It will be remembered for more than twice as long. In (FIG. 3), after being stored for a period of 3α indicated by A in (FIG. 3(b)), the data is read out in a time series opposite to the stored time series. (FIG. 2) is a block diagram showing an example of a storage means used in the present invention. In FIG. 2, the signal input to the input terminal 30 is stored in the storage means 31. For example, in the first storage means 2, the storage capacity of the storage means 31 is 2α or more, and in the signal example shown in FIG. 3, the storage capacity is 3α. Storage means 3
The signal stored as 1 is read out by an addresser 33 that generates an address order opposite to the address order at the time of storage, and outputted to the output terminal 32. By realizing the time axis reversal in this manner, the output signal of the first storage means 2 has a waveform as shown in FIG. 3(c). Next, the signal is input to the fourth storage means through the second transmission circuit 5 having the same transfer characteristic G as the first transmission circuit 1. The output signal of the second transmission circuit 5 has a waveform as shown in FIG. 3(f). The signal input to the fourth storage means 7 is at least α
be remembered for a longer period of time. (D in Figure 3(f)
After being stored for a J period excluding an E period, it is read out in a reverse chronological order to the stored time sequence and the switch 11
is input. The J period is a 2α period in (FIG. 3). The output signal of the fourth storage means (FIG. 3(
i))

Similarly, the signal input to the second storage means 3, which operates at a time α time later than the first storage means 1, is stored for a period of at least twice α, and then It is read out in the reverse chronological order of the memorized chronological order. The output signal of the second storage means 3 is as shown in FIG. 3(d). The output signal of the second storage means 3 is input to the fifth storage means 9 via the third transmission circuit 6 having the same transfer characteristic G as the first transmission circuit 1. The output signal of the third transmission circuit 6 is as shown in FIG. 3(g). After being stored in the fifth storage means 9 for at least a period of time or more, it is read out in the reverse chronological sequence to the stored chronological sequence. After being stored for K periods excluding periods F and G (FIG. 3(g)), the signals are read out in the reverse chronological order to the stored chronological order and input to the switch 11. The K period is a 2α period in (FIG. 3). Said fifth
The output signal of the storage means 9 is as shown in FIG. 3(j).

Similarly, the signal input to the third storage means 4, which operates with a further α time delay than the second storage means 3, is stored for a period of at least twice α, and then , are read out in the reverse chronological order to the memorized chronological order. The output signal of the third storage means 4 is (FIG. 3(e)
)become that way. The output signal of the second storage means 3 is
a fourth transmission circuit having the same transfer characteristic G as the first transmission circuit 1;
The signal is input to the sixth storage means 10 via the transmission circuit 7 . The output signal of the fourth transmission circuit 7 is as shown in FIG. 3(h). Next, the data is stored in the sixth storage means 10 for at least a period of α, and then read out in the reverse chronological order to the stored chronological order. In (Fig. 3(h)), H
After being stored for an L period excluding the I period, the switch 11 is read out in the reverse chronological order to the stored chronological order.
is input. The L period is a 2α period in (FIG. 3). The output signal of the sixth storage means 10 is as shown in FIG.
(k1)).

The switch 11 outputs the three series of signals to the output end 21 as one series of signals while switching them at every α time. The output signal appearing at the output end 21 is (Fig. 3(l))
As shown in FIG. 3(a), an emphasis waveform having preshoot and overshoot is obtained. (FIG. 3(l)), clip levels S1, S
2, no distortion occurs in the reproduced waveform after FM demodulation.

Further, the first, second, third, fourth, fifth, and sixth storage means may be analog memories, but more preferably, an AD converter is provided before the input terminal 20, and the first , digital memories may be used as the second, third, fourth, fifth, and sixth storage means. Also, the first, second, third,
It is preferable to use a digital filter as the fourth transmission circuit. In this case, in order to completely flatten the frequency characteristics after emphasis/de-emphasis, it is preferable to use a digital filter design using bilinear transformation. Further, in the explanation of FIG. 1, the emphasis circuit was described, but it may be used in a circuit generally intended to provide preshoot and overshoot. In addition, in FIG. 1, the fourth
The fifth and sixth storage means return the time axis of the signal from reverse time series to forward time series, but in order to reduce the circuit size, they are omitted and are recorded in reverse time series and returned to normal time series during playback. It's okay.

Furthermore, as shown in FIG. 7, the switch 11 in FIG. 1 may be removed and an adder 22 may be installed in its place. In this case, the impulse responses generated by each transmission circuit are superimposed while preserving the signal periods D, E, F, G, H, and I that were cut off in (Fig. 3(f), (g), and (h)). match. As a result, a processed waveform similar to the output waveform obtained when the block diagram shown in FIG. 1 is used is obtained.

Further, in order to reduce the number of circuits, a configuration as shown in FIG. 6 may be used. Furthermore, as shown in FIG. 6, the first transmission circuit 1 in FIG. 1 may be removed. That is, the signal input to the input terminal 60 is immediately divided into three series and the first
switch 61, second switch 62, and third switch 63. The signal that has passed through the first switch 61 passes through the first transmission circuit 64 with the transfer characteristic G, is read out once in the reverse time series to the time series stored in the first storage means 67, and is read out in the reverse time series to the time series stored in the first storage means 67. 61 again to the first transmission circuit 64 in reverse time series. As a result, since the divided signals are processed on the forward time axis and the reverse time axis, phase linear signal processing is achieved. Similarly, the signal input to the second switch 62 passes through the second transmission circuit 65 having the same transmission characteristic G as that of the first transmission circuit 64, and is once stored in the second storage means 68. Next, the data is read out in a time series opposite to the stored time series, and is input to the second transmission circuit 65 in reverse time series via the second switch 62 again. The signal input to the third switch 63 passes through a third transmission circuit 66 having the same transmission characteristic G as that of the first transmission circuit 64, and is once stored in the third storage means 69. Next, the data is read out in a time series opposite to the stored time series, and is input to the third transmission circuit 66 in reverse time series via the third switch 63 again. Second
The switch 62 and the second storage means 68 operate with a delay of the impulse response duration α of the first transmission circuit 64 from the first switch 61 and the first storage means 67, respectively,
The third switch 63 and the third storage means 69 are connected to the first transmission circuit 6 by the second switch 62 and the second storage means 68.
4 impulse response durations α, respectively. The fourth switch 70 converts the three series divided signals into one series continuous signal and outputs it to the output terminal 71. In this way, the circuit scale is reduced by the amount of the first transmission circuit 1 (FIG. 1) compared to the embodiment shown in FIG. 1.

Similarly, as shown in (FIG. 8), (FIG. 6
) switch 70 may be removed and an adder 72 may be installed in its place. In this case as well, (Fig. 3(f), (g), (
The signal periods D, E, F, G, H, truncated in h),
While preserving I, the impulse responses generated by each transmission circuit are superimposed. As a result, a processed waveform similar to the output waveform when using the block diagram shown in FIG. 6 is obtained.

Furthermore, although the present invention has been described with reference to the case where three series of signal processing using time axis inversion are used in parallel, the same effect can be obtained even if two series of signal processing are performed.

[0017]

As described above, according to the signal processing device of the present invention, a signal is passed through a transmission circuit in a positive time series once, and then passed through a transmission circuit having the same transfer characteristics in a reverse time series. This output has the effect of making the phase characteristic of the transmission circuit zero phase, and is particularly useful for video signals.

[0018] Furthermore, when dividing and processing continuous signals,
at least 2 of the duration α of the impulse response of the transmission circuit
Since the processing is performed over twice as long, it is possible to avoid unnecessary waveform changes that occur in discontinuous portions of the signal.

Furthermore, by performing the above processing in three series, it is possible to divide a continuous signal into segmented signals, process them, and then output them again as a continuous signal in real time.

Furthermore, as described above, when the signal processing device of the present invention is used as an emphasis circuit in a frequency modulation/demodulation system, by giving the waveform a preshoot and an overshoot, it can have the same amount of emphasis as the conventional one. ,
It is also possible to realize an emphasis circuit in which the peak value of the waveform is lower than before, without reducing the amount of emphasis.
This has the effect of significantly reducing the frequency deviation width compared to the conventional method. Alternatively, it is possible to add more emphasis than before, and it is possible to improve the waveform reproducibility of the reproduced signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a signal processing device of the present invention.

[Figure 2
] A block diagram showing a storage means used in the signal processing device of the present invention.

FIG. 3 is a waveform diagram showing signal waveforms of each part of the signal processing device of the present invention.

[Figure 4] Circuit diagram showing a conventional signal processing device

[Figure 5] Waveform diagram showing processed waveforms by a conventional signal processing device

FIG. 6 is a block diagram showing another embodiment of the signal processing device of the present invention.

FIG. 7 is a block diagram showing still another embodiment of the signal processing device of the present invention.

FIG. 8 is a block diagram showing still another embodiment of the signal processing device of the present invention.

[Explanation of symbols]

1 First transmission circuit 2 First storage means 3 Second storage means 4 Third storage means 5 Second transmission circuit 6 Third transmission circuit 7 Fourth transmission circuit 8 Fourth storage means 9 Fifth storage means 10 Sixth storage means 11 Switch 12 Input end 13 Output end

Claims (4)

[Claims] Claim 1: A signal passing through a first transmission circuit having a transfer characteristic of G is divided into three series, and is inputted to a first storage means, a second storage means, and a third storage means, After the signal input to the first storage means is stored for a period at least twice the impulse response duration α of the first transmission circuit, it is read in a time series opposite to the time series in which it was stored. and is input to a fourth storage means through a second transmission circuit having the same transfer characteristic G as the first transmission circuit,
The second memory is stored for at least a period of time, is read out in a reverse chronological order to the stored time series, and is input to a switch, and operates at a time delay of α time relative to the first storage means. The signal input to the means is at least 2 of α
After being stored for a period more than twice as long, it is read out in a time series opposite to the stored time series, and passed through a third transmission circuit having the same transfer characteristic G as the first transmission circuit, and then passed through a fifth transmission circuit. is inputted into the storage means and stored for at least a period of α, and then read out in a time series opposite to the stored time series and inputted to the switch, and further stored at time α from the second storage means. The signal input to the third storage means, which operates with a delay, is stored for a period at least twice as long as α, and then read out in a time series opposite to the time series in which it was stored. The fourth transmission circuit has the same transfer characteristic G as that of the first transmission circuit.
is inputted to the sixth storage means through the transmission circuit, and is stored for at least a period of time or longer, and then read out in a time series opposite to the stored time series and inputted to the switch,
A signal processing device characterized in that the switch outputs one series of signals to an output terminal while switching the three series of signals at every α time. [Claim 2] An adder is used in the switch part, and 3
2. The signal processing device according to claim 1, wherein the signal processing device outputs one series of signals while adding the series of signals. 3. The signal input to the input terminal is divided into three series and input to a first switch, a second switch, and a third switch, and the signal passing through the first switch has a transfer characteristic G.
is once stored in the first storage means through the first transmission circuit of
By inputting the divided signals in reverse time series to the first transmission circuit via the switch again, signal processing is performed on the forward time axis and the reverse time axis, and in the same way, the second switch The input signal passes through a second transmission circuit having the same transfer characteristic G as that of the first transmission circuit, is stored in the second storage means, and is then read out in a time series opposite to the stored time series. , the signal is input to the second transmission circuit in reverse time series via the second switch again, and the signal input to the third switch is input to the third transmission circuit having the same transfer characteristic G as that of the first transmission circuit. is once stored in the third storage means, then read out in a reverse time series to the stored time series, inputted to the third transmission circuit in reverse time series via the third switch again, and then
The switch and the second storage means operate with a delay of the impulse response duration α of the first transmission circuit from the first switch and the first storage means, respectively.
The storage means operates with a delay of the impulse response duration α of the first transmission circuit from the second switch and the second storage means, respectively, and the fourth switch operates while switching the three series classification signals at every time α. A signal processing device characterized in that the signal is converted into one series of continuous signals and outputted to an output terminal. [Claim 4] An adder is used in the switch part, and 3
4. The signal processing apparatus according to claim 3, wherein the signal processing apparatus outputs one series of signals while adding the series of signals.