JPH0793590B2 - Signal processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for processing frequency characteristics of an input signal such as a video signal or an audio signal.

[0002]

2. Description of the Related Art In a video tape recorder or the like for recording / reproducing a video signal, if the noise of the FM transmission line is white noise in a frequency modulation / demodulation system, the noise added to the demodulated signal will have a noise level as the frequency increases. It exhibits a so-called triangular noise characteristic that increases. In order to reduce this, increase the mid- and high-frequency levels of the input signal before frequency modulation (so-called emphasis is applied to increase the frequency shift width), and after the frequency demodulation, increase the mid- and high-frequency levels. Signal processing to reduce (so-called de-emphasis) is performed. However, since the band of the FM transmission line is limited by the electromagnetic conversion system and the like, there is a limit to the increase in the frequency deviation width due to the amount of emphasis, which causes a problem that the SN ratio of the reproduced signal is limited. It was It should be noted that this problem occurs not only in video tape recorders but also in all systems that frequency-modulate and transmit video signals such as satellite broadcasting.

FIG. 4 shows a conventional emphasis circuit.
In FIG. 4, the video signal applied to the input end 50 is subjected to emphasis processing and output to the output end 54. The conventional emphasis circuit in FIG. 4 has a capacitor 51 (capacitance value C), a resistor 52 (resistance value Rb), a resistor 53 (resistance value R).
a). In such a circuit (Fig.
When a signal as shown in (a)) is input, the output end 5
A signal as shown in FIG. 5B is obtained at 3. In the case of a video tape recorder, a signal as shown in FIG. 5 (b) is frequency-modulated and recorded on a magnetic tape, but the frequency band of the electromagnetic conversion system that is the FM transmission line is limited (see FIG. 5 (b)) is clipped at a level as shown by broken lines S1 and S2 and frequency-modulated. For this reason, there is a problem that the frequency demodulated signal causes waveform distortion, and the emphasis amount (Ra + Rb) / R is set so that the signal is not clipped.
When a is set to 1/2, the effect of emphasis is reduced to 1/2, and there is a problem that the SN ratio of the reproduced signal is reduced accordingly.

[0004]

These problems are significant in all systems involving frequency modulation in the transmission of signals. That is, when the emphasis amount for improving the SN in frequency modulation is increased, the waveform reproducibility is deteriorated due to clipping, and when the emphasis amount is reduced to improve the waveform reproducibility, the SN improvement amount is also decreased. .

An object of the present invention is to solve the above-mentioned drawbacks and to provide a signal processing apparatus which uses a sufficient emphasis amount and obtains good waveform reproducibility.

[0006]

In order to solve the above-mentioned problems, in the signal processing device of the present invention, the signal passed through the first transmission circuit having the transfer characteristic of G is divided into three series, and the first storage means , Input to the second storage means and the third storage means,
The signal input to the first storage means is stored for a period that is at least twice the impulse response duration α of the first transmission circuit and then stored in a time series opposite to the stored time series. When it is read out, input to the fourth storage means via the second transmission circuit having the same transfer characteristic G as the first transmission circuit, stored for at least α period or more, and then stored The signal read out in a time series opposite to that of the series and inputted to the switch, and inputted to the second storage means which operates with a delay of α time from the first storage means is at least twice as long as α or more. After being stored in the fifth storage means through the third transmission circuit having the same transfer characteristic G as that of the first transmission circuit and read out in a time series opposite to the stored time series. After being input and stored for at least α period, The signal read out in a time series opposite to the stored time series, input to the switch, and input to the third storage means which operates with a delay of α time from the second storage means is α After being stored for at least twice as long, it is read in a time series opposite to the stored time series and has the same transfer characteristic G as that of the first transmission circuit.
Is input to the sixth storage means via the fourth transmission circuit having the above, is stored for at least α period or more, is then read out in a time series opposite to the stored time series, and is input to the switch. The switch is configured to output a signal of one series to the output terminal while switching a signal of three series every α times.

[0007]

By adopting the above-mentioned structure of the present invention, the conventional problems can be solved, and if the same FM transmission line is used, the amount of emphasis more than the conventional one can be used with the same frequency deviation width as the conventional one. To Alternatively, it is possible to realize a signal processing device in which the peak of the waveform is significantly lower than in the conventional case with the same amount of emphasis as in the conventional case. Further, it is possible to provide a signal processing device having an arbitrary transfer characteristic having a preshoot and an overshoot. Further, it is possible to compensate for the phase characteristic of the transmission circuit and make the phase change of the processed signal zero, in real time.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the signal processing device of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a signal processing device of the present invention. FIG. 3 is a waveform diagram showing the signal waveform of each part of the signal processing device of FIG. In FIG. 1, the signal input to the input terminal 20 is input to the first transmission circuit 1 having a transfer characteristic of G. A signal as shown in FIG. 3A, for example, is input to the input terminal 20. The output signal of the first transmission circuit 1 is (FIG. 3B).
If the first transmission circuit is an emphasis circuit as shown in FIG. 5, the waveform has an overshoot. The signal that has passed through the first transmission circuit 1 is divided into three series, and the first storage means 2
Are input to the second storage means 3 and the third storage means 4. The signal input to the first storage means 2 is stored for a period that is at least twice the impulse response duration α of the first transmission circuit 1. In (FIG. 3), after being stored for the 3α period indicated by A in (FIG. 3 (b)), it is read in a time series opposite to the stored time series. FIG. 2 is a block diagram showing an example of storage means used in the present invention. The signal input to the input terminal 30 in FIG. 2 is stored in the storage means 31. For example, the first
In the storage means 2 of, the storage capacity of the storage means 31 is 2α or more,
In the signal example of FIG. 3, the capacity is 3α. The signal stored in the storage means 31 is read by an addresser 33 that generates an address order opposite to the address order at the time of storage and is output to an output terminal 32. By realizing the time axis inversion in this way, the output signal of the first storage means 2 has a waveform as shown in FIG. 3 (c). Next, it is input to the fourth storage means via the second transmission circuit 5 having the same transfer characteristic G as the first transmission circuit 1. The output signal of the second transmission circuit 5 has a waveform as shown in FIG. 3 (f). The signal input to the fourth storage unit 7 is stored for at least the α period or more. (After being stored for J periods excluding D and E periods in FIG. 3 (f),
It is read out in a time series opposite to the stored time series and input to the switch 11. The J period is a 2α period in (FIG. 3). The output signal of the fourth storage means is as shown in FIG. 3 (i).

Similarly, the signal input to the second storage means 3 which is operated with a delay of α time from the first storage means 1 is stored for a period of at least twice α or more, and then, It is read out in the reverse time series of the stored time series.
The output signal of the second storage means 3 is as shown in FIG. The output signal of the second storage means 3 is input to the fifth storage means 9 via the third transmission circuit 6 having the same transfer characteristic G as that of the first transmission circuit 1. The output signal of the third transmission circuit 6 is as shown in FIG. 3 (g). After being stored in the fifth storage means 9 for at least α period or more, it is read out in a time series opposite to the stored time series. In FIG. 3 (g), after being stored for K periods excluding the F and G periods, they are read out in a time series opposite to the stored time series and input to the switch 11. The K period is a 2α period in (FIG. 3). The fifth
The output signal of the storage means 9 is as shown in FIG. 3 (j).

Similarly, the signal input to the third storage means 4 which operates later by α time than the second storage means 3 is stored for a period of at least twice α or more. , It is read out in a time series opposite to the stored time series. The output signal of the third storage means 4 (see FIG.
(E)). The output signal of the second storage means 3 is input to the sixth storage means 10 via the fourth transmission circuit 7 having the same transfer characteristic G as that of the first transmission circuit 1. The output signal of the fourth transmission circuit 7 is (see FIG.
(H)). Next, after being stored in the sixth storage means 10 for at least the α period or more, it is read out in a time series opposite to the stored time series. (Fig. 3
In (h), after being stored for L periods excluding H and I periods, they are read out in a time series opposite to the stored time series and input to the switch 11. The L period is the 2α period in (FIG. 3). The sixth storage means 10
Output signal is as shown in FIG. 3 (k1).

The switch 11 outputs three series of signals to the output terminal 21 as one series of signals while switching them every α times. The output signal appearing at the output terminal 21 is (Fig. 3 (l)).
Thus, an emphasis waveform having a preshoot and an overshoot with respect to (FIG. 3A) is obtained. In FIG. 3 (l), clip levels S1 and S
Since it does not apply to any of the two, distortion of the reproduced waveform after FM demodulation does not occur at all.

The first, second, third, fourth, fifth and sixth storage means may be analog memories, but more preferably, an AD converter is provided before the input terminal 20, A digital memory may be used as the second, third, fourth, fifth and sixth storage means. Also, the first, second, third,
A digital filter may be used as the fourth transmission circuit. In this case, in order to completely flatten the frequency characteristic after emphasis / de-emphasis, it is preferable to use a digital filter design by bilinear conversion. In the description of (FIG. 1), the emphasis circuit has been described, but the circuit may be used for the purpose of providing preshoot and overshoot in general. In addition, in FIG.
Although the time axis of the signal is restored from the reverse time series to the normal time series by the fifth and sixth storage means, it is omitted to reduce the circuit size and recorded as the reverse time series and restored to the normal time series during reproduction. May be.

As shown in (FIG. 7), the switch 11 (FIG. 1) may be removed and an adder 22 may be installed instead. In this case, the impulse responses generated by the respective transmission circuits are overlapped with the signal periods D, E, F, G, H, and I truncated in (FIGS. 3 (f), (g), and (h)) being preserved. To match. As a result, a processed waveform similar to the output waveform when using the block diagram shown in FIG. 1 is obtained.

Further, the configuration shown in FIG. 6 may be adopted for further circuit reduction. Furthermore, as shown in (FIG. 6), the first transmission circuit 1 in (FIG. 1) may be removed. That is, the signal input to the input terminal 60 is immediately divided into three series, and the first series
Input to the switch 61, the second switch 62, and the third switch 63. The signal passed through the first switch 61 is read through the first transmission circuit 64 having the transfer characteristic G once in a time series opposite to the next stored time series stored in the first storage means 67, and the first switch is read. The signal is input to the first transmission circuit 64 via 61 again in reverse time series. As a result, since the signals are processed on the positive time axis and the reverse time axis with respect to the divided signal, the phase linear signal processing is achieved. Similarly, the signal input to the second switch 62 is once stored in the second storage means 68 via the second transmission circuit 65 having the same transfer characteristic G as the first transmission circuit 64. Then, it is read out in a time series opposite to the stored time series and is input to the second transmission circuit 65 via the second switch 62 in a reverse time series. Third
The signal inputted to the switch 63 of the first transmission circuit 64
It is once stored in the third storage means 69 via the third transmission circuit 66 having the same transfer characteristic G as. Then, the stored data is read in a time series opposite to the stored time series, and is input to the third transmission circuit 66 through the third switch 63 in a reverse time series. The second switch 62 and the second storage means 68 include the first switch 61 and the first storage means 67, and the first transmission circuit 64.
Of the third switch 63 and the third storage means 69 from the second switch 62 and the second storage means 68, respectively. The operation is delayed for each period α. The fourth switch 70 converts the 3-sequence division signal into a 1-sequence continuous signal and outputs it to the output end 71. By doing so, the first of (FIG. 1) is obtained from the embodiment shown in (FIG. 1).
The circuit scale is reduced by the amount of the transmission circuit 1.

Similarly, as shown in (FIG. 8), the switch 70 (FIG. 6) may be removed and an adder 72 may be installed instead. In this case as well ((f), (g),
The signal periods D, E, F, G, which are truncated in (h),
With H and I stored, the impulse responses generated by the transmission circuits of the respective parts are superimposed. As a result (Fig. 6)
A processed waveform similar to the output waveform when the block diagram shown in FIG.

Further, in the present invention, the case where the signal processing using the time axis reversal is used in parallel with three series has been described, but the same effect can be obtained even if the signal processing of two series is performed.

[0017]

As described above, according to the signal processing apparatus of the present invention, a signal is once passed through the transmission circuit in a positive time series and then through a transmission circuit having the same transfer characteristic in an opposite time series. The output has the effect of making the phase characteristic of the transmission circuit zero, and is particularly useful for video signals.

Further, in dividing and processing a continuous signal,
At least 2 of the duration α of the impulse response of the transmission circuit
Since the processing is performed over twice as long, it is possible to avoid unnecessary waveform changes occurring in the discontinuous portion of the signal.

Further, by performing the above-described processing by dividing it into three series, it is possible to execute the work of dividing the continuous signal into the divided signals for processing and then outputting the divided signals again in real time.

When the signal processing device of the present invention is used as an emphasis circuit for a frequency modulation / demodulation system as described above, the waveform has a preshoot and an overshoot, so that it has the same emphasis amount as the conventional one. ,
In addition, an emphasis circuit can be realized in which the peak value of the waveform is lower than before, without reducing the emphasis amount.
This has the effect of significantly reducing the frequency shift width compared to the conventional case.
Alternatively, more emphasis than before can be added, and the waveform reproducibility of the reproduced signal can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a signal processing device of the present invention.

FIG. 2 is a block diagram showing storage means used in the signal processing device of the present invention.

FIG. 3 is a waveform diagram showing a signal waveform of each part of the signal processing device of the present invention.

FIG. 4 is a circuit diagram showing a conventional signal processing device.

FIG. 5 is a waveform diagram showing a processed waveform by a conventional signal processing device.

FIG. 6 is a block diagram showing another embodiment of the signal processing device of the present invention.

FIG. 7 is a block diagram showing still another embodiment of the signal processing device of the present invention.

FIG. 8 is a block diagram showing still another embodiment of the signal processing device of the present invention.

[Explanation of symbols]

 1 1st transmission circuit 2 1st storage means 3 2nd storage means 4 3rd storage means 5 2nd transmission circuit 6 3rd transmission circuit 7 4th transmission circuit 8 4th storage means 9th 5 storage means 10 6th storage means 11 switch 12 input end 13 output end

Continued front page (72) Inventor Atsushi Ochi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yasuo Hamamoto 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) Reference Reference JP-A-59-221126 (JP, A)

Claims (4)

[Claims] 1. A signal that has passed through a first transmission circuit having a transfer characteristic of G is divided into three series, which are input to a first storage means, a second storage means, and a third storage means, and The signal input to the first storage means is stored for at least twice as long as the impulse response duration α of the first transmission circuit and then read in a time series opposite to the stored time series. The time series stored is stored in the fourth storage means via the second transmission circuit having the same transfer characteristic G as that of the first transmission circuit and stored for at least α period. A signal read out in a time series opposite to that of the above, input to the switch, and input to the second storage means that operates with α time delay from the first storage means is at least 2 of α.
After being stored for a period more than twice, it is read out in a time series opposite to the stored time series and passes through a third transmission circuit having the same transfer characteristic G as that of the first transmission circuit to a fifth transmission circuit. Is stored in the storage means for at least α period or more, is then read out in a time series opposite to the stored time series, and is input to the switch. The signal input to the third storage means operating with a delay is stored for a period of at least twice α or more, and then is read out in a time series opposite to the stored time series, and the third time is stored. A fourth transmission circuit having the same transfer characteristic G as that of the first transmission circuit;
Is input to the sixth storage means through the transmission circuit of, is stored for at least α period or more, is then read in a time series opposite to the stored time series, and is input to the switch,
The signal processing device, wherein the switch outputs three series signals to the output terminal as one series signal while switching the signals every α times. 2. The signal processing apparatus according to claim 1, wherein an adder is used in the switch portion and the signals of three series are added and output as signals of one series. 3. The signal input to the input end is divided into three series and input to the first switch, the second switch and the third switch, and the signal passed through the first switch has the first transfer characteristic G1. After being stored in the first storage means once through the transmission circuit of, and read out in a time series opposite to the next stored time series,
Is input to the first transmission circuit in reverse time series again, the signal processing is performed on the separated signal on the forward time axis and the reverse time axis, and similarly, the second switch. The signal input to is first stored in the second storage means through the second transmission circuit having the same transfer characteristic G as that of the first transmission circuit, and is read out in a time series opposite to the next stored time series. , A third transmission circuit having the same transfer characteristic G as that of the signal input to the second transmission circuit in reverse time series via the second switch and input to the third switch. Once stored in the third storage means, the data is read in a time series opposite to the next stored time series, and is input to the third transmission circuit in reverse time series via the third switch again.
Switch and the second storage means operate with a delay of the impulse response duration α of the first transmission circuit from the first switch and the first storage means, respectively.
Of the second switch and the second storage means operate with a delay of the impulse response duration α of the first transmission circuit from the second switch, respectively, and the fourth switch switches the three-sequence division signal every α time. A signal processing device, characterized in that it is converted into one series of continuous signals and output to an output end. 4. The signal processing apparatus according to claim 3, wherein an adder is used in the switch part, and the signals of three series are added and output as signals of one series.