JPH04152779A - Nonlinear digital signal processing circuit - Google Patents

Abstract

PURPOSE:To prevent the effect of distortion due to a limiter by interpolating an input digital signal to a signal of a multiple of plural number per unit time at a pre-stage of the limiter and restoring an output signal of the filter to which a low frequency component passes through to a signal number equal to a sample number of the original input digital signal per unit time at the post stage. CONSTITUTION:A digital input signal S0 sampled by a clock of a reference sampling frequency fS is interpolated by a clock being a multiple of plural number of the reference sampling frequency fS by a signal interpolation means 1. A limiter 2 applies amplitude limit to an output signal S1 of the means 1 by using a same clock as that of the signal interpolation means 1. A low pass filter means 3 passes through a low frequency component of an amplitude limit signal S2. An output signal S3 from the low pass filter means 3 is thinned by using a clock having the reference sampling frequency fS at a signal thinning means 4 and results in a signal of the same sample number per unit time as the input signal S0 of the signal interpolation means 1. Most of distortion component Ed stays in the signal interpolation area and the distortion component Ed resident in the original signal region before interpolation is decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a nonlinear digital signal processing circuit having a limiter used in a nonlinear emphasis circuit, etc., and in particular, the present invention relates to a nonlinear digital signal processing circuit having a limiter used in a nonlinear emphasis circuit. This invention relates to a nonlinear digital signal processing circuit that reduces the effects of distortion.

[Conventional technology]

A signal processing circuit using a limiter that limits the amplitude is VT
Recording/reproducing devices such as R2 are used in nonlinear emphasis circuits, nonlinear de-emphasis circuits, echo cancellers, etc. in various communication systems.

For example, FIG. 15 illustrates an example of a signal 1 processing circuit having a limiter that is commonly used in nonlinear emphasis circuits and nonlinear deemphasis circuits applied to VTRs.

FIG. 15 shows a schematic configuration of a signal processing circuit for a recording system and a reproduction system of a high-definition VTR. In the recording system (upper row of Fig. 15), the analog format recording video signal VI
DEO0 to analog-to-digital signal converter (ADC)
101 into a digital format video signal,
The emphasis circuit 102 increases the high frequency component, and the signal processing circuit 103 performs, for example, line sequential signal conversion processing, time axis compression/expansion processing, shuffling processing, etc., and the digital/analog converter (DAC) 104
The signal-processed digital signal is converted into an analog signal, frequency-modulated by an FM modulation circuit 105, and recorded as a video signal on a magnetic tape 108 via a recording magnetic head 106. In the regeneration system (lower part of Figure 15),
A video signal recorded on the magnetic tape 108 is read by a reproducing magnetic head 111, frequency demodulated via an FM demodulation circuit 112, converted into a digital signal via an ADC 113, and converted into a digital signal by a signal processing circuit 115 in the opposite manner to that of the signal processing circuit 103. The de-emphasis circuit 114 reduces the signal component corresponding to the signal component increased by the emphasis circuit 102, and the reproduced video signal VIDEO is generated via the DAC 116.

In the VTR, as mentioned above, the magnetic tape 108
In order to improve the S/N of recording and reproduction in the recording system, emphasis processing is performed on high frequency components in the recording system, and de-emphasis processing is performed in the reproduction system.

Such an emphasis circuit 102 is, for example, a first
It is composed of an FIR type nonlinear emphasis circuit including the limiter 13 shown in FIG. 6(a). This non-linear emphasis circuit is a high frequency signal component increasing circuit 10a.
, the original signal S10 is passed through a bypass filter (HPF)
A high frequency component whose amplitude should be increased is taken out through a limiter 13, the amplitude is limited to a predetermined magnitude, the amplitude-limited high frequency component is multiplied by a predetermined coefficient k in a coefficient multiplication circuit 16, and an adder circuit 17 adds this emphasis signal S16 to the original signal SIO. This emphasis circuit uses the limiter 13 to limit the amplitude and perform nonlinear signal processing, so it is called a nonlinear emphasis circuit.

FIG. 16(b) shows an FIR type nonlinear de-emphasis circuit corresponding to FIG. 16(a).

This non-linear de-emphasis circuit is shown in Figure 16(a).
In the high frequency signal component reduction circuit 20a, the HPF 22 extracts the high frequency component, the limiter 24 limits the amplitude, and the coefficient multiplication circuit 27 multiplies the coefficient by 1.
The de-emphasis signal S27 is removed from the reproduced original signal S20 in the adder circuit 21 to eliminate the effect of emphasis.

16(a), (bH) The broken non-linear emphasis circuit 102 and non-linear de-emphasis circuit 114 are connected to the signal processing circuit 103 shown by broken lines in FIG.
It may be provided at a subsequent stage, after the signal processing circuit 115.

[Problem to be solved by the invention] Nonlinear emphasis circuit 102 in FIG. 16(a)
Since the limiter 13 is provided in the signal, a problem has been encountered in that the high-order distortion generated by the limiter 13 is reflected back from the sampling clock, and the distortion component falls within the frequency band of the signal. The signal format is shown in FIGS. 17(a) and (b).

FIG. 17(a) shows a frequency spectrum diagram of the input signal S11 of the beam mitter 13, and FIG.
2 shows a frequency spectrum diagram of the output signal S13 of FIG. The horizontal axis represents energy along the sampling frequency f3° line axis. The energy E13 of the output signal S13 of the limiter 13 is lower than the energy Ell of the amplitude-limited public power signal Sll. In FIG. 17(b), the signal component indicated by the two broken lines is the aliasing distortion component Ed that falls within the band.
It shows.

Such distortion component Ed deteriorates the image quality of the reproduced image of the VTR. For example, if an image has distorted edges or ringing occurs, or if the sampling phase shifts, the position of the ringing moves, resulting in a very degraded image.

I have described the problems with VTRs above.

Even if the same non-linear emphasis circuit and non-linear de-emphasis circuit as above are used in the communication system.
A serious problem arises.

Furthermore, not only when applied to non-linear emphasis circuits and non-linear de-emphasis circuits, but also when using the above-mentioned limiter in echo cancellers, etc., the distortion caused by the limiter causes the same problem as above. let

As a method to solve such problems, for example, A
By sampling the DC sampling clock at a frequency that is sufficiently high compared to the signal band (a frequency multiple times higher than the highest frequency of the signal) and performing signal processing on that data, high-order distortion reflected from the sampling clock is eliminated.
A method can be considered to reduce the amount of drop in the signal band. However, there is a problem in that ADCs that operate at high frequencies and have high precision are expensive.

Therefore, it is an object of the present invention to provide a low-cost nonlinear digital signal processing circuit that is not affected by the distortion caused by the limiter described above in a digital signal processing circuit that includes a limiter.

[Failure to solve the problem]

In order to solve the above problems, the non-linear digital signal processing circuit of the present invention includes, as shown in FIG. After the limiter 2,
(Low-pass) filter means for passing low frequency components of the output of the limiter 2;3. It also includes means 4 for returning (thinning) the output signal of the filter means 3 to a number of signals per unit time equal to the number of samples of the original human input digital signal SO.

The circuit shown in FIG. 1 is inserted, for example, between the HPFII and the coefficient multiplication circuit 16 in FIG. 16(a).

[Effect]

FIGS. 2(a) to 2(d) show frequency spectrum diagrams of the signals in FIG. 1.

FIG. 2(a) shows the frequency spectrum of the human input signal SO for the signal interpolation means 1. Reference sampling frequency f8
The digital input signal S sampled by the clock of
O is interpolated in the signal interpolation means 1 with a clock having a sampling frequency 2f which is multiple times the reference sampling frequency f, in this example, as shown in FIG. 2(b). Therefore, the output signal S of the signal interpolation means 1
The number of 1 is 2 of the input digital signal SO per unit time.
Double. The limiter 2 limits the amplitude of this output signal S1 using the same clock as the signal interpolation means 1. As shown in FIG. 2(c), the energy E2 of the amplitude-limited signal S2 is lower than the initial energy EO. The low-pass filter means 3 passes low frequency components of the amplitude limited signal S2. The output signal S3 from the low-pass filter means 3 is thinned out by a clock having a reference sampling frequency f in the signal thinning means 4, and becomes a signal having the same number of samples as the input signal SO of the signal interpolation means 1 per unit time. The spectrum of the subtracted signal S4 is shown in FIG. 2(d).

The signal interpolation means 1 once interpolates the input signal SO with a clock having twice the sampling frequency 2f to double the number of signals per unit time, and then the limiter 2 is operated. The aliasing distortion component Ed from the sampling clock by the limiter 2 is based on a clock having a double sampling frequency 2f. Therefore, the distortion component Ed falling into the signal component becomes as shown by the broken line in FIG. 2(C) when viewed from the clock interval with respect to the reference sampling frequency f. In other words, most of the distortion components Ed fall into the signal interpolation area, and the distortion components E fall into the original signal head that is not interpolated.
d becomes smaller. The signal thinning means 4 thins out the signal corresponding to the interpolated signal component from among the signals from the low pass filter means 3. This signal is thinned out so as to match the number of input digital signals SOO applied to the signal interpolation means 1 per unit time. As a result, signal components containing a large amount of distortion component Ed are thinned out and removed, and the distortion component Ed that falls into the remaining signal becomes extremely small.

As a result, the nonlinear digital signal processing circuit shown in FIG. 1 can reduce the influence of the aliasing distortion component Ed caused by the limiter 2.

When the number of signal interpolations is increased, the amount of drop in the distortion component Ed can be reduced. Therefore, signal interpolation can be performed using a clock having a sampling frequency that is multiple times the reference sampling frequency f of the input digital signal SO.

In the above circuit, the signal interpolation means 1 and the signal thinning means 4 are basically constituted by switching circuits, and the low-pass filter means 3 is constituted by existing means, so that it does not include expensive circuit elements. [Embodiments] Two embodiments will be described below, illustrating the case where the nonlinear digital signal processing circuit of the present invention is applied to a specific circuit.

FIGS. 3(a) and 3(b) show FIR type nonlinear emphasis circuits 10 and 11R type nonlinear emphasis circuits using the nonlinear digital signal processing circuit of the present invention, respectively.
A de-emphasis circuit 20 is shown, which includes, for example:
The nonlinear emphasis circuit 10 used as the nonlinear emphasis circuit 102 in the recording system and the nonlinear deemphasis circuit 114 in the reproduction system of the high-definition VTR shown in FIG. Signal interpolation circuit (INT)12.
Limiter 13. Low pass filter (LPF)14. Signal thinning circuit (CULL)15. and coefficient multiplication circuit 16
A high frequency signal component increasing circuit 10A consisting of
7, an adder circuit 17 adds the original signal SIO and an increase signal S16 in which the amplitude of the high frequency component of the original signal SIO is increased in the high frequency signal component increase circuit 10A. If the amplitude of the high frequency component of the signal interpolation circuit 12 is greater than a predetermined value, the limiter 13 limits the amplitude to a predetermined value.

The HPFII and signal thinning circuit 15 operate at CLKI having a reference sampling frequency f.

Other circuits 12 to 14 have double sampling frequency 2f
, operates on CL, with 2.

A detailed circuit example of the signal interpolation circuit 12 is shown in FIG. The signal interpolation circuit 12 in FIG. 4 includes data delay holding circuits 121 . Switching circuit 122. The data delay and hold circuit 123 and the adder circuit 124 are connected as shown, and function as a pre-data hold type interpolation circuit, the operating characteristics of which are shown in FIG. The data delay holding circuit 121 uses the signal Sll
is the time corresponding to the reference sampling frequency f5 (CLK
1 minute) and hold. This holding output and ground voltage (0
(2) is alternately switched by the switching circuit 122 at CLK2 with a double sampling frequency of 2f. The data delay holding circuit 123 is the data delay holding circuit 12
The signal is delayed and held by half the clock time (CLK1) of CLK1, that is, by a time corresponding to CLK2. By applying the holding output from the data delay holding circuit 123 and the 0■ voltage to the adding circuit 124 and adding them together, the signal Sll shown as X in FIG. 5 is output at a clock frequency twice that of the signal Sll. ,
That is, the signal between X and X is output as interpolated data shown as ◯.

This doubles the number of data per unit time.

The limiter 13 limits the amplitude of this double interpolated data at CLK2. Therefore, if an aliasing distortion component of the sampling clock occurs, CLK2
The distortion component for (double sampling frequency 2f) is folded back.

FIG. 6 shows a circuit example of the LPF 14. This LPF 14 is an IIR type LPF, including an adder circuit 141, a data delay holding circuit 142. Addition circuit 143 Coefficient multiplication circuit 144 . A coefficient multiplication circuit 145 is connected as shown. The data delay holding circuit 142 is the data delay holding circuit 121 in FIG.
This circuit has the same configuration as . Coefficient multiplication circuit 145
multiplies the signal of the data delay hold circuit 142 by the coefficient β and feeds it back negatively to the adder circuit 141, the adder circuit 143 adds the output of the adder circuit 141 and the output of the data delay hold circuit 142, and the coefficient multiplier circuit 144 adds The amplitude of the output of the circuit 143 is adjusted by a coefficient (1+β)/2. This LPF1
4 cuts high frequency components of the output of the limiter 13 and passes low frequency components. That is, this LPF 14 performs interpolation at a double sampling frequency of 2f in the signal interpolation circuit 12, and excludes unnecessary high frequency components whose amplitude is limited by the limiter 13.

The signal thinning circuit 15 basically consists of a switching circuit that operates on CLKI. That is, the output signal of the LPF 14 is input to the sampling clock CL of the signal interpolation circuit 12.
By switching with a clock CLKl that is half of K2, interpolated signal components containing many distortion components Ed are eliminated.

The output of the signal thinning circuit 15 is multiplied by a predetermined coefficient k by the coefficient multiplication circuit 16 shown in FIG. 3(a) and added to the addition circuit 17 as a high frequency signal increasing component.

FIG. 7 shows another example of the circuit configuration of the signal interpolation circuit 12. The signal interpolation circuit 12 in FIG. 7 performs the linear interpolation shown in FIG. 8, and the data delay holding circuit 121 CLK
In addition to the basic circuit configuration consisting of a switching circuit 122 that switches at 2 times, a coefficient multiplication circuit 125 with a coefficient of 1/2 for linear interpolation, and data delay and hold circuits 126 and 127 having half the delay characteristics of the data delay and hold circuit 121.
, a coefficient multiplication circuit 128 with a coefficient of 1/2. Further, the adder circuit 129 is configured as shown in the figure. The delay characteristics of the data delay and hold circuits 126 and 127 are similar to the data delay and hold circuit 123 in FIG. In this signal interpolation circuit 12 as well, the data delay holding circuit 121 and switching circuit 122 for signal interpolation are the same as those shown in FIG. Circuits 125-129 linearly interpolate signal Sll as shown in FIG. In FIG. 8, X indicates the signal Sll before interpolation, and O indicates the interpolated signal.

FIG. 9 shows yet another circuit configuration example of the signal interpolation circuit 12. This signal interpolation circuit 12 includes a data delay holding circuit 12.
In addition to the basic circuit consisting of the switching circuit 122 and the data delay holding circuits 1201 to 1204 . weighting factor α
0. α1 weight multiplication circuits 1207 to 1210. and,
An adder circuit 1211 is connected and configured as shown. The delay characteristics of the central data delay and hold circuits 1202 and 1203 are similar to the data delay and hold circuit 123 in FIG. Kono circuit 1201-1204.1207-1211
performs one-curve interpolation using a multi-stage filter circuit configuration. By further increasing the number of taps, it is possible to perform more ideal interpolation.

Further, as another example of the circuit configuration of the LPF 14, an FIR transversal type filter is shown in FIG. This LPF1
4 are data delay holding circuits 1401 to 1207. Weighting factor multiplication circuits 1408-1412 and addition circuit 1414 are connected as shown.

The signal interpolation circuit 12 shown in FIGS. 4, 7, and 9 and the filter PF 14 shown in FIGS. 6 and 10 can be arbitrarily selected depending on the signal component to be processed.

Each of these circuits may be constructed as an individual chip component as shown in FIG. 3(a).
The non-linear emphasis circuit IO shown in ) may be configured as an integral unit using, for example, a DSP.

Signal interpolation circuit 12. LPF14. The specific circuit configuration of the signal thinning circuit 15 is not limited to that described above, and various other circuit configurations may be adopted.

The detailed circuit configuration applied to the nonlinear emphasis circuit 10 shown in FIG. 3(a) has been shown above, but FIG.
The de-emphasis circuit 20 in b) can also have the same circuit configuration as described above, taking into account that it is an inverse circuit.

10. A nonlinear emphasis circuit using a nonlinear digital signal processing circuit that reduces the influence of distortion components according to an embodiment of the present invention. and de-emphasis circuit 2
In a VTR using 0, ringing does not occur, and images with stable image quality are provided even if the clock phase changes.

11 to 13 show circuit configurations of modified forms of the nonlinear emphasis circuit 10 of FIG. 3(a).

The nonlinear emphasis circuit IO shown in FIG. 11 is obtained by disposing the HPFII and the signal interpolation circuit 12 in FIG. 3(a) in reverse. Its circuit operation is similar to the nonlinear emphasis circuit 10 of FIG. 3(a). however,
In this circuit configuration, the interpolation signal generation circuits after the switching circuit 122 of the signal interpolation circuit 12, for example, the data delay holding circuits 1201 to 1206 in FIG. Weighting coefficient multiplication circuits 1207 to 1210 and addition circuit 1211
The nonlinear emphasis system shown in FIG. 12 has the advantage that since it basically has a filter circuit configuration, these can be integrated with HPFII, and the circuit configuration of the signal interpolation circuit 12 and HPFII as a whole can be simplified. The circuit 10''' includes an LPF 18 in front of the HPFII in the nonlinear emphasis circuit 10 of FIG. 3(a).
It has been established. In addition, the nonlinear emphasis circuit 10'' in FIG. 13 is the nonlinear emphasis circuit 10'' in FIG. 11 in which an LPF 18 is provided before the hi circuit 12.
By providing 18.

By eliminating the distortion component EdO due to folding back of the double sampling clock CLK2 and the high band component, the -layer distortion component Ed
can be reduced.

Of course, a nonlinear data circuit corresponding to those shown in FIGS. 11 to 13 can be constructed.

The above detailed circuit example is applied to the FIR type non-linear emphasis circuit 10 and the IIR type de-emphasis circuit 20 as shown in FIGS. 3(a) and 3(b). A nonlinear emphasis circuit and a nonlinear deemphasis circuit to which a digital signal processing circuit is applied are shown in Figure 14 (a).
), an IIR type nonlinear emphasis circuit 10, and an FIR type nonlinear deemphasis circuit 20, as shown in FIG. 14(b). Alternatively, a combination of these can be used.

High frequency signal component increasing circuit 10A in FIG. 14(a)
shows a circuit equivalent to the high-frequency signal component increase circuits 10A to 10A"' shown in FIG. 3(a) and FIGS. 11 to 13 described above.The signal reduction circuit 2 in FIG.
The same applies to OA.

The above-mentioned example shows that it would be difficult to use CLK2 having a sampling frequency 2f, which is twice the reference sampling frequency f, for the signal interpolation and subsequent signal processing. It is possible to use a clock with a sampling frequency of . −
In boat fishing, increasing the sampling frequency and increasing the number of interpolated data increases the effect of reducing distortion components, but increases the signal processing speed.

As a specific example of application of the non-linear digital signal processing circuit of the present invention, we have described the case where the non-linear digital signal processing circuit of the present invention is applicable to a non-linear emphasis circuit and a de-emphasis circuit in a high-definition VTR.・Not limited to application to emphasis circuits and non-linear de-emphasis circuits, but also non-linear and de-emphasis circuits in one communication system.
Needless to say, it is applicable to emphasis circuits and nonlinear de-emphasis circuits.

Furthermore, the non-linear digital signal processing circuit of the present invention can be applied to these non-linear emphasis circuits and non-linear digital signal processing circuits.
In addition to being applied to de-emphasis circuits, the present invention can also be applied to various other digital signal processing circuits that have limiters and whose purpose is to reduce the influence of distortion components, such as echo cancellers, or to Needless to say, it can be applied to nonlinear digital signal processing circuits themselves.

[Effects of the Invention] As described above, the nonlinear digital signal processing circuit of the present invention can reduce distortion components caused by limiters without using expensive circuit elements.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a nonlinear digital signal processing circuit according to the present invention. FIGS. 2(a) to (d) are signal waveform diagrams in FIG. 1. FIGS. 3(a) and (b) are nonlinear digital signal processing circuits according to the present invention. FIG. 2 is a circuit diagram as a first embodiment in which the processing circuit is used as a non-linear emphasis circuit and a non-linear de-emphasis circuit. FIG. 4 is a detailed circuit diagram of a first embodiment of the digital signal interpolation circuit shown in FIG. 3(a). FIG. 5 is a graph showing the signal processing operation of the digital signal interpolation circuit of FIG. 4. Figure 6 shows the first part of the low-pass filter in Figure 3(a).
7 is a detailed circuit diagram as a second embodiment of the digital signal interpolation circuit in FIG. 3(a). FIG. 8 shows the signal processing operation of the digital signal interpolation circuit in FIG. 7. Graph FIG. 9 is a detailed circuit diagram as a third embodiment of the digital signal interpolation circuit in FIG. 3(a). FIG. 10 is a detailed circuit diagram of a second embodiment of the low-pass filter in FIG. 3(a). FIGS. Circuit diagram as the fourth embodiment FIG. 14(a),
(b) is a block diagram of a non-linear emphasis circuit and a non-linear de-emphasis circuit as a modification of FIGS. 3(a) and 3(b). FIGS. 15(a) and 15(b) are configuration diagrams of a signal recording processing system and a signal reproduction processing system of a VTR to which the nonlinear digital signal processing circuit of the present invention is applied. Figures 16(a) and (b) are shown in Figures 15(a) and (
FIGS. 17(a) and 17(b) are graphs showing the signal processing in FIG. 16(a). (Explanation of symbols) 1...Signal interpolation means 2...Limiter means. 3 ・ ・ 4 ・ ・ 10 ・ ・ 10A ・ 11 ・ ・ 13 ・ ・ 15 ・ ・ 16 ・ ・ l 7 ・ ・ 20 ・ ・ 2OA ・ 21 ・ ・ 23 ・ ・ 24 ・ ・ 26 ・ ・ 27 ・ ・ ・Low pass filter Means/Signal thinning means/Non-linear/emphasis circuit/High frequency signal component increasing circuit/HPF, 12...Signal interpolation circuit/Limiter 14...LPF/Signal thinning circuit.・Coefficient multiplication circuit 3 ・Addition circuit, 1 day...LPF ・Nonlinear de-emphasis circuit.・High frequency signal component reduction circuit. -Addition circuit, 22...HPF.・Signal interpolation circuit.・Limiter, 25...LPF.・Signal thinning circuit.・Coefficient multiplication circuit.

Claims (1)

[Claims] 1. In a circuit that processes a digital signal and includes a limiter that limits the signal amplitude, in a stage before the limiter, an input digital signal is interpolated into a signal whose number of samples is multiple times the number of samples per unit time. filter means for passing low frequency components of the output of the limiter, and means for thinning out the output of the filter means into a number of signals equal to the number of samples before interpolation per unit time. A nonlinear digital signal processing circuit characterized by comprising: