JP3039606B2 - Frequency conversion circuit and digital camera integrated VTR - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit and a digital camera-integrated VTR.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional analog camera integrated VT.
R is a block diagram, and FIG. 5 is a conventional digital camera integrated type V
It is a block diagram of TR. Hereinafter, a conventional technique will be described with reference to the drawings. In FIG. 4, a camera-integrated VTR
Is composed of a camera section A and a deck section B. A CCD (solid-state imaging device) 1 driven by a first clock signal CK1 in the camera unit A supplies a video signal obtained by converting imaging light into an electric signal to a camera signal processing unit 2, where a gamma signal is output. The analog video signal 2a is obtained by performing known signal processing such as correction.

Next, in the deck section B, the analog video signal 2a is separated into a luminance signal and a chrominance signal by the analog recording / reproducing processing means 3, and the respective signals are subjected to predetermined processing. To generate a recording signal.
Is recorded on the magnetic tape 5. At the time of reproduction, the reproduction signal reproduced from the magnetic tape 5 by using the magnetic head 4 is subjected to a predetermined analog reproduction process to reproduce the reproduction video signal a.
a is generated.

As described above, an analog camera-integrated VTR
Since the signal processing after CCD1 is performed in analog, the first clock signal CK1 may be set in any manner as long as the band of the output signal of CCD1 can be secured.
There was a CD.

On the other hand, with the progress of digitization of video, a digital camera integrated VTR is also being developed. As shown in FIG. 5, the camera-integrated VTR converts an output signal of the CCD 1 into a digital signal via an A / D converter 6, and then performs predetermined digital signal processing by a digital camera signal processing means 7. The digital video signal 7a is generated.

The digital video signal 7a is digitally processed by analog signal processing by the digital recording / reproducing processing means 8 and is also subjected to digital signal processing such as compression of video information and addition of an error correction code. After that, a predetermined digital modulation is performed to generate a recording signal, and the recording signal is recorded on the magnetic tape 5 using the magnetic head 4. At the time of reproduction, a predetermined analog reproduction process is performed on a reproduction signal reproduced from the magnetic tape 5 using the magnetic head 4 to generate a reproduction video signal aa.

As described above, the video signal is recorded and reproduced also in the digital camera integrated type VTR. However, since the digital signal processing is constituted by a synchronous system, the first clock signal CK1 supplied to the CCD 1 is A / D Converter 6, digital camera signal processing means 7, digital recording / reproducing processing means 8
Is also supplied.

[0008]

However, the clock signal used for digital recording / reproducing processing is 13.5 MHz (858) in consideration of compatibility with the conventional commercial VTR.
fh), there is a disadvantage that the CCD 1 is limited to one that can be driven at 13.5 MHz. As a result, there has been a problem that a high-reliability and inexpensive CCD cannot be used, which has been conventionally used in a large amount in a consumer analog camera integrated VTR.

Therefore, an object of the present invention is to provide a frequency conversion circuit between a camera section and a deck section to solve the above-mentioned problems.

[0010]

SUMMARY OF THE INVENTION The present invention provides the following structure to solve the above problems.

According to a first aspect of the present invention, there is provided a frequency conversion circuit for frequency-converting input video data synchronized with a first clock signal into output video data synchronized with a second clock signal. A low-pass filter for generating intermediate image data at an intermediate point between the input image data and the intermediate image data,
An interpolation circuit that performs linear interpolation at sample points synchronized with the second clock signal to generate output video data.

According to a second aspect of the present invention, there is provided a solid-state imaging device which converts imaging light into an electric signal and is driven by a first clock signal, and outputs the first clock signal to the output of the solid-state imaging device which has been converted into a digital signal. Digital camera signal processing means for performing predetermined signal processing by using the digital camera signal processing means, and the output of the digital camera signal processing means synchronized with the first clock signal as input video data, and the output video data synchronized with the second clock signal At least a frequency conversion circuit for performing frequency conversion on the output video data, and digital recording processing means for performing a predetermined recording process on the output video data using the second clock signal and recording the output video data on a recording medium. A digital camera-integrated VTR characterized in that it is a frequency conversion circuit according to the invention.

[0013]

FIG. 1 is a block diagram of a digital camera-integrated VTR to which the present invention is applied, FIG. 2 is a conceptual diagram for explaining the operation of the frequency conversion means, and FIG. 3 is a block diagram of the frequency conversion means. Embodiments will be described below with reference to the drawings.
It is to be noted that the same components as those in FIG.

FIG. 1 differs from FIG. 5 in that a second clock signal CK2 having a frequency different from that of the first clock signal CK1 is used as a clock signal for driving the digital recording / reproducing processing means 8 in the deck section B. The point is that the frequency conversion means 10 is interposed between the camera section A and the deck section B.

The principle of operation of this frequency conversion means 10 is shown in FIG.
This will be described with reference to FIG. The curve in FIG.
a is a signal waveform to be represented, and input data Y0, Y2, Y4,... Y2m represented by black circles (m is an integer of 0 or more)
Is the digital video signal 7a and the first clock signal C
It exists every K1 sample period Ta (for example, 1 / 910fh). On the other hand, the output data y1, y2,
... ym is the output signal 10a and the second clock signal C
It exists every K2 sample periods Tb (for example, 1 / 858fh).

First, input data Y0, Y2, Y4,.
The intermediate value data Y1, Y3,... Y2m + 1 representing the intermediate value of each data is generated by a digital low-pass filter based on 2m (illustrated by triangles in the figure). The reason why the intermediate value data is generated is to improve the accuracy of the subsequent linear interpolation.

Next, output data is generated by performing linear interpolation based on the input data and the intermediate value data. In this regard, the output data y1, y2,... Ym are obtained by the following equations.

Y1 = Y3 × k1 + Y2 × (1-k1) =
k1 × (Y3-Y2) + Y2 y2 = Y5 × k2 + Y4 × (1-k2) = k2 × (Y5
−Y4) + Y4

That is, generally, when m ≧ 1, ym = km × (Yn + 1−Yn) + Yn, where Yn + 1 and Yn are data adjacent to ym,
n ≧ 2. Further, km is a decimal part with respect to an integer part (ka) of the following equation. When ka + km = {Tb / (Ta × 2)} × m m = 0 , y0 = Y0

Further, what kind of input data, intermediate value data and output data are generated based on the constant km within one horizontal scanning period is determined by the first and second clock signals CK1 and CK2.
Since it is determined by the relationship of the frequency of CK2, ROM
Can be read out at a predetermined timing and used.

Now, a specific circuit configuration of the frequency conversion means 10 will be described with reference to FIG. Camera section A
Digital signal 7a (input data) supplied from
Generates the above-described intermediate value data by the digital low-pass filter 101 and supplies the intermediate value data to the first delay means 102 together with the input data.

The data delayed by the first delay means 102 for a predetermined period of time in clock units is further delayed by the second delay means 103 for a predetermined time in units of clock periods. The outputs of the first and second delay means 102 and 103 are supplied to one input of multipliers 104 and 105, respectively.
The output (constant km, 1-km) from the ROM 106 supplied to the other input is multiplied at a predetermined timing. The outputs of the multipliers 104 and 105 are added to an adder 107.
Is supplied to the D flip-flop 108, latched by the second clock signal CK2, and becomes an output signal 10a (output data).

As described above, since the output data can be obtained by converting the sampling frequency of the input data, the frequency of the clock signal of the camera unit A and the frequency of the clock signal of the deck unit B can be made different. A conventionally used CCD can be used.

In the above embodiment, the ROM 10
6. Constant km, 1-km to correspond to a plurality of CCDs
May be stored, and a predetermined constant may be read by changing the read address in accordance with the type of CCD.

In the embodiment described above, the first and second
Although the clock signals CK1 and CK2 have been described as having independent frequencies, they may of course be synchronized by PLL means (not shown).
In such a case, there is an advantage that the output of the adder 107 can be reliably latched by the D flip-flop 108 in FIG.

[0026]

As described above, according to the configuration of the frequency conversion circuit of the present invention, a low-pass filter for generating intermediate video data at an intermediate point between adjacent sample points of input video data, An interpolation circuit that performs linear interpolation at sample points synchronized with the second clock signal based on the intermediate video data to generate output video data, so that the video data can be converted between different sampling frequencies. In particular, since the intermediate video data is generated, the accuracy of the output video data can be improved.

According to the structure of the digital camera-integrated VTR according to the present invention as described above, the second clock signal used for digital recording processing and the first clock signal used for driving the solid-state imaging device are different. It can be compatible with the digital recording process of the conventional professional VTR, and has been integrated
Highly reliable and inexpensive C used in large quantities in TR
There is an effect that a CD can be used.

[Brief description of the drawings]

FIG. 1 is a digital camera-integrated VTR to which the present invention is applied.
It is a block diagram of.

FIG. 2 is a conceptual diagram for explaining the operation of a frequency conversion unit.

FIG. 3 is a block diagram of a frequency conversion unit.

FIG. 4 is a block diagram of a conventional analog camera integrated VTR.

FIG. 5 is a block diagram of a conventional digital camera integrated VTR.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CCD (solid-state image sensor) 7 Digital camera signal processing means 5 Magnetic tape (recording medium) 8 Digital recording / reproducing processing means (digital recording processing means) 10 Frequency conversion means (frequency conversion circuit) 101 Low-pass filter (digital low-pass filter) 7a Input data (input video data) 10a Output data (output video data) CK1 First clock signal CK2 Second clock signal

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masanori Kubota 3-12-12 Moriyacho, Kanagawa-ku, Yokohama-shi, Kanagawa Japan Investigator in Japan Victor Co., Ltd. Akira Suzuki (56) References JP-A-6-217326 (JP, A JP-A-5-244625 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 5/782-5/783 H04N 5/225 H04N 5 / 335

Claims (2)

(57) [Claims] 1. A frequency conversion circuit for frequency-converting input video data synchronized with a first clock signal to output video data synchronized with a second clock signal, comprising: an intermediate point between adjacent sample points of the input video data. A low-pass filter for generating intermediate video data, and an interpolation circuit for performing linear interpolation at sample points synchronized with the second clock signal based on the input video data and the intermediate video data to generate output video data. A frequency conversion circuit comprising: 2. A solid-state imaging device that converts imaging light into an electric signal and is driven by a first clock signal;
Digital camera signal processing means for performing predetermined signal processing using the clock signal of the above, and an output of the digital camera signal processing means synchronized with the first clock signal as input video data, and synchronized with a second clock signal. At least a frequency conversion circuit for frequency-converting the output video data, and digital recording processing means for performing a predetermined recording process on the output video data using the second clock signal and recording the output video data on a recording medium; A digital camera-integrated VTR, comprising the frequency conversion circuit according to claim 1.