JPS60111581A - Processor of still picture signal - Google Patents

Abstract

PURPOSE:To lower the data rate of the output read from a memory than the rate of an input signal and to remove the required noise components in a short time by weighted-averaging the signal read from the frame memory in which an input digital still picture signal is written and the input signal. CONSTITUTION:A still picture is image-pick-up by a color video camera 1, and converted to a composite color video signal of an NTSC system by a color encoder 2. The signal is digitized by an A/D converter 3, and supplied to a signal processor 4. Noise removing and conversion of the data rate are executed, and the signal is supplied to a still picture file 5. The signal from a digital still picture input terminal 1 of the circuit 4 is multipled by 1-K times by a counter 12, and added to an adder 13. The output of the counter 12 is added to a frame memory 17 through a switch circuit 14. The output which is read from the memory 17 is multipled by K times by a counter 24, and is added to the adder 13. The weighted average between the read signal and the input signal is obtained, and the required noise is removed for a short time.

Description

Detailed Description of the Invention "Field of Industrial Application" The present invention relates to a still image signal processing device that is applied when recording still image signals obtained from an input device such as a video camera to a still image file device. Regarding.

"Background technology and its problems" It is possible to store still images (natural images, documents, etc.) using recording media capable of recording large amounts of data, such as magnetic tapes, magnetic discs, and optical discs. There are known still image file devices that can. In still image file devices, digitizing and recording still image signals is more advantageous than analog recording in terms of high-density recording.

However, the digital still image signal obtained by digitizing the output signal of a video camera has a high data rate, and there is a problem in that it exceeds the data transmission capacity of the recording/reproducing device if left as is. Also.

Reducing noise contained in a digital still image signal is desirable from the viewpoint of ensuring high quality still images to be filed.

``Object of the Invention'' Therefore, an object of the present invention is to reduce the data rate of an input digital still image signal and to reduce the noise of a manually generated digital still image signal, and to perform both using a common frame memory. An object of the present invention is to provide a still image signal processing device that enables the processing of still image signals.

``Summary of the Invention'' The present invention is a still image signal processing device that records an input digital still image signal of standard data rate 1 on a still image recording device.

The present invention includes a frame memory into which an input digital still image signal is written, a circuit that performs noise removal by weighted averaging of the digital still image signal read from the frame memory and the input digital still image signal, and A still image signal comprising: a circuit for lowering the data rate of the read output from the memory than the data rate of the input digital still image signal; and a circuit for switching between a noise removal operation and a data rate conversion operation. This is a processing device.

"Embodiment" An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of a still image recording system to which the present invention is applied.

In FIG. 1, reference numeral 1 denotes, for example, a single-tube color video camera for photographing still images, and its output is supplied to a color encoder 2, where it is converted into an NTSC system full-color video signal. This composite color video signal is supplied to the A/D converter 3, and 4 fsc
(fsc: color subcarrier frequency), 13.
For example, 1
The samples are digitized to 8 bits. This A
The digital color video signal at a standard data rate from the /D converter 3 is supplied to a signal processing device 4 to which the present invention is applied, and the signal processing device 4 performs noise removal and data rate conversion. A digital still image signal with a lower sampling rate is obtained from the signal processing device 4. This digital still image signal is supplied to the still image file device 5 and recorded on a recording medium such as a magnetic tape, magnetic sheet, or optical disk.

FIG. 2 shows an example of a signal processing device 4 to which the present invention is applied. In Figure 2, the input terminal indicated by 11 has an A/D
A digital still image signal from the converter 3 is supplied,
This digital still image signal is converted into (1,=
K) (K is a constant, 0<K<1) and is supplied to the adder 13. The output signal of this adder 13 is supplied to one input terminal 15 of a switch circuit 14. No input signal is supplied to the other input terminal 16 of the switch circuit 14.

One frame of the digital still image ffl appearing at the output of the switch circuit 14 is written into the frame memory 17. The frame memory 17 consists of a RAM with a capacity capable of storing still image data for 17 L/-m, an address generation circuit, and a memory control circuit. One input terminal 19 of the switch circuit 18 has a
A clock CK is supplied from a terminal 21, and a clock CK2 is supplied from a clock generation circuit 22 to the other input terminal 20. The clock CKI is the same as the sampling clock used for digitization in the A/D converter 3, and the clock CK2 has a frequency equal to the sampling rate of recording data determined by the still image file device 5. .

The frequencies of clocks CK+ and CK2 are set to north and f
2, the relationship is (f,>f,,).

The digital still image signal read from the frame memory 1γ is taken out to the output terminal 23, multiplied by the coefficient multiplier 24, and supplied to the adder 13. Output terminal 25
A clock CK2 is led to the clock CK2, and a clock CI(2) as a timing reference signal and a digital still image signal with a low cheater ray 1 are supplied to the still image capture device 5. Alternatively, a clock generated inside the still image file device 5 may be supplied to the signal processing device 4.

The above-described signal processing device 4 constitutes a cyclic noise resolution user in a state where the switch circuits 14 and 18 select the input terminals 15 and 19, respectively, as shown in the figure. In this state, the output of the signal processing device 4 is not recorded by the still image file device 5.

A noise reducer performs noise removal by taking advantage of the fact that signal components are the same among a plurality of frames, whereas noise has no correlation between frames. The noise removal operation of this embodiment will be explained. The signal amplitude of the digital still image signal supplied to the input terminal 11 is S
Then, frame time T1. The signal amplitude during the output of the frame memory 17 at each of T, . . . , T1 is:
It will be as shown below.

T, : (1-K) S T2 : (I K ) S 10K (I K ) 5
111q: (1-K)S+K(1-K)S+K(1-
K) STi: (1-K) (1++K”-1-0
-1-K(.-1)18 Therefore, if (1→OO'), then the signal amplitude is multiplied by 1 and taken out as an output.

Assuming that the noise power included in the digital still image signal supplied to the input terminal 11 is N, the noise power being output from the frame memory 17 is calculated at frame times T, , T2 .・、
Each of T1 is as shown below.

T,: (1-K)2N T2: (I K)2N Ten to 2 (1-K)2NT
3: (I K) N+ to 2 (1-K) 2N 10 K'
(I I()NTi: (i K )”(1+ K”+
K“”−・10Kz(1−+ ))N Therefore, (i
-+C/) ), then the noise power is (1-K)
2.Z-2.N-ConcaveN1-10K (0<K<1), so a digital still image signal with reduced noise components can be obtained as the output of the frame memory 17. . In this way, after noise removal, the switch circuits 14 and 18 are connected to the input terminals 16 and 2.
The state can be changed to select 0. One frame of digital still image signals read from the frame memory 17 by the clock CK2 is supplied to the still image file device 5 together with the clock CK2, and recorded on the recording medium.

FIG. 3 shows another embodiment of the invention. Similar to the previous embodiment, the coefficient multiplier 12.24 and the frame memory 17
A noise reducer is configured, and the switch circuit 18 switches the clock supplied to the frame memory 17, noise is removed, and the digital still image signal whose data rate is lowered is sent to the still image file device 5. recorded. In another embodiment shown in FIG. 3, a switch circuit 26 is provided having three input terminals 27, 28, 29,
The digital still image signal sent through the frame memory 11
will be written to.

The digital still image signal from the input terminal 11 is supplied as is to the first input terminal 27 of the switch circuit 26.
Its second input terminal 28 is supplied with the output signal of the adder 13, and its third input terminal 29 is supplied with no signal, for example. During a noise removal operation in which a clock CKI synchronized with the input digital still image signal is supplied, the first input terminal 27 is selected for the first frame, and the next one is selected.

From frames onwards, the second input terminal 28 is selected.

Then, when the noise removal is completed, the third input terminal 29
is selected, and the digital still image signal read out from the frame memory 1γ by the clock CK2 is recorded by the still image file device 5.

The noise removal operation in this other embodiment will be explained in the same manner as in the previous embodiment. First, frame memory 17
The signal amplitude during the output of frame time T1. T2.・・・
, TI are as shown below.

T□: S T2: (1-K)≦10KS = S r1: (1-K) S10K (1-K) 2S = ST in S+
i: S, the signal amplitude is always the input amplitude S.

Further, the noise power being output from the frame memory 17 is as shown below at each of the frame times T, , T2, . . . , T1.

T□:N T2: (1-K)2N0 to 2N T3: (1-K)2N-1- to 2 ((1-K)2
N ten to 2NITi: (1-K)” (1+ to 2+
K'10・102(i −2)) N”−K2(i −1
−)N (However, 1≧2) Therefore, (i−+c/)
), the noise power is as follows, and noise can be removed.

In comparison with the noise removal operation of the above-mentioned embodiment, in this other embodiment, the noise is removed by setting the input digital still image signal that is not passed through the coefficient unit 12 as an initial value in the frame memory 11 at its it stage. At any frame time in which an operation is performed, the signal amplitude in the output signal can be multiplied by 1, ie, the input amplitude. In this invention, which handles still image signals,
Since there is no need to consider blurring in the "motion" portion, it is possible to increase the value of K and shorten the time required for noise reduction. However, when K is increased, the configuration of the above-mentioned embodiment has a problem in that it takes a long time for the signal amplitude to become equal to the input amplitude.

In this other embodiment, even if the value of K is increased, the signal amplitude is always equal to the input amplitude, and the time required to achieve the desired noise removal can be shortened.

"Effects of the Invention" The present invention can output a digital still image signal with reduced noise and a low data rate that is compatible with the transmission capacity of the recording device. According to the present invention, noise removal and data rate conversion can be performed using a common frame memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a still image recording system to which this invention can be applied, FIG. 2 is a block diagram of one embodiment of this invention, and FIG. 3 is a block diagram of another embodiment of this invention. It is. 4. Signal processing device, 11.. Digital still image signal input terminal, 14, 18.26--
・−・Switch circuit, 17・・・・・・−・Frame memory. Agent Masato Sugiura

Claims (1)

[Scope of Claims] ill A still image signal processing device configured to record an input digital still image signal at a standard data rate in a still image recording device, comprising: a frame memory into which the input digital still image signal is written; A circuit that removes noise by weighted averaging the digital still image signal read out from the frame memory and the input digital still image signal; 1. A still image signal processing device comprising: a circuit for reducing the data rate; and a circuit for switching between the noise removal operation described in 1. and the data rate conversion operation described in 1. (2. In the still image signal processing device according to claim 1, the input digital still image signal is written into the frame and memory as one of the initial values during the noise removal operation. A still image signal processing device characterized by: