JP2693841B2 - Digital signal processing circuit and magnetic recording / reproducing apparatus - Google Patents

Description

The present invention relates to a digital signal processing circuit, and more particularly to a digital video signal separation / noise suppression circuit and a magnetic recording / reproducing apparatus (VTR) to which the circuit is applied.

[Prior Art] Recently, technological development for improving image quality by digital signal processing of image signals has been advanced in response to consumers' needs for improving image quality of TVs and VTRs.

As one of such technologies, there is one that uses a digital comb-shaped filter. For example, radio technology "VIDEO TECHNI
CAL REPORT NO.54 ”[8] (1984) Sakamoto, Minakami P153-15
There are six.

The content thereof is a circuit in which a magnetic chrominance reproducing means of a recording system and a chromaticity signal S / N improving means of a reproducing system are realized by digital signal processing in a magnetic recording / reproducing apparatus by low frequency conversion chromaticity signal processing. Its main structure is as follows. First, the composite video signal input to the recording system is digitalized using one A / D converter, and then separated into a luminance signal and a chromaticity signal by digital signal processing, and two D / A converters are used. Each will be converted to analog. On the other hand, in the reproduction system, the reproduction chromaticity signal is input and digitized by the above A / D converter. This signal is subjected to S / N improvement processing by a circuit which also serves as a part of the digital signal processing circuit for luminance / chromaticity separation described above.
Then, similarly, one of the two D / A converters described above is used for analogization.

That is, the above-mentioned conventional example has a configuration in which a digital signal processing circuit with 1 input and 2 outputs and a digital signal processing circuit with 1 input and 1 output are also used.

[Problems to be Solved by the Invention] Therefore, in this circuit, when operating as a digital signal processing circuit with one input and two outputs, one A / D converter and two D / A converters are used, When operating as a 1-input 1-output digital signal processing circuit, only one of the above A / D converter and D / A converter is used. Other unused D / A converters are not considered and expensive D
There was a problem when the / A converter was not used effectively.

It is an object of the present invention to effectively utilize a D / A converter which is not used in a 1-input 1-output digital signal processing circuit when the digital signal processing circuit of the prior art is also used.

Further, although signal delay may occur due to digital signal processing, it is another object of the present invention to provide a circuit having good compatibility with peripheral analog circuits even in such a case.

[Means for Solving the Problems] A digital signal processing circuit of the present invention is a separation processing means for separating an A / D-converted input signal into two separation signals. A delay processing means for outputting a delay signal obtained by applying the same amount of delay processing as the delay time required for the processing of the signal processing means to the output signal together with the output signal processing means, the two separated signals, the processed signal and the delay It is provided with a switching means for switching a signal and outputting it to two D / A converters.

Further, in the digital signal processing circuit of the present invention, the separation processing means performs Y / C separation of the composite video signal, and the signal processing means performs S / N improvement of the luminance signal.

A magnetic recording / reproducing apparatus of the present invention includes the digital signal processing circuit in which the composite video signal is a recording signal and the luminance signal is a reproducing signal.

[Operation] The digital signal processing circuit of the present invention can separate an input signal into two separated signals and can output a signal having no delay time difference from a signal obtained by signal processing the input signal.

In the magnetic recording / reproducing apparatus of the present invention, together with the recording luminance signal and the recording chromaticity signal obtained by separately processing the recording composite video signal,
A reproduced S / N improved luminance signal obtained by improving the reproduced luminance signal by S / N and a reproduced luminance signal having no delay time difference from the reproduced S / N improved luminance signal can be obtained.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention. In the figure, 26 is an A / D converter for converting an input analog signal into a digital signal, 1 is a separation processing circuit for separating one input signal into two output signals by digital signal processing, and 2 is an arbitrary one-input one-output A signal processing circuit for performing digital signal processing, 3 is a delay processing circuit for delaying an input digital signal, 21 and 22 are multiplexers for switching and outputting two digital signals (hereinafter abbreviated as MPX), and 27 and 28 are input digital signals. Is a D / A converter that converts the analog signal into an analog signal.

Hereinafter, the operation of the present embodiment will be described. The analog input signal In is input to the A / D converter 26 and outputs a digital signal In '. When the separation processing of the composite input signal is performed, the input signal In ′ is input to the separation processing circuit 1 and two output signals S ₁ and
It is separated into S ₂ . The separated signals S ₁ and S ₂ selected by the MPXs 27 and 28 are converted into analog signals by the D / A converters 27 and 28, and output as separated output signals Out1 and Out2.

On the other hand, when the non-composite signal requires a predetermined signal processing, the input signal In ′ is input to the signal processing circuit 2 and output as the output signal T. Further, the input signal In ′ is input to the delay processing circuit 3 and subjected to the same delay processing as the time required for the processing of the signal processing circuit 2 to output the output signal D. The output signals T and D are selected by the MPXs 21 and 22 and analogized by the D / A converters 27 and 28, respectively, to obtain the output signals Out1 and Out2.

As described above, when the separation processing of the composite signal and the one-output signal processing of the non-composite signal are required, the signal T subjected to the signal processing and the signal D not subjected to the signal processing are simultaneously obtained according to the present embodiment. In addition, there is no delay time difference between the two signals.

Generally, there may be a time delay in the signal processing process,
In that case, there is no problem if only the signal processed by the subsequent circuit is required, but if unprocessed signals are also required, the delay time between both signals must be adjusted again. In the present embodiment, the output signals S ₁ and S ₂ of the composite signal separation processing circuit 1 are D / A.
Since the D / A converters 27 and 28 for conversion are commonly used as the D / A converters for the processed output signal T of the non-composite signal and the delayed output signal D, it is not necessary to provide an expensive circuit element separately, A consistent output signal can be obtained.

FIG. 2 shows a concrete example of the digital signal processing circuit according to the first embodiment of the present invention.

This circuit constitutes a transversal type digital filter, and 301 to 306 are delay circuits consisting of shift registers which transfer the input digital signals according to the given clock, and the input signal is multiplied by k times from 75 to 81. In the coefficient unit, 75 and 81, 76 and 80, 77 and 79 have the same coefficient. 41 to 46 are adders, and 47 is a subtractor.

 Next, the operation will be described.

The input signal In ′ is sequentially delayed by the shift registers 301 to 306. The respective output signals are multiplied by a predetermined coefficient by the coefficient multipliers 75 to 81. Further, the output signals of the coefficient units are sequentially added by the adders 41 to 46 to obtain the output signal S ₂ . The output signal S ₂ has a group delay time corresponding to the delay processing of the delay circuits 301 to 306, and is a time-symmetrically weighted signal. As described above, the coefficients of the coefficient unit are arranged symmetrically with respect to the coefficient unit 78. Therefore, assuming that the delay times of the delay circuits 301 to 306 are the same, the addition to the input signal In ′ is performed. The signal having the same delay time as the group delay time of the output signal S ₂ is the signal D output from the delay circuit 303. Therefore, when the signal S ₂ is subtracted from the signal D by the subtractor 47, it is possible to obtain the signal S ₁ having the characteristic opposite to that of the signal S ₂ . For example, here the coefficient unit 75
If the coefficients from to 81 are selected so as to have the band stop type filter characteristic, the signal S ₁ will be processed by the band pass type filter. That is, the signals S ₁ and S ₂ are separated output signals obtained by separating one signal into two signals having different characteristics in a predetermined frequency range. On the other hand, when only the band stop type filter characteristic is required, only the band stop signal S ₂ is D / A converted and output. Therefore, switching from the band pass signal S ₁ to the remaining D / A converter, the delay signal D
When D is converted to analog and output, there is no delay time difference between the band stop signal S ₂ and the delay signal D,
It is possible to form a circuit configuration having high compatibility with the peripheral circuits described above and wide applicability.

As can be seen from the above description, it is not necessary that the separation processing circuit, the signal processing circuit, and the delay processing circuit in the first embodiment be independent circuits. Further, according to the specific example shown in FIG. 2, the signal S ₁ and the signal T in FIG. ₁ are commonly output, and in this case, the MPX 21 in FIG. 1 is not necessary. Similarly, MPX22 may not be necessary. In this specific example, a digital signal processing circuit filters the input digital signal In ′ in parallel with a circuit for separating the input digital signal In ′ into two signals S ₁ and S ₂ having mutually opposite characteristics. It consists of a processing circuit that outputs ₂ and a delay circuit that outputs a delayed signal D. By switching and outputting the output signals, the two D / A converters are effectively used and the latter stage circuit It is a highly versatile processing circuit for connection with.

FIG. 3 is a circuit block diagram showing a second embodiment which is an application example when the input signal In is a video signal in the first embodiment.

This embodiment is a Y / C separation circuit for separating the composite video signal into a luminance signal (Y) and a chromaticity signal (C) as the separation processing circuit in the first embodiment, and an S / S of the luminance signal Y as a signal processing circuit. It is composed of a luminance S / N improving circuit for improving / N. Since the other elements are the same as those in the first embodiment, the corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

When the analog input signal In is a composite video signal, it is digitalized by the A / D converter 26 and then input to the Y / C separation circuit 10 and separated into a luminance signal Y and a chromaticity signal C. Y and C are selected by MPX21 and 22, and D / A converters 27 and 28
When the input signal is the luminance signal Y, after being analogized by
It is input to the luminance S / N improvement circuit 20 and the delay processing circuit 3. The luminance S / N improving circuit 20 improves the S / N of the luminance signal to obtain an improved luminance signal Y '. Further, the delay processing circuit 3 delays by the same amount as the delay time required for the processing of the luminance S / N improving circuit 20 to obtain the delay signal Yd. The output signals Y'and Yd are selected by the MPXs 21 and 22, and then converted into analog signals by the D / A converters 27 and 28 and output externally.

Next, specific examples of the Y / C separation circuit 10 and the luminance S / N improvement circuit 20 will be described with reference to FIGS. 4 to 6 and FIGS.

FIG. 4 (a) shows a simple Y / C separation circuit composed of a comb filter (hereinafter abbreviated as LCMF) using a line delay means.

In the figure, 66 is a band-pass filter (hereinafter abbreviated as BPF) that separates and extracts the frequency band in which the chromaticity signal is interleaved with the luminance signal, and 33 is the BPF 66 input composite video signal.
A delay circuit (hereinafter abbreviated as DL) that performs the same amount of delay processing as the delay time required for Cm filtering processing, 31 is 1
Line delay circuits (hereinafter abbreviated as 1HDL), 48 and 49 are subtractors.

Next, the operation will be described. The input composite video signal Cm is input to the BPF 66 to obtain an extraction signal Bs obtained by separating and extracting the interleaved frequency band of the chromaticity signal. The signal Bs is input to the 1HDL31 to obtain the extracted delay signal Bsh which is subjected to the 1-line delay processing. Since the phase of the chromaticity signal C is inverted for each line, the chromaticity signal C is obtained by subtracting the extraction delay signal Bsh from the extraction signal Bs by the subtractor 48 to eliminate the luminance signal included in the pass band. .

On the other hand, the input composite video signal Cm is input to the DL33 and the BPF66
Obtain the delayed signal that has been delayed by the same amount as
And the delay time are matched, and the chromaticity signal C is subtracted from this delay signal to obtain the luminance signal Y. This example is a Y / C separation means that utilizes the strong correlation of chromaticity signals between the signals of two adjacent lines. However, if there is no correlation of chromaticity signals, the chromaticity signals cannot be extracted. In addition, there is a problem that the luminance signal remains.

Therefore, depending on the presence / absence of line correlation in the Y / C separation circuit shown in FIG. 4 (a), if there is line correlation, LCMF is used.
Y / C separation processing is performed, and when there is no line correlation, Y / C separation processing by LCMF is not performed to prevent color dripping, and only the separation and extraction processing of the band in which the color signals are interleaved is improved. An example of such a Y / C separation means is shown in FIG. 4 (b). The method for determining the presence or absence of line correlation in the input composite video signal of this improved example is to examine the magnitude relationship between signals of adjacent lines in the band in which the chromaticity signal is superposed, and recognize the signal change pattern from this magnitude relationship. The correlation pattern is determined by the change pattern.

In the figure, 38 and 39 are phase inverters, and 40 is the input signal 1/2
1/2 coefficient multiplier that multiplies by, 60, 61, 62 are the input signals,
The minimum value circuit (hereinafter abbreviated as MIN circuit) that outputs the smaller one, 63, 64, 65 is the maximum value circuit (hereinafter abbreviated as the MAX circuit) that outputs the larger of the two input signals, 50, Reference numeral 51 is an adder, and the other parts are the same as those described with reference to the symbols in FIG. 4 (a), and therefore description thereof will be omitted. The same applies to the following drawings.

The operation will be described. The input composite video signal Cm is
Input to 1HDL32 and obtain 1 line delay signal Cmh. Signal Cmh
Is further input to 1HDL31 to obtain a signal Cm2h delayed by one line. That is, the signals Cm, Cmh, Cm2h are composite video signals of three adjacent lines. The signals Cm, Cmh, Cm2h are BPF67, 6 respectively.
The extracted signals Bs, Bsh, Bs2h obtained by separating and extracting the interleaved frequency band of the chromaticity signal are obtained by putting them in 8, 69. Since the phase of the chromaticity signal is inverted for each line,
A signal Bsh to align the phases of the three extraction signal is phase inverted by the phase inverter 38 inverting extraction delay signal Bsh ^- get. The extracted video signals of the adjacent three lines thus obtained are discriminated by the following procedure. That is, the MAX circuit 63
When the 64 and MIN circuit 60, the signal Bs and Bsh ^- get to select the smaller one towards the larger Bs2h selection signal Bsi ^- larger and signal Bsh of. Also, the MIN circuits 61 and 62 and the MAX circuit 65
, The signal Bs and Bsh ^- get to select the one larger smaller Bs2h selection signal Bsa ^- smaller and signals Bsh.
Thus-obtained selection signal Bsi, always inverted extraction delayed signal to any one of Bsa Bsh ^- is selected. Signal
It is assumed that the signal Bsh ^- is selected for Bsi. Again, if there is no correlation between the three lines, the signal Bsa and the signal Bsh
^- are added by the adder 50 is obtained, 1/2 at 1/2 coefficients 40
Fold has been obtained averaging signal Bsf also signal Bsh ^- and equal. Therefore, in this case, the chromaticity signal C obtained by restoring the phase of the signal Bsf by the phase inverter 39 is separated and extracted only by the BPF 68.

Inverting the extracted signal Bsh ^- extraction signal Bs, if there is a correlation with any of Bs2h, or extraction signal Bs, Bsh ^-, if there is any correlation Bs2h, the signal Bsa signal Bsh ^- a correlation with the signal , Or the most correlated signal is selected. The selection signal Bsa thus obtained is added to the other selection signal Bsi by the adder 50 and is multiplied by 1/2 by the 1/2 coefficient unit 40 to subtract between the video extraction signals between two adjacent lines having a correlation. Averaging is performed and the output signal Bsf is obtained. That is, in this case, the inverted extraction signal B
sh ^- whether there is a correlation, or signal Bsh ^- so that the chromaticity comb filter with the adjacent lines most is a correlation it has been configured. The above is the same when the inverted extraction signal Bsh ⁻ is selected as the selection signal Bsa. In this way, the luminance / chromaticity signal separation by the BPF of the composite video signal and the luminance / chromaticity signal separation by the comb filter are adaptively processed. The algorithm for discriminating the signal correlation by the combination of the MAX circuit and the MIN circuit is described in detail in Japanese Patent Laid-Open No. 215175/58. The phase of the output signal Bsf from which the luminance signal component has been separated in this manner is restored by the phase inverter 39, and the chromaticity signal C is obtained. On the other hand, the 1-line delay signal Cmh is subjected to the same amount of delay processing as that of the BPFs 67 to 69 in the DL 33, is added to the output signal Bsf subjected to the filtering processing, and is added by the adder 51 to eliminate the chromaticity signal component and obtain the luminance signal Y.

As the Y / C separation circuit, there is another frequency band separation system using a transversal type digital filter as shown in the example of FIG. However, this method has a problem in that a luminance signal in a band in which the chromaticity signal is interleaved is also processed as a chromaticity signal. Therefore, recently, a comb filter using a line delay means or a frame delay means is used. ing.

Next, a specific example of the brightness S / N improving circuit will be described. As the luminance S / N improvement circuit, one using inter-line correlation,
There are a method using inter-field correlation, a method using inter-frame correlation, and the like. A specific example using the medium line correlation is shown in FIG. 5 (a). In the figure, 29 is a limiter circuit that limits the amplitude of the input signal (hereinafter abbreviated as LMT circuit) 52,
53 is a subtractor.

 Hereinafter, the operation will be described.

The input luminance signal Y is input to 11HDL31 to obtain a luminance delay signal Yh which has been subjected to 1-line delay processing. The line difference signal obtained by subtracting the luminance delay signal Yh from the luminance signal Y by the subtracter 52 is input to the BPF 66 to obtain the band line difference signal Ys limited to the carrier frequency band of the chromaticity signal. The signal Ys is subjected to amplitude limitation by the LMT circuit to obtain the line difference limitation signal Ysl. On the other hand, the input luminance signal Y is subjected to the same amount of delay processing as that of the BPF 66 by the DL 33 to obtain the delayed luminance signal Yd. The line difference limiting signal Ysl is subtracted from the delayed luminance signal Yd by the subtracter 53 to obtain the S / N improved luminance signal Yi. In this method, the band line difference signal
The chromaticity signal mixed in the luminance signal in Ys is extracted. However, if the amplitude is large, it is more likely that it is an oblique component of the original luminance signal.Therefore, after limiting the amplitude to the same level as the chromaticity signal with the LMT circuit, subtract it from the delayed luminance signal Yd. As a result, the chromaticity signal mixed in the luminance signal is removed, and the S / N of the high frequency component is improved.

Another concrete example of the concrete example of the luminance S / N improving circuit shown in FIG. 5 (a) is shown in FIG. 5 (b) in which the S / N is improved up to the low frequency component of the luminance signal. In the figure, 82 is a coefficient unit that multiplies the input signal by k, 52, 53 and 55 are subtractors, and 54 is an adder.

Next, the operation will be described. The input luminance signal Y is subtracted from the output signal Yh ′ of 1HDL31 by the subtractor 55,
A difference component signal Ysu between two lines is obtained. The line difference signal Ysu is multiplied by k (0 <k <1) by the k multiplier 82, and then the LMT circuit 30
The amplitude is limited by and is fed back to the input luminance signal Y by the adder 50 to obtain the reduced improvement signal Y '. The low-frequency improvement signal Y'is the fifth
The same processing as that of the luminance S / N improvement circuit of FIG. 5A is performed until the S / N improvement luminance signal Yi of the output corresponding to the input signal Y of FIG. On the other hand, the delayed luminance signal output Yd is
The input luminance signal Y is delayed by DL34 and output. According to this method, the high-frequency component of the luminance is improved in S / N based on the same principle as that of FIG. It is regarded as a noise signal and is fed back to the input signal without any particular filtering processing. As a result, comb-shaped filter characteristics also occur in the low-frequency component of the luminance signal, and S / N is improved. Where k
Since the feedback signal is controlled by the multiplier, the attenuation amount does not become infinitesimally small like the high frequency component, and the vertical resolution does not deteriorate much.

Although the Y / C separation circuit and the luminance S / N improvement circuit have been described above, it is understood that there are many common elements in the above circuit. Therefore, not only the D / A converter can be effectively used but also the circuits themselves can be commonly used for the two circuits.

Therefore, as a specific example in which both are used, FIG.
FIG. 6 shows a specific example of a signal processing circuit in which the Y / C separation circuit shown in FIG. 5 and the luminance S / N improvement circuit shown in FIG. In the figure, 23, 24 and 25 are MPXs and 55 and 57 are subtractors.

Next, the operation will be described. When the input signal In ′ is the composite video signal Cm, the signal Cm is selected by MPX23 and
The extracted signal Bs input to the PF 66 and limited to the interleaved frequency band of the chromaticity signal is obtained. The extracted signal Bs is
An extraction delay signal Bsh selected by the MPX24 and subjected to 1-line delay processing by 1HDL31 is obtained. Furthermore, the extracted signal Bs is MPX25
And the extraction delay signal Bsh is subtracted by the subtractor 55 and then selected by the MPX21 to obtain the chromaticity signal C. On the other hand, the input composite video signal Cm is subjected to the same delay processing as the delay time given by the BPF 66 in the DL 33 to obtain the delayed video signal Cmd. The subtractor 57 subtracts the chromaticity signal C selected by the MPX 22 from the delayed video signal Cmd to obtain the luminance signal output Y. Next, when the input signal In ′ is the luminance signal Y, the luminance signal Y is MPX2.
The delayed luminance signal Yh selected in 4 and subjected to 1-line delay processing by 1HDL31 is obtained. The input luminance signal Y is MPX25.
And the delayed luminance signal Yh is subtracted by the subtractor 55 to obtain the line difference luminance signal Ysu. Line difference luminance signal Ysu is MPX23
The band line difference signal Ys selected by the BPF 66 and limited to the chromaticity signal carrier frequency band is obtained, and further input to the LMT circuit 29 to pass only the small amplitude signal. On the other hand, as the input luminance signal Y, a delay signal Yd is obtained by subjecting the DL33 to a delay process with a delay time equivalent to that of the BPF 66. On the other hand, the output signal of the LMT circuit 29 is M
The luminance signal Yi selected by the PX22 and subtracted from the delay signal Yd by the subtracter 57 and having an improved S / N ratio is output. The delayed signal Yd is selected by the MPX21 and output as the delayed luminance signal Yd.

Considering that the BPF66 is a linear circuit, the video signal processing circuit shown in FIG. 6 can be interchanged with the order of the 1HDL31 and can be the simplified video signal processing circuit shown in FIG. it can.

As can be seen from FIGS. 6 and 7, the Y /
It can be seen that the C separation circuit and the luminance signal S / N improvement circuit 12 have many common elements. Therefore, in this embodiment, not only the effective use of the two D / A converters can be achieved by obtaining an output signal having good compatibility with the subsequent circuit in the luminance signal S / N improvement process, The signal processing circuit itself can effectively be used without expanding the circuit scale.

8 and 9 show a third embodiment in which the video signal processing circuit according to the second embodiment of the present invention shown in FIG. 3 is applied to a magnetic recording / reproducing apparatus of a low frequency conversion chromaticity signal processing system. It is a circuit block diagram. In FIG. 8, 11 is the video signal Y / C separation / luminance S / N improvement circuit (hereinafter abbreviated as YCSN) shown in FIG. 3, 83, 84, 85, 86 are analog switches, and 15 is an FM modulator. A representative recording luminance signal processing circuit, 14 is a recording chromaticity signal processing circuit typifying low-frequency conversion processing. 58 and 59 are adders, 17 is a recording signal amplifier, 4 is a cylinder head, 5
Is a tape, 16 is a reproduction amplifier for amplifying a reproduction signal, 71 is a high-pass filter, 72 is a low-pass filter (hereinafter, respectively)
HPF and LPF are abbreviated), 12 is a reproduction luminance signal processing circuit that represents an FM demodulator, and 13 is a reproduction chromaticity signal that is represented by a circuit that restores the chromaticity signal that has undergone low frequency conversion to the original frequency band. A processing circuit, 18 is a crystal oscillator that oscillates a signal having a color subcarrier frequency, and 70 is a delay equalizer (hereinafter abbreviated as DEQ) that delays the signal.

Next, the operation will be described. The composite video signal Cm, which is the input signal, is switched by the switch 83 when recording by the magnetic recording / reproducing apparatus.
Selected by and input to the Y / C separation circuit 11. The luminance signal Y separated by the Y / C separation circuit is selected by the switch 84 and subjected to FM modulation processing by the recording luminance signal processing circuit 15. On the other hand, the chromaticity signal C separated at 11 is selected by the switch 85 and subjected to the low frequency conversion processing by the recording chromaticity signal processing circuit 14. The thus processed luminance signal Y and chromaticity signal C are added by the adder 59 to obtain a recorded composite video signal. This recording signal is amplified by the recording amplifier 17, then selected by the switch 86 and recorded on the recording tape 5 by the cylinder head 4.

During reproduction by the magnetic recording / reproducing apparatus, the video signal recorded on the recording tape 5 is read by the cylinder head 4 and input to the reproducing amplifier 16 via the switch 86. The luminance signal Y FM-modulated by the HPF 71 is separated from the reproduced video signal amplified by the amplifier 16 and demodulated by the reproduced luminance signal processing circuit 12. The luminance signal Y thus restored is input to the luminance S / N improving circuit 11 via the switch 83. on the other hand,
The chromaticity signal C is separated from the reproduced video signal as a chromaticity signal in the low-frequency converted state by the LPF 72, and is restored to the original frequency band by the reproduced chromaticity signal processing circuit 13. The playback video signal changes in the time axis due to the processing during recording and playback,
Since the continuity of the reproduced burst signal is lost, the burst signal of the reproduced color signal is synchronized with the output color subcarrier of the crystal oscillator 18 when the chromaticity signal is restored.

Therefore, there is a slight difference in frequency between the color subcarrier of the chromaticity signal during recording and the color subcarrier of the chromaticity signal during reproduction.
In addition, a chromaticity signal remains in the reproduction luminance signal, or a chromaticity signal is mixed in during the recording and reproduction process.
If such a luminance signal Y is added to the chromaticity signal C as it is, interference with the chromaticity signal occurs. Therefore, the reproduced luminance signal Y remains through the luminance S / N improving circuit 11 as shown in FIG.
Alternatively, it is necessary to filter the mixed chromaticity signal.

The reproduction luminance signal Y obtained as described above is the switch 84.
And is sent to the adder 58. On the other hand, the reproduction chromaticity signal C is DE
At Q70, the luminance S / N improvement circuit 11 performs the same amount of delay processing as the delay received by the reproduced luminance signal, and sends it to the adder 58. Here, the luminance signal Y and the chromaticity signal C are added to obtain the reproduced composite video signal Cm. By the way, when the video signal is externally output while being separated, the interference with the chromaticity signal does not occur, so that it is not necessary to use the luminance S / N improving circuit. Therefore,
Switch the delayed luminance signal output Yd that has undergone only delay processing
Output to external terminal via 85. Since there is no delay time difference between the S / N improved luminance signal Yi and the delayed luminance signal Yd, the reproduced chromaticity signal C
Can use the output of DEQ70 as it is as an external output. For example, the FM demodulation luminance signal and the high frequency conversion chromaticity signal output from the reproduction luminance and chromaticity signal processing circuits 12 and 13 have a delay time difference with each other, so if there is no delay output Yd from YCSN11, the time delay time difference is A separate delay element is required for adjusting the time of the two signals. In a circuit system that has a 1-input 2-output separation processing circuit and a 1-input 1-output signal processing circuit as in this embodiment, and a post-stage circuit requires an input signal before processing, the present invention is compatible with peripheral circuits. It is possible to construct a good circuit system.

Next, the third embodiment is provided with a luminance / chromaticity separation input terminal, a chromaticity comb filter and a field noise reducer (hereinafter abbreviated as CCMF and FNR, respectively),
FIG. 9 shows a modification in which the recorded video signal can be monitored. In the figure, 73 is CCMF and 74 is FNR.

The operation of the part different from the magnetic recording / reproducing apparatus shown in FIG. 8 will be described below.

First, the recording operation will be described. When the input signal is the composite video signal Cm, the luminance signal Y input to the Y / C separation circuit 11 via the switches 87 and 88 and separated and output is the switches 89 and 90.
The signal is input to the recording luminance signal processing circuit 15 via. Also Y /
The chromaticity signal C separated by the C separation circuit 11 is input to the recording chromaticity signal processing circuit 14 via the switch 93. The process of receiving the recording luminance signal and the recording chromaticity signal is as described with reference to FIG. On the other hand, the luminance signal Y separated and output from the Y / C separation circuit 11 is output as the monitor external output of the recording luminance signal and the recording chromaticity signal via the switches 90 and 91 and the switch 93, respectively. Further, the input composite video signal Cm itself is also output to the switches 87 and 95 for monitoring the recorded composite video signal.

Next, the case where a signal is applied to the luminance / chromaticity separation input terminal will be described. First, the luminance signal Y is a switch 87, 89,
It is input to the recording brightness signal processing circuit 15 via 90 and is output as an external monitor output of the recording brightness signal via the switches 90 and 91. The chromaticity signal C is input to the recording chromaticity signal processing circuit 14 via the switches 92 and 93, and the output of the switch 93 is output as it is as an external output for monitoring the recording chromaticity signal.

Since the composite video signal output as an external output of the recording signal for monitoring may cause signal interference with each other when the luminance and chromaticity are added as described in the embodiment of FIG.
Is added after being subjected to the luminance S / N improvement processing. The input separated luminance signal Y is inputted to the luminance S / N improving circuit 11 via the switches 87 and 88, and after being filtered, it is inputted to the adder 58.
The separated chromaticity input signal C passes through the switches 92 and 93, and then is input to the adder 58 after the delay time is matched with the luminance signal Y subjected to the S / N improvement processing in the DEQ 70. The composite video signal thus obtained is output as an external monitor output via the switch 95.

Next, the operation at the time of reproduction will be described. A video signal recorded on the tape 5 is reproduced, and a reproduction luminance signal processing circuit is reproduced.
The processing up to the output of 12 and the reproduction chromaticity signal processing circuit 13 is the same as the description of FIG. The reproduced luminance signal Y output from the reproduced luminance signal processing circuit 12 is input to the luminance S / N improving circuit 11 via the switches 90 and 88. Here, only the delay process is performed, and the delayed brightness output signal Yd is externally output via the switch 91. On the other hand, the luminance signal Yi that has been subjected to the S / N improvement processing for output of the composite video signal is input to the adder 58. The reproduction chromaticity signal C, which has been converted to a high frequency by the reproduction chromaticity signal processing circuit 13, is CC.
It is filtered by the MF74 and FNR73, and is output as an external separation output through the switches 92 and 93. Further, the reproduction chromaticity signal input to the adder 58 via the switch 93 is superimposed on the improved processed reproduction luminance signal and output to the external output terminal as a composite video signal Cm. CCMF74 removes the chromaticity signal mixed from the adjacent track on the magnetic tape of the reproduced chromaticity signal, and FNR73 uses the field delay signal to improve the S / N of the reproduced chromaticity signal. . Although the FNR is generally composed of a digital signal processing circuit using a digital memory, the reproduced chromaticity signal C is greatly delayed with respect to the luminance signal Y due to the filtering by the FNR. Therefore, it is necessary to match the delay time of the delayed luminance signal output Yd with the delay time of this FNR. DEQ70 due to the change of delay time
Also, the delay time of the brightness S / N improvement circuit may be adjusted to this delay time. For details of FNR, see, for example, Takahiko Fukibuki "Digital Signal Processing of Images", Nikkan Kogyo Shimbun P115.
-118.

The chromaticity comb filter causes a shift in the center of gravity of 0.5 lines unless it is configured by a comb filter that uses the determination of the correlation between lines. However, in order to make this shift in the center of gravity difficult to see, the luminance signal Y is set to 1 You can delay the line.
FIG. 10 shows a specific example of the luminance S / N improving circuit 11 which compensates for the deviation of the center of gravity of the reproduced chromaticity signal.

By adjusting the delay times of DL36 and 37 so that the delay times of DL35 and DL36 become the same as the delay time of FNR73, the above-mentioned delay time conditions can be achieved at the same time.

The delay time of the delayed luminance signal Yd is not necessarily the luminance S / N.
It suffices to match not only the delay time of the improvement circuit 11 but also the needs of peripheral circuits. Conversely, the luminance signal can be easily delayed from 400 ns to at most 600 ns. For a delay of more than 1 μs, a delay of one line, and the like, the method of effectively using a part of the digital signal processing circuit as in the present embodiment is most effective.

If the above YCSNs are integrated on one chip and integrated into an IC,
It can be used as a versatile IC for digital TVs and VTRs.

[Effects of the Invention] As described above, according to the present invention, in a digital signal processing circuit that performs both digital signal separation processing and signal processing, delay is performed without being subjected to signal processing, together with signal processed signals. Since a signal whose time is matched is obtained and D / A conversion is performed by switching to a plurality of separated signals obtained by the separation processing, an expensive D / A converter can be effectively used.

Further, the digital signal processing circuit of the present invention outputs both a signal processed signal and a signal not processed, and since there is no delay time difference between them, it is possible to provide a circuit having good compatibility with peripheral circuits.

Also in the magnetic recording / reproducing apparatus of the present invention, since the circuit is effectively used, it is possible to design inexpensively and compactly.

The digital signal processing circuit of the present invention can be effectively used not only in digital signal processing type TVs and VTRs but also in the field of signal multiplex communication by digital signals.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention,
FIG. 2 is a circuit block diagram showing a specific example of the first embodiment,
FIG. 3 is a circuit block diagram showing a second embodiment of the present invention,
FIG. 4 is a circuit block diagram showing a specific example of the Y / C separation circuit,
FIG. 5 is a circuit block diagram showing a concrete example of the luminance S / N improving circuit, FIGS. 6 to 7 are circuit block diagrams showing a concrete example of the second embodiment, and FIGS. 8 to 9 are FIG. 10 is a circuit block diagram showing the third embodiment, and FIG. 10 is a circuit block diagram showing a concrete example of the YCSN. 1 ... Separation processing circuit, 2 ... Signal processing circuit, 3 ... Delay processing circuit, 10 ... Y / C separation circuit, 11 ... Y / C separation and brightness S /
N improvement circuit, 20 …… Brightness S / N improvement circuit, 21-25 …… Multiplexer, 26 …… A / D converter, 27,28 …… D / A converter, 29
...... Limiter, 31-38, 301-306 …… Delay circuit, 41-59
...... Adder, subtractor, 66 to 69 …… Band filter, 75 to 82…
… Coefficient unit, 83-95 …… Switch.

Front Page Continuation (72) Inventor Takeshi Ichige 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Home Appliances Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-63-290484 (JP, A) JP-A-59- 207793 (JP, A)

Claims (5)

(57) [Claims] 1. An A / D converter for converting an analog input signal into a digital signal, separation processing means for separating the digital signal into at least two separation signals, and processing the digital signal to obtain one processed signal. A signal processing means for outputting and at least two D / A converters provided for each of the separated signals and converting the separated signals into analog signals are provided, and the processed signal is defined among the D / A converters. In the digital signal processing circuit configured to convert the digital signal into an analog signal, a delay signal obtained by subjecting the digital signal to the same amount of delay processing as the time required for the signal processing means to process the digital signal is provided. A delay processing unit for outputting is provided, and the delayed signal is converted into an analog signal by a predetermined one of the D / A converters other than the D / A converter that converts the processed signal into an analog signal. thing Digital signal processing circuit according to claim. 2. The digital signal according to claim 1, wherein the digital signal input to the separating means is a composite signal, and the digital signal input to the signal processing means is a non-composite signal. Processing circuit. 3. The non-composite signal is a periodic signal, and the delay processing means adds an integer multiple of the cycle of the non-composite signal in addition to the time required for the signal processing means to process the digital signal. 3. The digital signal processing circuit according to claim 2, further comprising a delay process for delaying the time. 4. The composite signal is a composite video signal, the non-composite signal is luminance, and the separation means is Y / C separation means for separating the composite video signal into a luminance signal and a chromaticity signal. 3. The method according to claim 2,
Alternatively, the digital signal processing circuit described in 3. 5. A magnetic recording / reproducing apparatus comprising a digital signal processing circuit according to claim 4, wherein the composite video signal is a recording signal and the luminance signal is a reproducing signal.