JPH04291520A - Signal processing unit - Google Patents

Signal processing unit

Info

Publication number
JPH04291520A
JPH04291520A JP3056641A JP5664191A JPH04291520A JP H04291520 A JPH04291520 A JP H04291520A JP 3056641 A JP3056641 A JP 3056641A JP 5664191 A JP5664191 A JP 5664191A JP H04291520 A JPH04291520 A JP H04291520A
Authority
JP
Japan
Prior art keywords
period
transmission circuit
signal
storage means
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3056641A
Other languages
Japanese (ja)
Inventor
Atsuo Ochi
厚雄 越智
Masayuki Yoneyama
匡幸 米山
康男 ▲はま▼本
Yasuo Hamamoto
Akihiro Takeuchi
明弘 竹内
Masaaki Kobayashi
正明 小林
Haruo Ota
晴夫 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3056641A priority Critical patent/JPH04291520A/en
Priority to DE69220986T priority patent/DE69220986T2/en
Priority to EP92302023A priority patent/EP0503891B1/en
Priority to US07/849,332 priority patent/US5299003A/en
Priority claimed from US07/849,332 external-priority patent/US5299003A/en
Priority to KR1019920004021A priority patent/KR960004326B1/en
Publication of JPH04291520A publication Critical patent/JPH04291520A/en
Pending legal-status Critical Current

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  • Noise Elimination (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To enhance the waveform reproducibility without reducing an emphasis quantity by providing a preshoot and an overshoot to the waveform. CONSTITUTION:An input signal is inputted to a transmission circuit 2 whose transfer characteristic is G, and its output has a waveform having an overshoot when the circuit 2 is an emphasis circuit and is distributed into two series, and they are inputted to storage means 3, 5. An input signal to the means 3 is read in a reverse time series to a time series at the storage and inputted to a transmission circuit 4 whose transfer characteristic is G. Thus, an overshoot and a preshoot are formed to both leading and trailing edges. Furthermore, the input signal to the means 5 is stored with a delay by only M/2 from a timing stored in the means 3 and the time axis is inverted for each period M. A switch 7 selects an output signal of the circuit 4 or 6 and the selected signal is outputted. Moreover, an emphasis waveform having a preshoot and an overshoot with respect to the input signal is obtained by inverting the time axis for each period M at a storage means 8.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、映像信号あるいは音声
信号など入力された信号の周波数特性を処理する信号処
理装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for processing the frequency characteristics of an input signal such as a video signal or an audio signal.

【0002】0002

【従来の技術】映像信号を記録再生するビデオテープレ
コーダなどにおいては、周波数変復調系ではFM伝送路
のノイズをホワイトノイズとすると、復調された信号に
加わるノイズは周波数の増加に伴ってノイズレベルも増
加する、いわゆる三角ノイズ特性を示す。これを軽減す
るために周波数変調する前に入力された信号の中・高域
のレベルを増大させ(いわゆるエンファシスをかけて周
波数偏移幅を増大させる)、周波数復調後に中・高域の
レベルを低下させる(いわゆるディエンファシス)信号
処理を行っている。しかし、FM伝送路の帯域について
は電磁変換系などにより帯域制限を受けるためエンファ
シス量による周波数偏移幅の増大に限度があり、それに
より再生された信号のSN比が制限されるという問題が
あった。なお、この問題はビデオテープレコーダのみな
らず衛星放送などのように映像信号を周波数変調して伝
送する系すべてにおいて生じる問題である。
[Prior Art] In video tape recorders and the like that record and reproduce video signals, in a frequency modulation/demodulation system, if the noise on the FM transmission line is white noise, the noise added to the demodulated signal will increase in noise level as the frequency increases. It exhibits an increasing so-called triangular noise characteristic. In order to alleviate this, the level of the medium and high range of the input signal is increased before frequency modulation (so-called emphasis is applied to increase the frequency deviation width), and the level of the medium and high range is increased after frequency demodulation. Signal processing is performed to lower the signal (so-called de-emphasis). However, since the band of the FM transmission line is limited by the electromagnetic conversion system, there is a limit to the increase in frequency deviation width due to the amount of emphasis, which causes the problem of limiting the S/N ratio of the reproduced signal. Ta. Note that this problem occurs not only in video tape recorders but also in all systems in which video signals are frequency modulated and transmitted, such as satellite broadcasting.

【0003】(図6)は従来例のエンファシス回路であ
る。(図6)において入力端子10に加えられた映像信
号はエンファシス処理されて出力端14に出力される。 (図6)における従来のエンファシス回路はコンデンサ
11(容量値C)、抵抗12(抵抗値Rb)、抵抗13
(抵抗値Ra)で構成されている。このような回路に(
図7)のaに示すような信号が入力された場合、出力端
14には(図7)のbに示すような信号が得られる。 ビデオテープレコーダの場合、(図7)のbに示すよう
な信号を周波数変調して磁気テープに記録するのである
が、FM伝送路である電磁変換系の周波数帯域に限度が
あるため(図7)のbの破線S1,S2に示すようなレ
ベルでクリップして周波数変調する。このため周波数復
調した信号は波形歪を生じるという課題があり、クリッ
プされないようにエンファシス量(Ra+Rb)/Ra
を1/2とするとエンファシスの効果が1/2となり、
その分再生信号のSN比が低下するという課題があった
FIG. 6 shows a conventional emphasis circuit. In FIG. 6, the video signal applied to the input terminal 10 is subjected to emphasis processing and output to the output terminal 14. The conventional emphasis circuit in (Fig. 6) includes a capacitor 11 (capacitance value C), a resistor 12 (resistance value Rb), and a resistor 13.
(resistance value Ra). In a circuit like this (
When a signal as shown in a of FIG. 7 is input, a signal as shown in b of FIG. 7 is obtained at the output terminal 14. In the case of a video tape recorder, the signal shown in b in Figure 7 is frequency-modulated and recorded on a magnetic tape, but because the frequency band of the electromagnetic conversion system that is the FM transmission line is limited ( ) is clipped and frequency modulated at the levels shown by broken lines S1 and S2 in b. For this reason, there is a problem that the frequency demodulated signal causes waveform distortion, and in order to avoid clipping, the emphasis amount (Ra + Rb) / Ra
If is set to 1/2, the effect of emphasis becomes 1/2,
There was a problem in that the SN ratio of the reproduced signal decreased accordingly.

【0004】0004

【発明が解決しようとする課題】これらの問題は、信号
の伝送において周波数変調を含むすべての系にて顕著な
問題である。すなわち周波数変調におけるSN改善のた
めのエンファシス量を増加させるとクリップにより波形
再現性が劣化し、波形再現性を良好とするためにエンッ
ファシス量を減少させるとSN改善量も低下するという
困難があった。
These problems are significant in all systems involving frequency modulation in signal transmission. In other words, when the amount of emphasis for improving SN in frequency modulation is increased, the waveform reproducibility deteriorates due to clipping, and when the amount of emphasis is decreased to improve the waveform reproducibility, the amount of SN improvement also decreases. .

【0005】本発明は上記の欠点を解消し、十分のエン
ファシス量を使用して、なおかつ、良好な波形再現性を
得る信号処理装置を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal processing device that eliminates the above-mentioned drawbacks, uses a sufficient amount of emphasis, and obtains good waveform reproducibility.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
に、本発明の信号処理装置は、伝達特性がGである第1
の伝送回路と、前記第1の伝送回路に接続され、前記第
1の伝送回路のインパルス応答持続期間αの少なくとも
2倍以上の期間Mの記憶容量を持ち、期間M毎に入力信
号を記憶された時系列と逆の時系列で順に出力する第1
の記憶手段と、前記第1の記憶手段の出力に接続された
伝達特性Gを持つ第2の伝送回路と、前記第1の伝送回
路に接続され、期間Mの記憶容量を持ち、第1の記憶手
段よりも期間αから期間(Mーα)までの時間遅れを持
ち期間M毎に入力信号を記憶された時系列と逆の時系列
で順に出力する第2の記憶手段と、前記第2の記憶手段
の出力に接続された伝達特性Gを持つ第3の伝送回路と
、各期間M内の信号が欠落しないように前記第2および
第3の伝送回路の出力信号を切り換えるスイッチと、少
なくともMの記憶容量を持ち、前記スイッチの出力信号
を切り換え期間毎に記憶された時系列と逆の時系列で順
に出力する第3の記憶手段とで構成されている。
[Means for Solving the Problems] In order to solve the above problems, a signal processing device of the present invention provides a first signal processing device having a transfer characteristic of G.
and a transmission circuit connected to the first transmission circuit, having a storage capacity for a period M that is at least twice the impulse response duration α of the first transmission circuit, and storing an input signal for each period M. The first step is to output sequentially the reverse time series and the reverse time series.
a second transmission circuit having a transfer characteristic G connected to the output of the first storage means; a second transmission circuit connected to the first transmission circuit and having a storage capacity of a period M; a second storage means that has a time delay from the period α to the period (M−α) than the storage means and sequentially outputs the input signal for each period M in a time series opposite to the stored time series; a third transmission circuit having a transfer characteristic G connected to the output of the storage means; a switch for switching the output signals of the second and third transmission circuits so that the signals within each period M are not dropped; The third storage means has a storage capacity of M and sequentially outputs the output signals of the switches in a time series opposite to the time series stored in each switching period.

【0007】[0007]

【作用】本発明の、上記した構成を取ることにより、回
路規模を大きく増大させることなく従来の問題点を解決
し、同一のFM伝送路で有れば従来と同一の周波数偏移
幅でもって従来以上のエンファシス量を使用可能にする
。あるいは、従来と同一のエンファシス量でもって波形
のピークが従来より大幅に低くなる信号処理装置を実現
できる。さらにはプリシュートとオーバーシュートを持
った任意の伝達特性を有する信号処理装置を提供できる
。また、伝送回路の有する位相特性を補償し、処理後の
信号の位相変化を零とすることを実時間で行うことがで
きる。
[Operation] By adopting the above-mentioned configuration of the present invention, the conventional problems can be solved without significantly increasing the circuit scale, and if the same FM transmission path is used, the same frequency deviation width as the conventional one can be achieved. Enables use of more emphasis than before. Alternatively, it is possible to realize a signal processing device in which the peak of the waveform is significantly lower than that of the conventional one with the same amount of emphasis as the conventional one. Furthermore, it is possible to provide a signal processing device having arbitrary transfer characteristics with preshoot and overshoot. Furthermore, it is possible to compensate for the phase characteristics of the transmission circuit and make the phase change of the processed signal zero in real time.

【0008】[0008]

【実施例】以下、本発明による信号処理装置の一実施例
を図面を参照しながら説明する。(図1)は、本発明の
信号処理装置の一例を示すブロック図である。また(図
2)から(図5)は、(図1)の信号処理装置の各部の
信号波形を示す波形図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a signal processing apparatus according to the present invention will be described below with reference to the drawings. (FIG. 1) is a block diagram showing an example of a signal processing device of the present invention. Moreover, (FIG. 2) to (FIG. 5) are waveform diagrams showing signal waveforms of each part of the signal processing device of (FIG. 1).

【0009】(図1)において、1は入力端子、2は伝
達特性Gを持つ第1の伝送回路、3は伝送回路2のイン
パルス応答持続期間αの少なくとも2倍以上の期間Mの
記憶容量を持ち、期間M毎に入力信号を記憶された時系
列と逆の時系列で順に出力する第1の記憶手段、4は伝
送回路2のインパルス応答持続期間αの少なくとも2倍
以上の期間Mの記憶容量を持ち、第1の記憶手段よりも
期間αから期間(Mーα)までの時間遅れを持ち期間M
毎に入力信号を記憶された時系列と逆の時系列で順に出
力する第2の記憶手段、4および5は第1の伝送回路2
と同一の伝達特性を持つ第2の伝送回路、7は各期間M
内の信号が欠落しないように前記伝送回路4および5の
出力信号を切り換えるスイッチ、8は前記スイッチ7の
出力信号を切り換え期間毎に記憶された時系列と逆の時
系列で順に出力する記憶手段である。
In FIG. 1, 1 is an input terminal, 2 is a first transmission circuit having a transfer characteristic G, and 3 is a storage capacity for a period M that is at least twice the impulse response duration α of the transmission circuit 2. 4, storage means for storing a period M that is at least twice as long as the impulse response duration α of the transmission circuit 2; It has a capacity, has a time delay from period α to period (M-α) than the first storage means, and has a period M
4 and 5 are the first transmission circuit 2; 4 and 5 are the first transmission circuit 2;
7 is a second transmission circuit having the same transfer characteristic as M.
A switch 8 switches the output signals of the transmission circuits 4 and 5 so that the signals in the transmission circuits 4 and 5 are not lost, and 8 is a storage means for sequentially outputting the output signals of the switch 7 in a time series opposite to the time series stored in each switching period. It is.

【0010】1に入力された信号は、伝達特性がGであ
る第1の伝送回路2に入力される。入力端子1には例え
ば(図2)のaに示すような信号が入力される。第1の
伝送回路2の出力信号は、(図2)のbに示すように第
1の伝送回路2がエンファシス回路であればオーバーシ
ュートを有する波形となる。ここで、第1の伝送回路2
のインパルス応答持続期間をαとする。また、(図2)
においてt0〜t1、t1〜t2、t2〜t3などの各
期間は少なくとも期間α以上に設定されている。第1の
伝送回路2を経た信号は2系列に分かれ、第1の記憶手
段3と第2の記憶手段5とに入力される。前記第1の記
憶手段3に入力された信号は、期間t0〜t2、t2〜
t4毎に記憶された後、記憶された時系列と逆の時系列
で読み出される。(図3)のaに波形図を示す。時間軸
が逆転された信号は、第1の伝送回路と同一の伝達特性
を持つ第2の伝送回路4に入力される。すなわち、(図
3)bに示すように、立ち上がりおよび立ち下がりの両
エッジにオーバーシュートとプリシュートが形成される
。また、第1の記憶手段5に入力された信号は、第1の
記憶手段3に記憶されるタイミングよりもM/2だけ遅
れて記憶され、期間M毎に時間軸が逆転される。すなわ
ち、期間t1〜t3、t3〜t5毎に処理される。その
波形図を(図4)bに示す。スイッチ7は、期間t1〜
t2、t3〜t4、t5〜t6は伝送回路4の出力信号
を、t2〜t3、t4〜t5、t6〜t7は伝送回路6
の出力信号を選択し出力する。こうして得られた信号は
、(図5)aに示すような波形となる。さらに、第2の
記憶手段8にて期間M毎に時間軸を逆転することによっ
て(図5)bに示す波形が得られる。(図5)bは、入
力信号に対してプリシュートとオーバーシュートを有す
るエンファシス波形が得られていることを示している。 ここで、エンファシスのプリシュートとオーバーシュー
トはクリップレベルS1,S2のいずれにも掛からない
ためFM復調後の再生波形の歪は全く発生しない。
The signal input to the first transmission circuit 2 is input to the first transmission circuit 2 whose transmission characteristic is G. For example, a signal as shown in a in FIG. 2 is input to the input terminal 1. The output signal of the first transmission circuit 2 has a waveform with an overshoot if the first transmission circuit 2 is an emphasis circuit, as shown in b of FIG. 2. Here, the first transmission circuit 2
Let α be the impulse response duration of . Also (Figure 2)
In the above, each period such as t0 to t1, t1 to t2, t2 to t3, etc. is set to be at least longer than the period α. The signal that has passed through the first transmission circuit 2 is divided into two streams and input into the first storage means 3 and the second storage means 5. The signal input to the first storage means 3 is transmitted during periods t0 to t2 and t2 to t2.
After being stored every t4, it is read out in the reverse chronological order to the stored chronological order. A waveform diagram is shown in a of FIG. 3. The signal whose time axis has been reversed is input to the second transmission circuit 4 having the same transmission characteristics as the first transmission circuit. That is, as shown in FIG. 3b, overshoots and preshoots are formed at both the rising and falling edges. Furthermore, the signal input to the first storage means 5 is stored with a delay of M/2 from the timing at which it is stored in the first storage means 3, and the time axis is reversed every period M. That is, it is processed every period t1 to t3 and t3 to t5. The waveform diagram is shown in (FIG. 4) b. The switch 7 is activated during the period t1~
t2, t3-t4, t5-t6 are the output signals of the transmission circuit 4, and t2-t3, t4-t5, t6-t7 are the output signals of the transmission circuit 6.
Select and output the output signal. The signal thus obtained has a waveform as shown in (a) of FIG. 5. Furthermore, by reversing the time axis every period M in the second storage means 8 (FIG. 5), the waveform shown in b is obtained. (FIG. 5) b shows that an emphasis waveform having preshoot and overshoot is obtained for the input signal. Here, since the emphasis preshoot and overshoot do not affect either the clip levels S1 or S2, no distortion occurs in the reproduced waveform after FM demodulation.

【0011】なお、上述の説明では、期間M毎に時間軸
を逆転する処理を同一期間内で行っているが、Mだけ遅
れて処理してもよい。
[0011] In the above description, the process of reversing the time axis every period M is performed within the same period, but the process may be performed with a delay of M.

【0012】さらに、上述の説明では、第1の記憶手段
と第2の記憶手段の処理期間のずれをM/2としている
が、伝送回路インパルス応答持続期間αから期間(Mー
α)までの時間であれば同様の結果が得られる。また、
スイッチの切り換えタイミングもM/2としているが、
期間M内の信号が欠落しないようなタイミングで伝送回
路4および5の出力信号を切り換える場合であってもよ
い。
Furthermore, in the above explanation, the difference between the processing periods of the first storage means and the second storage means is M/2, but the difference between the transmission circuit impulse response duration α and the period (M-α) Similar results can be obtained with time. Also,
The switching timing of the switch is also M/2,
The output signals of the transmission circuits 4 and 5 may be switched at a timing such that the signals within the period M are not dropped.

【0013】[0013]

【発明の効果】以上のように本発明の信号処理装置によ
れば、一度、正の時系列で伝送回路に信号を通し、次に
逆の時系列で同じ伝達特性を有する伝送回路に通して出
力することにより、伝送回路の持つ位相特性を零位相と
する効果を持ち、映像信号においては特に有用である。 また、連続信号を区切って処理する際に、伝送回路のイ
ンパルス応答の持続期間αの少なくとも2倍以上の期間
に渡って処理するため、信号の不連続部分に発生する不
要な波形変化を避ける事ができる。また、以上の処理を
2系列に分けて実施する事により、連続信号を区分信号
に分割して処理した後、再び連続信号として出力すると
いう作業を実時間で実行できる。
As described above, according to the signal processing device of the present invention, a signal is passed through a transmission circuit in a positive time series once, and then passed through a transmission circuit having the same transfer characteristics in a reverse time series. This output has the effect of making the phase characteristic of the transmission circuit zero phase, and is particularly useful for video signals. In addition, when processing continuous signals in sections, processing is performed over a period that is at least twice the duration α of the impulse response of the transmission circuit, so unnecessary waveform changes that occur in discontinuous portions of the signal can be avoided. Can be done. Furthermore, by performing the above processing in two series, it is possible to perform the task of dividing a continuous signal into segmented signals, processing them, and then outputting them again as continuous signals in real time.

【0014】また、上述したように本発明の信号処理装
置を周波数変復調系のエンファシス回路として用いた場
合には、波形にプリシュートとオーバーシュートをもた
せることにより、従来と同一のエンファシス量を有し、
かつ波形のピーク値が従来より低くなるエンファシス回
路が実現でき、エンファシス量を低下させることなく、
周波数偏移幅を従来より大幅に低下させる効果がある。 あるいは、従来より以上のエンファシスを加えることが
でき、再生された信号の波形再現性を向上することがで
きる。
Furthermore, as described above, when the signal processing device of the present invention is used as an emphasis circuit in a frequency modulation/demodulation system, by giving the waveform a preshoot and an overshoot, it can have the same amount of emphasis as the conventional one. ,
It is also possible to realize an emphasis circuit in which the peak value of the waveform is lower than before, without reducing the amount of emphasis.
This has the effect of significantly reducing the frequency deviation width compared to the conventional method. Alternatively, it is possible to add more emphasis than before, and it is possible to improve the waveform reproducibility of the reproduced signal.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例である信号処理装置を示すブ
ロック図
FIG. 1 is a block diagram showing a signal processing device that is an embodiment of the present invention.

【図2】本発明の一実施例である信号処理装置の各部の
信号波形を示す波形図
FIG. 2 is a waveform diagram showing signal waveforms of each part of a signal processing device that is an embodiment of the present invention.

【図3】本発明の一実施例である信号処理装置の各部の
信号波形を示す波形図
FIG. 3 is a waveform diagram showing signal waveforms of each part of a signal processing device that is an embodiment of the present invention.

【図4】本発明の一実施例である信号処理装置の各部の
信号波形を示す波形図
FIG. 4 is a waveform diagram showing signal waveforms of each part of a signal processing device that is an embodiment of the present invention.

【図5】本発明の一実施例である信号処理装置の各部の
信号波形を示す波形図
FIG. 5 is a waveform diagram showing signal waveforms of each part of a signal processing device that is an embodiment of the present invention.

【図6】従来の実施例を示すブロック図[Fig. 6] Block diagram showing a conventional embodiment

【図7】従来の
実施例の信号波形を示す波形図
[Fig. 7] Waveform diagram showing signal waveforms of conventional embodiments

【符号の説明】[Explanation of symbols]

1  入力端子 2  第1の伝送回路 3  第1の記憶手段 4  第2の伝送回路 5  第2の記憶手段 6  第3の伝送回路 7  スイッチ 8  第3の記憶手段 9  出力端子 1 Input terminal 2 First transmission circuit 3. First storage means 4 Second transmission circuit 5 Second storage means 6 Third transmission circuit 7 Switch 8 Third storage means 9 Output terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  伝達特性がGである第1の伝送回路と
、前記第1の伝送回路に接続され、前記第1の伝送回路
のインパルス応答持続期間αの少なくとも2倍以上の期
間Mの記憶容量を持ち、期間M毎に入力信号を記憶され
た時系列と逆の時系列で順に出力する第1の記憶手段と
、前記第1の記憶手段の出力に接続された伝達特性Gを
持つ第2の伝送回路と、前記第1の伝送回路に接続され
、期間Mの記憶容量を持ち、第1の記憶手段よりも期間
αから期間(Mーα)までの時間遅れを持ち期間M毎に
入力信号を記憶された時系列と逆の時系列で順に出力す
る第2の記憶手段と、前記第2の記憶手段の出力に接続
された伝達特性Gを持つ第3の伝送回路と、各期間M内
の信号が欠落しないように前記第2および第3の伝送回
路の出力信号を切り換えるスイッチと、少なくともMの
記憶容量を持ち、前記スイッチの出力信号を切り換え期
間毎に記憶された時系列と逆の時系列で順に出力する第
3の記憶手段とを備えたことを特徴とする信号処理装置
1. A first transmission circuit having a transfer characteristic of G, and a storage of a period M connected to the first transmission circuit and at least twice as long as an impulse response duration α of the first transmission circuit. a first storage means having a capacity and sequentially outputting the input signal in a time series opposite to the stored time series every period M; and a first storage means having a transfer characteristic G connected to the output of the first storage means. The second transmission circuit is connected to the first transmission circuit, has a storage capacity of a period M, has a time delay from period α to period (M-α), and has a time delay from period α to period (M-α) for each period M. a second storage means for sequentially outputting input signals in a time series opposite to the stored time series; a third transmission circuit having a transfer characteristic G connected to the output of the second storage means; a switch that switches the output signals of the second and third transmission circuits so that the signals in M are not lost; and a switch that has a storage capacity of at least M, and stores the output signals of the switch in a time series stored for each switching period. A signal processing device comprising: third storage means for sequentially outputting in reverse chronological order.
JP3056641A 1991-03-14 1991-03-20 Signal processing unit Pending JPH04291520A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP3056641A JPH04291520A (en) 1991-03-20 1991-03-20 Signal processing unit
DE69220986T DE69220986T2 (en) 1991-03-14 1992-03-10 Signal processing device
EP92302023A EP0503891B1 (en) 1991-03-14 1992-03-10 Signal processing apparatus
US07/849,332 US5299003A (en) 1991-03-14 1992-03-10 Signal processing apparatus for changing the frequency characteristics of an input signal
KR1019920004021A KR960004326B1 (en) 1991-03-14 1992-03-11 Signal processing apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3056641A JPH04291520A (en) 1991-03-20 1991-03-20 Signal processing unit
US07/849,332 US5299003A (en) 1991-03-14 1992-03-10 Signal processing apparatus for changing the frequency characteristics of an input signal

Publications (1)

Publication Number Publication Date
JPH04291520A true JPH04291520A (en) 1992-10-15

Family

ID=26397600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3056641A Pending JPH04291520A (en) 1991-03-14 1991-03-20 Signal processing unit

Country Status (1)

Country Link
JP (1) JPH04291520A (en)

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