JPH0325345Y2 - - Google Patents

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Publication number
JPH0325345Y2
JPH0325345Y2 JP10195084U JP10195084U JPH0325345Y2 JP H0325345 Y2 JPH0325345 Y2 JP H0325345Y2 JP 10195084 U JP10195084 U JP 10195084U JP 10195084 U JP10195084 U JP 10195084U JP H0325345 Y2 JPH0325345 Y2 JP H0325345Y2
Authority
JP
Japan
Prior art keywords
circuit
emphasis
signal
clip
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10195084U
Other languages
Japanese (ja)
Other versions
JPS6121056U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10195084U priority Critical patent/JPS6121056U/en
Publication of JPS6121056U publication Critical patent/JPS6121056U/en
Application granted granted Critical
Publication of JPH0325345Y2 publication Critical patent/JPH0325345Y2/ja
Granted legal-status Critical Current

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  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 本考案はクリツプ部分補償回路に係り、例えば
VTRの再生系に用いられ、記録系におけるクリ
ツプ回路にて波形の一部期間をクリツプされてい
る部分を補償して取出す補償回路に関する。
[Detailed description of the invention] Industrial application field The present invention relates to a clip partial compensation circuit, for example.
The present invention relates to a compensation circuit used in a VTR playback system to compensate for and extract a portion of a waveform that is clipped by a clip circuit in a recording system.

従来の技術 VTRの輝度信号再生回路では、磁気テープに
記録されているFM信号を復調する際にいわゆる
三角ノイズを生じる。この三角ノイズを軽減する
回路として、一般に、記録時において変調波の高
域を強調するプリエンフアシス回路、再生時にお
いてその高域を低減させるデイエンフアシス回路
が用いられている。
BACKGROUND TECHNOLOGY In the brightness signal reproducing circuit of a VTR, so-called triangular noise is generated when demodulating an FM signal recorded on a magnetic tape. As a circuit for reducing this triangular noise, a pre-emphasis circuit that emphasizes the high frequency range of a modulated wave during recording and a de-emphasis circuit that reduces the high frequency range during playback are generally used.

ところで、プリエンフアシス回路におけるエン
フアシス量が大きい程デイエンフアシス後のSN
比を良好にし得るが、このようにすると、映像信
号の黒から白への立上り等に生じるスパイクが大
になり、過変調状態になつて反転等の不都合を生
じる。このスパイク部分をある一定振幅以下に制
限する回路としてのクリツプ回路を用いる。
By the way, the larger the amount of emphasis in the pre-emphasis circuit, the higher the SN after de-emphasis.
Although it is possible to improve the ratio, this increases the spikes that occur when the video signal rises from black to white, leading to overmodulation and causing problems such as inversion. A clip circuit is used to limit this spike portion to a certain amplitude or less.

第3図Aに示す映像信号をプリエンフアシス回
路にてその高域を強調し、この強調部分をあるク
リツプレベルにてクリツプすると同図Bに示す如
く、クリツプされた部分m1とクリツプされない
部分m2とを生じる。この信号をプリエンフアシ
ス特性と逆の特性をもつデイエンフアシス回路に
て高域低減すると同図Cに示す如く、再現波形が
悪化する部分m3とそれ程悪化しない部分m4とを
生じる。
When the high range of the video signal shown in FIG. 3A is emphasized by a pre-emphasis circuit and this emphasized portion is clipped at a certain clip level, as shown in FIG. 3B, a clipped portion m 1 and an unclipped portion m 2 are created. and give rise to. When this signal is reduced in high frequency by a de-emphasis circuit having characteristics opposite to the pre-emphasis characteristics, a portion m 3 where the reproduced waveform deteriorates and a portion m 4 where the reproduction waveform does not deteriorate as much are generated as shown in FIG.

考案が解決しようとする問題点 従来装置では、デイエンフアシス特性をプリエ
ンフアシス特性の逆特性にしないで第4図に示す
ようにクリツプされた部分の再現波形m5を良好
にしているが、このようにすると、クリツプされ
ない部分の再現波形m6の再現性が悪化し、又、
上記両特性を互いに逆特性にしていないのでSN
比が十分にとれない問題点があつた。
Problems to be solved by the invention In the conventional device, the reproduced waveform m5 of the clipped part as shown in Fig. 4 is improved by not making the de-emphasis characteristic the inverse of the pre-emphasis characteristic. , the reproducibility of the reproduced waveform m6 of the unclipped portion deteriorates, and
Since both of the above characteristics are not reversed, SN
There was a problem that the ratio was not sufficient.

本考案は、プリエンフアシス回路の出力と略同
じ波形の出力信号を得、後段のデイエンフアシス
回路にプリエンフアシス回路と逆特性のものを用
いてSN比の高い信号を得ることができるクリツ
プ部分補償回路を提供することを目的とする。
The present invention provides a clipped partial compensation circuit that can obtain an output signal with approximately the same waveform as the output of the pre-emphasis circuit, and can obtain a signal with a high signal-to-noise ratio by using a subsequent de-emphasis circuit with characteristics opposite to that of the pre-emphasis circuit. The purpose is to

問題点を解決するための手段 第1図中、2は入力信号の高域を強調するエン
フアシス回路、6は入力信号のクリツプ期間を検
出する比較器、5はエンフアシス回路の出力と入
力信号とを切換える切換回路である。
Means for solving the problem In Figure 1, 2 is an emphasis circuit that emphasizes the high frequency range of the input signal, 6 is a comparator that detects the clip period of the input signal, and 5 is a circuit that connects the output of the emphasis circuit and the input signal. This is a switching circuit.

作 用 エンフアシス回路2で入力信号の高域を強調
し、比較器6で入力信号のクリツプ期間を検出
し、比較器6の出力でクリツプ期間エンフアシス
回路2の出力を取出す一方、それ以外の期間入力
信号を取出す。
Function The emphasis circuit 2 emphasizes the high frequency range of the input signal, the comparator 6 detects the clip period of the input signal, and the output of the comparator 6 is used to obtain the output of the clip period emphasis circuit 2, while inputting other periods. Take out the signal.

実施例 第1図は本考案回路の一実施例のブロツク系統
図を示す。同図において、端子1には記録系のク
リツプ回路(図示せず)にて特に振幅の大きいス
パイク部分を制限された映像信号a(第2図A)
が入来する。映像信号aは記録系におけるプリエ
ンフアシス回路(図示せず)のエンフアシス特性
と略同じ特性をもつエンフアシス回路2にてその
高域を強調されて第2図Bに示す信号bとされ、
減衰器3にて後述の遅延回路4の出力レベルと同
じレベルになるように減衰され、スイツチ回路5
の端子aに供給される。
Embodiment FIG. 1 shows a block diagram of an embodiment of the circuit of the present invention. In the figure, terminal 1 is connected to a video signal a (Figure 2A) whose spike portions with particularly large amplitudes are limited by a clip circuit (not shown) in the recording system.
comes in. The high frequency range of the video signal a is emphasized by an emphasis circuit 2, which has substantially the same characteristics as the emphasis characteristics of a pre-emphasis circuit (not shown) in the recording system, and becomes the signal b shown in FIG. 2B.
The attenuator 3 attenuates the output level to the same level as the output level of the delay circuit 4, which will be described later.
is supplied to terminal a of.

この場合、エンフアシス回路2の特性が記録系
におけるプリエンフアシス回路の特性と同じであ
るので、信号bの部分b1,b2の傾斜は記録系にお
けるクリツプ回路によるクリツプ前の信号(即
ち、プリエンフアシス回路の出力信号)の傾斜と
略同じになる。
In this case, since the characteristics of the emphasis circuit 2 are the same as those of the pre-emphasis circuit in the recording system, the slopes of portions b 1 and b 2 of the signal b are the signals before clipping by the clip circuit in the recording system (i.e., the pre-emphasis circuit's characteristics). The slope is approximately the same as the slope of the output signal).

一方、映像信号aは遅延回路4にてエンフアシ
ス回路2における遅延時間と同量遅延され、スイ
ツチ回路5の端子bに供給される。
On the other hand, the video signal a is delayed in the delay circuit 4 by the same amount as the delay time in the emphasis circuit 2, and is supplied to the terminal b of the switch circuit 5.

6は2種の基準電位VHC,VLCをもつウイン
ド・コンパレータ(比較器、クリツプ期間検出回
路)で、映像信号aのクリツプレベルをVH,VL
とすると、VHC<VH,VLC>VLの如く選定されて
いる(なお、VHCとVH,VLCとVLとの夫々の差は
極く小さい)。映像信号aは比較器6にて基準電
位VHC,VLCと比較され、そのレベルが電位VHC
VLCより大の期間のみHレベル、小の期間Lレベ
ルの信号c(同図C)が取出され、切換信号とし
てスイツチ回路5に供給される。
6 is a window comparator (comparator, clip period detection circuit) having two types of reference potentials V HC and V LC , which determines the clip level of the video signal a to V H , V L
Then, V HC <V H , V LC >V L are selected (note that the differences between V HC and V H and between V LC and V L are extremely small). The video signal a is compared with reference potentials V HC , V LC in a comparator 6, and the level is determined as the potentials V HC , V LC .
A signal c (C in the same figure) which is at H level only during a period greater than V LC and at L level during a period smaller than V LC is taken out and supplied to the switch circuit 5 as a switching signal.

スイツチ回路5の可動接片は、比較器6の出力
信号cがHレベルの時端子a、出力信号cがLレ
ベルの時端子bに夫々接続される構成とされてお
り、これにより、第2図Dに示す信号dが取出さ
れ、端子7より取出される。信号dは、映像信号
aのクリツプ期間は信号bの部分b1,b2、その他
の期間は映像信号aを遅延された信号であり、記
録系におけるプリエンフアシス回路の出力と略同
じ波形とし得る。
The movable contacts of the switch circuit 5 are configured to be connected to the terminal a when the output signal c of the comparator 6 is at the H level, and to the terminal b when the output signal c is at the L level. A signal d shown in FIG. D is taken out from the terminal 7. The signal d is a signal obtained by delaying parts b 1 and b 2 of the signal b during the clipping period of the video signal a, and is a delayed signal of the video signal a during other periods, and can have substantially the same waveform as the output of the pre-emphasis circuit in the recording system.

なお、エンフアシス回路2における遅延時間が
無視できる場合は、遅延回路4を設ける必要はな
い。
Note that if the delay time in the emphasis circuit 2 can be ignored, it is not necessary to provide the delay circuit 4.

考案の効果 本考案回路は、プリエンフアシス回路出力の波
形の一部期間をクリツプされた入力信号を供給給
されその高域をプリエンフアシス回路の特性と略
同じ特性で強調するエンフアシス回路と、入力信
号のクリツプされている期間を検出するクリツプ
期間検出回路と、クリツプ期間検出回路の出力に
てクリツプ期間エンフアシス回路の出力を取出す
一方、クリツプ期間以外の期間入力信号を取出す
ように切換える切換回路とにて構成したため、プ
リエンフアシス回路の出力と略同じ波形の出力信
号を取出し得、これにより、後段のデイエンフア
シス回路にプリエンフアシス回路の特性と逆特性
のものを用い得、従つて、デイエンフアシス回路
より大振幅部分及び小振幅部分ともに再現性の良
好な信号を取出し得、更に、比較的簡単に構成し
得るので安価であり、又更に、デジタル信号処理
し得る回路にて構成し得る等の特長を有する。
Effects of the invention The circuit of the invention consists of an emphasis circuit which is supplied with an input signal in which a part of the period of the waveform of the output of the pre-emphasis circuit is clipped and which emphasizes the high frequency range with substantially the same characteristics as the characteristics of the pre-emphasis circuit; This is because it consists of a clip period detection circuit that detects the period in which the clip is being clipped, and a switching circuit that outputs the output of the clip period emphasis circuit from the output of the clip period detection circuit, while switching to extract the input signal for periods other than the clip period. , it is possible to extract an output signal with approximately the same waveform as the output of the pre-emphasis circuit, thereby allowing the subsequent de-emphasis circuit to have characteristics opposite to those of the pre-emphasis circuit. Both of them have the advantage of being able to extract signals with good reproducibility, being relatively simple to construct and therefore inexpensive, and being constructed of circuits capable of digital signal processing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は夫々本考案回路の一実施例
のブロツク系統図及びその動作説明用信号波形
図、第3図はプリエンフアシス回路をデイエンフ
アシス回路の特性と逆特性にした場合の信号波形
図、第4図は従来回路によるデイエンフアシス後
の信号波形図である。 1……映像信号入力端子、2……エンフアシス
回路、5……スイツチ回路、6……比較器、7…
…出力端子。
Figures 1 and 2 are a block system diagram and a signal waveform diagram for explaining the operation of an embodiment of the circuit of the present invention, respectively, and Figure 3 is a signal waveform diagram when the pre-emphasis circuit has characteristics opposite to those of the de-emphasis circuit. , FIG. 4 is a signal waveform diagram after de-emphasis by a conventional circuit. 1...Video signal input terminal, 2...Emphasis circuit, 5...Switch circuit, 6...Comparator, 7...
...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プリエンフアシス回路出力の波形の一部期間を
クリツプされた入力信号を供給されその高域を該
プリエンフアシス回路の特性と略同じ特性で強調
するエンフアシス回路と、該入力信号のクリツプ
されている期間を検出するクリツプ期間検出回路
と、該クリツプ期間検出回路の出力にて該クリツ
プ期間上記エンフアシス回路の出力を取出す一
方、該クリツプ期間以外の期間上記入力信号を取
出すように切換える切換回路とよりなるクリツプ
部分補償回路。
An emphasis circuit that is supplied with an input signal in which a partial period of a waveform of an output of a pre-emphasis circuit is clipped and emphasizes the high range thereof with substantially the same characteristics as the pre-emphasis circuit, and detects the clipped period of the input signal. A clip partial compensation circuit comprising a clip period detection circuit and a switching circuit configured to extract the output of the emphasis circuit during the clip period from the output of the clip period detection circuit, and to extract the input signal during periods other than the clip period. .
JP10195084U 1984-07-05 1984-07-05 Clip partial compensation circuit Granted JPS6121056U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10195084U JPS6121056U (en) 1984-07-05 1984-07-05 Clip partial compensation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10195084U JPS6121056U (en) 1984-07-05 1984-07-05 Clip partial compensation circuit

Publications (2)

Publication Number Publication Date
JPS6121056U JPS6121056U (en) 1986-02-06
JPH0325345Y2 true JPH0325345Y2 (en) 1991-05-31

Family

ID=30661362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10195084U Granted JPS6121056U (en) 1984-07-05 1984-07-05 Clip partial compensation circuit

Country Status (1)

Country Link
JP (1) JPS6121056U (en)

Also Published As

Publication number Publication date
JPS6121056U (en) 1986-02-06

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