JPS607280A - Signal processor - Google Patents

Abstract

PURPOSE:To reduce remarkably the frequency shift width less than a conventional example without reducing emphasis amount by providing pre-shoot and overshoot to a waveform when the signal processor is used as an emphasis circuit of a frequency modulating/demodulating system. CONSTITUTION:A video signal applied to an input terminal 1 is fed to the 1st transmission ciruit 7 having a transfer function of G. The 1st transmission circuit 7 is an emphasis circuit 22. Memory circuits 9, 10 store sequentially an inputted signal and when a control signal fed to control terminals 28, 29 is at L level, the memory circuits 9, 10 output a signal in opposite time series as the stored time series. The signal processing having optional emphasis characteristic provided with pre-shoot and overshoot is attained by selecting optionally the transfer characteristic G of the 1st transmission circuit 7 and the 2nd transmission circuit 12 as mentioned above.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal processing device that converts a signal such as a video signal into a signal with desired frequency characteristics, and is applicable to transmission systems such as video tape recorders and satellite broadcasting. It is useful for use.

Conventional configurations and their problems In video tape recorders and the like that record and reproduce video signals, a frequency modulation recording method is common. In a frequency modulation/demodulation system, if the noise on the FM transmission line is white noise, the noise added to the demodulated signal exhibits so-called triangular noise characteristics in which the noise level increases as the frequency increases. In order to reduce this, before frequency modulation, the level and width of the middle and high range of the input signal is increased (increasing the width), and after frequency demodulation, the level of the middle and high range is lowered (so-called de-emphasis). Processing is in progress. However, the band of the FM transmission line is limited by the electromagnetic conversion system, etc., so there is a limit to the increase in frequency deviation width due to the amount of emphasis, which limits the S/N ratio of the reproduced signal. There was a problem.

Note that this problem is not limited to video tape recorders.
This problem occurs in all systems that transmit frequency modulated video signals, such as satellite broadcasting.

OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems and
If it is a transmission line, with the same frequency deviation width as before,
The object of the present invention is to provide a signal processing device that enables use of an amount of emphasis greater than that of the conventional art.

Alternatively, it is an object of the present invention to provide a signal processing device in which the peak value of a waveform is significantly lower than that of the conventional art with the same amount of emphasis as in the conventional art.

A further object of the present invention is to provide a signal processing device having arbitrary transfer characteristics with preshoot and overshoot.

Structure of the Invention In order to achieve the above object, the present invention includes an emphasis circuit and a de-emphasis circuit, and the emphasis circuit includes a first transmission circuit, a first switch, a first memory circuit, The structure includes a second memory circuit, a second switch, and a second transmission circuit, and the first...
The second memory circuit sequentially inputs signals over a period of n x H (where n is an arbitrary positive integer and H is a horizontal scanning period), and inputs the input signals in the opposite time over the next n x H period. The first . The second transmission circuit is configured so that both transmission characteristics are G, and the signal input to the first transmission circuit and processed is transmitted by the first switch.
The output signals of the first and second memory circuits are switched every nxH time and input to the first memory circuit and the second memory circuit, and the output signals of the first and second memory circuits are also connected to the second switch. The de-emphasis circuit is configured to be switched in a phase opposite to that of the first switch, converted into one series of signals, and then outputted through the second transmission circuit. The transmission circuit includes a transmission circuit, a third switch, a third memory circuit, a fourth memory circuit, and a fourth transmission circuit, and the third. The fourth memory circuit is configured to sequentially input signals over n×H time and output the inputted signals in reverse time series over the next n×H time, and
The transmission circuits are constructed such that their transfer characteristics are both 100, and the signal input to and processed by the third transmission circuit is switched every nxH times by the third switch. , the output signals of the third and fourth memory circuits are input to the third memory circuit and the fourth memory circuit, and the output signals of the third and fourth memory circuits are inputted to the third memory circuit and the fourth memory circuit, and the output signals of the third and fourth memory circuits are controlled by the fourth switch. One series of (
+', i, and then outputted through the fourth transmission circuit as the output signal.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the explanation will be given using an emphasis circuit used in a video tape recorder (VTFt) as an example of a signal processing circuit. FIG. 1 shows a conventional emphasis circuit used in VH3 type VTRs and the like. In FIG. 1, a video signal applied to an input terminal 1 is outputted to an output terminal 6 via an emphasis circuit 60. The emphasis circuit 50 includes a capacitor (capacitance value C1) 61° and a resistor (resistance value Rh) 52. Resistance (resistance value Ra) 53
It consists of Their values are, for example, Rb+R
a CxRb=1, 311 sec, Ra=6.

When a video signal as shown in FIG. 2(-) is input to the input terminal 1 of such a circuit, a signal as shown in FIG. 2(-) is obtained at the output terminal 6. In the case of a video tape recorder, the signal shown in FIG. 2(b) is frequency-modulated and recorded on a magnetic tape (not shown).
Since the frequency band of the electromagnetic conversion system, which is the M transmission path, is limited, the signal is clipped at the point indicated by the broken line S in Fig. 2(b), and the signal is made as shown in Fig. 2(C). Frequency modulation. Alternatively, by changing the constants of each part of the emphasis circuit 60 and setting Ki (-Ra), a signal as shown in FIG. 2(d) can be obtained. Frequency modulation. In the case of Fig. 2 (C), there is a problem that waveform distortion occurs, and in the case of Fig. 2 (d), the effect of emphasis becomes 100, and the S/N ratio of the reproduced signal decreases by that amount. There is a problem.

FIG. 3 shows an emphasis circuit 34 using an example of the signal processing device of the present invention, and FIG. 4 shows a de-emphasis circuit 36. In Figure 3, input terminal 1
The video signal applied to is supplied to the first transmission circuit 7 whose transfer function is G. The first transmission circuit 7 is an emphasis circuit 22 as shown in FIG. Emphasis circuit 22, capacitor (capacitance value C2) 23. Resistance (resistance value RC)24. R is composed of 26 resistors (resistance value Rd)
There is c+Rd. These values are set to Rd-2,5, for example.

When a video signal as shown in FIG. 2(a) is input to such a circuit, a signal as shown in FIG. 2(e) is obtained at the output terminal.

On the other hand, the signal whose level is inverted every 1H is the C0NT terminal 1.
5 has been added. This signal is obtained, for example, by inputting a horizontal synchronizing signal included in the input video signal to a flip-flop circuit (not shown). In this way, the signal supplied to the C0NT terminal 15 is transmitted to the control terminal 26 of the first switch 8 and to the first memory circuit 90.
is applied to the control terminal 28 and inverted by the inverter 17, and is applied to the control terminal 27 of the second switch 11 and
The signal is supplied to the control terminal 29 of the second memory circuit 100.

Here, the video signal processed by the first transmission circuit 7 is
The signal is switched by the first switch 8 every horizontal scan (every 1H) and is input to the first memory circuit 9 and the second memory circuit 10 every 1H.

The first memory circuit 9 and the second memory circuit 10 are constituted by analog memories, for example, and have a storage capacity of 1H. When the control signals applied to the control terminals 28 and 29 are at H level, the memory circuits 9 and 1 are
0, the input signals are stored sequentially and the control terminal 28.2
When the control signal applied to 9 is at L level, the memory circuits 9 and 10 output in a time series opposite to the stored time series. Still, when the control signal applied to the control terminal 26 is at H level, the movable piece of the switch 8
11 is knocked down to the first memory circuit 9 side and is at L level! i, it is turned over to the second memory circuit 10 side. The first one like this
As shown in FIG. 2(f), the output waveform of the memory circuit 9 has an inverse time series in units of H with respect to the input waveform [FIG. 2(e)]. The output signal of the first memory circuit and the second memory circuit
The output signal of the memory circuit is applied to the second switch 11. The movable piece of the second switch 11 is a control terminal 27
When the control signal applied to is at H level, it is connected to the output terminal of the first memory circuit 9, and when it is at L level, it is connected to the output terminal of the second memory circuit 10. As a result, at the output end of the second switch circuit 11, a continuous signal whose time sequence is opposite to that of the input signal is obtained in units of 1H. This signal with the reverse time series is sent to the output terminal 2 via the first transmission circuit 7 and the second transmission circuit 12 having the same transfer function G.
is output to. The signal output to the output terminal 2 is an emphasized video signal according to the present invention. V
In a TR (not shown), the thus emphasized video signal is frequency-modulated and then recorded on a magnetic tape (not shown) via a magnetic head (not shown).

During reproduction by a VTR (not shown), a reproduced signal is obtained by scanning a recorded magnetic tape (not shown) with a magnetic head (not shown). By passing this reproduced signal through a frequency demodulator (not shown), the reproduction signal shown in Fig. 2 (q
) to obtain the demodulated signal shown in (). Such a signal is supplied to an input terminal 6 of a de-emphasis circuit 35, not shown in FIG.

The signal supplied to the input terminal 6 is supplied to the third switch 14 via the third transmission circuit 3.

Here, the third transmission circuit 3 transmits the! 1wo nature is the first
is set to be the reciprocal of the transmission circuit 7.

This causes the input signal waveform of the third switch 14 to change to the second
The result is as shown in Figure (f). This signal is switched to IHi by the third switch 14 and is input to the third memory circuit 19 and the fourth memory circuit 2Q. The output signals of the third memory circuit 19 and the fourth memory circuit 2o are switched every 1H by the fourth switch 21 and converted into continuous signals. The third memory circuit 19 and the fourth memory circuit 20 are connected to the first memory circuit 9 or 1.
0, and when the control signals applied to the control terminals 32 and 33 are at H level, the memory circuit 1 shown in 2.
9 and 2o sequentially store the input signals, and when the control signals applied to the control terminals 32 and 33 are at L level,
The memory circuits 19 and 20 output data in a time series opposite to the stored time series.

However, when the control signals applied to the control terminals 30 and 31 are at H level, the movable pieces of the third switch 14 and the fourth switch 21 are pushed to the third memory circuit 19 side, and when the control signals are at L level, they are pushed to the third memory circuit 19 side. is pushed to the fourth memory circuit 2Q side.

The waveform of the signal output to the fourth switch 21 after undergoing such signal processing is shown in FIG. 2(e).

The output signal of the fourth switch 21 is output to the output terminal 6 via the fourth transmission circuit 4. Similarly to the third transmission circuit, the fourth transmission circuit 4 is set so that its transmission characteristic is a reciprocal of that of the first transmission circuit 7 (or second transmission circuit 12). As a result, a video signal having a waveform similar to that shown in FIG. 2(a) is obtained at the output terminal 5.

The waveform shown in Fig. 2 (q) has preshoot and overshoot, so the amount of emphasis is
Although it is the same as the conventional example shown in the figure, a waveform whose peak value is lower than the broken line S is obtained.

In addition, in the above explanation, the first. Second. Although the third and fourth memory circuits 9, 10, 19, and 20 are analog memories (e.g., charge transfer devices from Soprd. with a converter and a D at the output end.
The memory may be a digital memory including a flip-flop circuit or the like.

Furthermore, an A/D converter is provided before the input terminal 1, and the first . The second memory circuits 9 and 1o are configured with digital memories composed of flip-flop circuits, etc., and the first transmission circuit 7 and the second transmission circuit 12 are configured with non-recursible digital filters or recursible digital filters. Even if the D/A converter is configured after the output terminal 6 and the D/A converter is configured as shown in FIG. Unfortunately, a similar configuration is possible for the de-emphasis circuit 36 as well.

Further, in the above explanation, a video signal is used as an input signal, and the first . Second. Third. Fourth memory circuit 9, 10, 1
All the signals applied to the 9.20 or C0NT terminals are expressed in units of H, but depending on the input video signal, their units may be set to nxH (where n is any positive integer). Along with this, the first. Second. 3. Let the capacity of each of the fourth memory circuits 9, 10, 19, and 20 be nxH.

In the above explanation, it was explained as an emphasis circuit, but as shown in Figure 2 (q), the preshoot,
It may be used in circuits intended to provide overshoot.

Effects of the Invention As described above, the signal processing device of the present invention allows the transfer characteristic G of the first transmission circuit (corresponding to 7 in the above-described embodiment) and the second transmission circuit (corresponding to 12 in the same embodiment) to be arbitrarily set. By choosing, signal processing with arbitrary emphasis characteristics with preshoot and overshoot can be obtained.

As described above, when the signal processing device of the present invention is used as an emphasis circuit of a frequency modulation/demodulation system, by giving the waveform a preshoot and an overshoot, it can have the same amount of emphasis as the conventional one. Moreover, it is possible to realize an emphasis circuit in which the peak value of the waveform is significantly lower than that of the conventional one, and effects such as the frequency deviation width can be significantly lowered than that of the conventional one without reducing the amount of emphasis can be obtained.

Alternatively, if the same frequency deviation width as before is used, it is possible to add more emphasis than before, and the effect of improving the S/N ratio of the reproduced signal can be obtained. .

Furthermore, the output signal of the emphasis circuit is further passed through a circuit that reverses the time series so that it is the same as the time series intervention signal of the signal, and is connected to the signal transmission path (in a VTR, the FM modulator, recording amplifier, tape head system, etc.). , a transmission path consisting of a regenerative amplifier and an FM demodulator), the present invention reverses the time sequence of the signal in the de-emphasis circuit, although the time sequence of the signal is reversed in the signal transmission path. Since the present invention includes a circuit for reversing the time series, only two sets in total are required, one set for the emphasis circuit and one set for the emphasis circuit, which has the effect of reducing the circuit scale.

[Brief explanation of the drawing]

Figure 1 is a wiring diagram showing an example of a conventional emphasis circuit.
FIG. 2 is a signal waveform diagram, FIGS. 3 and 4 are schematic block diagrams showing examples of the signal processing device of the present invention, and FIG. 6 is an example of the circuit configuration of the first transmission circuit in FIG. 3. FIG. 3... Third transmission circuit, 4... Fourth transmission circuit, 7... First transmission circuit, 8... First switch, 9... ...First memory circuit, 10...
...Second memory circuit, 11...Second switch, 12...Second transmission circuit, 14...
...Third switch, 19...Third memory circuit, 20...Fourth memory circuit, 21...
・Fourth switch. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (g)

Claims (1)

[Scope of Claims] (i) An emphasis circuit and a de-emphasis circuit are provided, and the emphasis circuit includes a first transmission circuit, a first switch, a first memory circuit, and a second memory circuit. , a second switch, and a second transmission circuit; The second memory circuit has nxH(
However, it is configured to sequentially input signals over a period of time (where n is an arbitrary positive integer and H is a horizontal scanning period), and output the input signals in reverse time series over the next nxH time. , the above-mentioned No. 1. The second transmission circuit is configured so that both transmission characteristics are G. The signal input to the first transmission circuit and processed is
The output signals of the first and second memory circuits are switched by the first switch every nxH time and input to the first memory circuit and the second memory circuit, and the output signals of the first and second memory circuits are switched every nxH time. With the second switch, the signal is switched in an opposite phase to the switching of the first switch, converted into one series of signals, and then outputted via the second transmission circuit; The de-emphasis circuit is the third
The transmission circuit includes a transmission circuit, a third switch, a third memory circuit, a fourth memory circuit, and a fourth transmission circuit, and the third. The fourth memory circuit is configured to sequentially input signals over nxH time and output the inputted signals in reverse time sequence over the next nxH time, and the fourth memory circuit is configured to sequentially input signals over nxH time and output the inputted signals in reverse time sequence over the next nxH time. The fourth transmission circuit is configured so that both transfer characteristics are negative, and the signal input to the third transmission circuit and processed is switched every nxH time by the third switch. and the output signals of the third and fourth memory circuits are inputted to the third memory circuit and the fourth memory circuit, and the output signals of the third and fourth memory circuits are switched by the fourth switch. 2. A signal processing device characterized in that the signal processing device is configured to be switched in a phase opposite to that of the first signal, converted into one series of signals, and then outputted through the fourth transmission circuit. (2) First. The transfer characteristic G of the second transmission circuit is an emphasis circuit, and the third. The signal processing device according to claim 0, characterized in that the transfer characteristic 6 of the fourth transmission circuit is a de-emphasis characteristic.