JPS607279A - Video signal processor - Google Patents

Abstract

PURPOSE:To reduce remarkably a frequency shift width less than a conventional circuit without decreasing emphasis amount by providing pre-shoot and overshoot to a waveform when a video signal processor is used as the emphasis circuit for a frequency modulation/demodulation system. CONSTITUTION:A signal is changed over at each 1H by the 3rd switch 14 and inputted to the 3rd memory circuit 19 and the 4th memory circuit 20. When a control signal applied to control terminals 32, 33 is at H level, the memory circuits 19, 20 store sequentially the inputted signal and when a control signal applied to the control terminals 32,33 is at L level, the said memory circuits 19,20 outputs the signal in an opposite time series as the stored time series. Since the waveform shown in Figure becomes a waveform having pre-shoot and overshoot, a waveform having a peak value lower than that of broken lines S is obtained regardless that the emphasis amount is the same as that of a conventional example.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal processing device that converts a video signal into a signal with desired frequency characteristics, and is used in transmission systems such as video tape recorders and satellite broadcasting. Conventional configurations and their problems In video tape recorders and the like that record and reproduce video signals, a frequency modulation recording method is common. In frequency modulation and demodulation systems, noise in the FM transmission line is
〜Noise, the noise added to the demodulated signal exhibits the so-called triangular noise characteristic, in which the noise level increases as the frequency increases. In order to completely reduce this, before frequency modulation, the level of the mid- and high-frequency range of the input signal is increased (so-called emphasis is applied to increase the frequency deviation width), and after frequency demodulation, the level of the mid- and high-frequency range of the input signal is increased. Signal processing is performed to lower the level of the signal (so-called de-emphasis). However, 1. Since the band of the FM transmission line is limited by the electromagnetic conversion system, there is a limit to the increase in the frequency deviation width depending on the amount of emphasis, which limits the S/N ratio of the reproduced signal. There's a problem/c.

Note that this problem is not limited to video tape recorders.
This problem occurs in all systems that transmit frequency modulated video signals, such as satellite broadcasting.

OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems and
If it is a transmission line, with the same frequency deviation width as before,
It is an object of the present invention to provide a signal processing device that can use a full amount of emphasis more than ever before.

The purpose of this invention is to provide a No. 411 processing device in which the peak value of the waveform is significantly lower than that of the prior art with the same emphasis as the conventional one.

In the back, a signal heat J41i y1'' having any transfer characteristics with a brushed overshoe 1-4;
'It is intended to serve IS.

Structure of the Invention In order to achieve the above object, the present invention includes a first transmission circuit whose transfer function is G to which a human input signal is input, a first switch, a first memory circuit, and a second transmission circuit. a memory circuit, a second switch, a second transmission circuit having the same transmission function cl as the first transmission circuit, and a third switch;
a third memory circuit, a fourth memory circuit, and a fourth switch; Second. Third. Each of the fourth memory circuits is a memory circuit configured to sequentially input signals over nXH time and output the inputted signals in reverse time series over the next nxH time, and The signal input to the signal processing circuit is switched by the first switch every nXH time and is alternately input to the first memory circuit and the second memory circuit, and the signal is input to the first and second memory circuits. The output signal of the second memory circuit is switched by the second switch at an inverse position 4'l to the switching of the first switch, converted into one series of signals, and then sent to the second transmission circuit. is switched every nXH time by the third switch circuit to alternately supply power to the third memory circuit and the fourth memory circuit. The output signal is switched by the fourth switch in an opposite phase to the switching of the third switch, and the output signal is a signal converted into one series of signals.

(However, n is any positive integer, Hlri Water XF k
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the description will be made using an emphasis circuit used in a video tape recorder (VTR) as an example of a video signal processing circuit. Figure 1 shows VH8 system V
This is a conventional 177771 circuit used in 'l'R, etc. In FIG. 1, the video signal applied to the input terminal 1 is outputted to the output terminal 5 through the entire amplifier 7 bus circuit 5o. The emphasis circuit 5o includes a capacitor (capacitance value C
+) csl.

Resistance (m contact value Rb) 52, resistance (tJUc value R
a) Consists of 53. Their value is set to a, for example.

When a video signal as shown in FIG. 2 (2L) is input to the input terminal 1 on the 1111 path, a signal as shown in FIG. 2(b) is obtained at the output terminal 6. In the case of a video tape recorder, the signal shown in Figure 2(b) is frequency-modulated and recorded on a magnetic tape (not shown), but there is a limit to the frequency band of the electromagnetic conversion system that is the FM transmission line. Therefore, the signal is clipped at the point shown by the broken line S in Fig. 2(b) to make the signal as shown in Fig. 2(C),
Frequency modulation. Alternatively, by changing the constants of each part of the emphasis circuit 50 and setting the emphasis amount (=R&) as Rb+Ra, a signal as shown in FIG. 2(d) is generated and frequency modulated. In the case of Fig. 2 (0), there is a problem that waveform distortion occurs, and in the case of Fig. 2 (d), the effect of dl and emphasis becomes -9, and the S/N ratio of the regenerated signal decreases accordingly. There is a problem with doing so.

FIG. 3 shows an emphasis circuit using an example of the signal processing device of the present invention. In Figure 3, input terminal 1
The video signal applied to is supplied to the first transmission circuit 7 whose transfer function is G. The first transmission circuit 7 is an emphasis circuit 22 as shown in FIG. The emphasis circuit 22 is composed of a capacitor (capacitance value C2) 23, a resistor (resistance value Re) 24, and a resistor (resistance value Rd) 25. .

has been established.

When a video signal as shown in FIG. 2(a) is input to such a circuit, a signal as shown in FIG. 2(e) is obtained at the output terminal.

On the other hand, the signal whose level is inverted every 1H is the C0NT terminal 1.
6 has been added. This signal is obtained, for example, by manually inputting a horizontal synchronizing signal included in the input video signal to a full-circuit flop circuit (not shown).

In this way, the signal supplied to the CON T terminal 15 is divided into two series.

One series is applied to the control terminal 26 of the first switch 8 and the control terminal 28 of the first memory circuit 90, and is inverted by the inverter 17, and is applied to the control terminal 27 of the second switch 11 and the second It is supplied to the control terminal 29 of the memory circuit 1o. The other series is routed through a delay circuit 18 composed of, for example, a two-stage mono multi-by-break,
Control terminal 30 of the third switch 14 and control of the third memory circuit 19 ☆; 11: Supplied to the child 32 and
The control terminal 31 of the fourth switch 21 and the control terminal 33 of the fourth memory circuit 20 are inverted at the impark 22 .
supplied to Note that the delay circuit 18 is set to match the delay time of the second transmission circuit 12, which will be described later.

Here, the video signal processed by the first transmission circuit 7 is switched by the first switch 8 every horizontal scan (every 1H), and is transferred to the first memory circuit 9 and the second memory circuit every 1H. The memory circuit 10 is manually operated.

The first memory circuit 9 and the second memory circuit 10 [,
For example, it is composed of an analog memory, and its storage capacity is 1L. When the control signals applied to the control terminals 28 and 29 are at H level, the memory circuits 9 and 10
stores the manually input signals sequentially and connects them to the control terminals 28 and 29.
When the control signal applied to is at L level, the memory circuits 9 and 1 output in a time series opposite to the stored time series. Unfortunately, when the control signal applied to the control terminal 26 is at H level, the movable piece of the switch 8
When i and lj are at L level, they are pushed toward the second memory circuit 10 side. The output waveform of the first memory circuit 9 is as shown in FIG. 2(f).
It is aligned with the input waveform [Fig. 2(e)] and has a reverse time series with H as a unit. The output signal of the first memory circuit and the output signal of the second memory circuit are applied to the second switch 11. The movable piece of the second switch 11 is connected to the output terminal of the first memory circuit 9 when the it, 'll ill signal applied to the control terminal 27 is at H level, and is connected to the output terminal of the first memory circuit 9 when it is at L level. Connected to the output terminal of circuit 1Q. As a result, at the output end of the second switch circuit 11, a continuous signal whose time sequence is opposite to that of the input signal is obtained in units of 1 Li. This signal whose time series is reversed is supplied to the third switch 14 via the first transmission circuit 7 and the second transmission circuit 12 having the same transfer function G. third switch 1
The input signal waveform of No. 4 is shown in FIG. 2(g). This signal is
The signal is switched to 1Hf77 by the third switch 14 and input to the third memory circuit 19 and the fourth memory circuit 20. The output signals of the third memory circuit 19 and the fourth memory circuit 20 are switched every 1H by the fourth switch 21 and converted into continuous signals. The third memory circuit 19 and the fourth memory circuit 20 have the same circuit configuration as the first memory circuit 9 or 10, and the control terminal 3
When the control signal applied to control terminal 32.33 is at H level, the memory circuits 19 and 2o sequentially store the input signals, and when the control signal applied to control terminal 32.33 is at L level, the memory circuits 19 and 2o store the input signals in sequence. The memory circuits 19 and 2o output data in a time series opposite to the stored time series.

Furthermore, the movable pieces of the third switch 14 and the fourth switch 21 are arranged so that the control signal υ applied to the control terminals 30 and 31 is
When it is turned to the 9 side and is at L level, the fourth memory circuit 201
1411 t/to be knocked down.

After receiving such signal processing, the fourth switch (Fig. 2)
The waveform shown in h) is a waveform that has Prinny 1. and Over Seatler, so even though the amount of emphasis is the same as the conventional example shown in Fig. 1, its peak value is lower than the broken line S. is obtained.

In addition, in the above explanation, the first. Second. Third. and the fourth
The memory circuits 9, 10, 19, and 20 are analog memories (
For example, each memory circuit has an A/D conversion word at the input end, and a D at the output end.
/A conversion Showa 4.7 The memory may be a digital memory composed of a flip-flop circuit or the like.

Furthermore, is there A/D conversion before input terminal 1? 1. Second. Third. Fourth memory circuit 9°10.1
9.20' (Constructed with a digital memory composed of a flip-flop circuit, etc., and the first transmission circuit 7 and the second transmission circuit 12 are configured with a non-recursible type digital filter or a liquor/pull type digital filter) However, even if the configuration includes a D/A converter after the output terminal 5, the same operation will occur.

In the above explanation, the video signal υ is used as the input signal, and the first. Second. Third. Fourth memory circuit 9, 10, 1
9.20 or the signals applied to the C0NT terminal are all expressed in units of H, but depending on the input video signal, their units are f, 1 n x H ((!'1. l,, n is any positive integer) ) (accordingly, the capacity of the memory circuit 9.10°19.20 may be set to nX
H).

In the above explanation, it was explained as an emphasis circuit, but as shown in FIG.

Effects of the Invention As described above, the video signal processing device of the present invention has a first transmission circuit (targeted in 7 of the above embodiment) and a second transmission circuit (targeted in 12 of the above embodiment). ) by arbitrarily selecting the transfer characteristic G of
- It is possible to obtain a signal processing device having completely arbitrary transfer characteristics.

As mentioned above, when the video signal processing device of the present invention is used as an emphasis circuit for a full frequency modulation/demodulation system, it can have the same amount of emphasis as the conventional one by providing a waveform with a bristled overshoe. Moreover, it is possible to realize an emphasis circuit in which the peak value of the waveform is significantly lower than that of the conventional method, and effects such as the frequency deviation width can be significantly reduced compared to the conventional method without decreasing the amount of emphasis can be obtained.

Alternatively, if we use the same frequency deviation width as before, we can add more emphasis than before,
This has the effect of improving the SN ratio of the reproduced signal.

[Brief explanation of the drawing]

Figure 1 is a wiring diagram showing an example of a conventional emphasis circuit.
2 is a signal waveform diagram, FIG. 3 is a schematic block diagram showing an example of the signal processing device of the present invention, and FIG. 4 is a wiring diagram showing an example of the circuit configuration of the first transmission circuit in FIG. 3. be. 7...First transmission circuit, 8...First switch, 9...First memory circuit, 10...
...Second memory circuit, 11...Second switch, 12...Second transmission circuit, 14...
-Third switch, 19...Third memory circuit, 20...Fourth memory circuit, 21...
・Fourth switch. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (2)

[Claims] (1) A first transmission circuit whose transmission characteristic is G, a first switch, a first memory circuit, a second memory circuit,
a second switch, a second transmission circuit having the same transfer function 0 as the first transmission circuit, a third switch, a third memory circuit, a fourth memory circuit, and a fourth transmission circuit; The first switch is configured to include a switch. Second. Third. Each of the fourth memory circuits sequentially receives a video signal over nXH time (where n is an arbitrary positive integer and H is horizontal scanning time), and receives the input video signal over the next nXH time. The video signal input to the first transmission circuit is configured to be output in reverse time series, and the video signal input to the first transmission circuit is switched by the first switch for nXH time, and then output to the first memory circuit. and the second three memory circuits, and the output signals of the first and second memory circuits are switched by the second switch in an opposite phase to the switching of the first switch. After being converted into one series of signals, the signals are passed through the second transmission circuit, switched by the third switch circuit for nXH time, and input into the third memory circuit and the fourth memory circuit. ,
The output signals of the third and fourth memory circuits are switched by the fourth switch in an opposite phase to the switching of the third switch, and output signals are converted into one series of signals. A video signal processing device characterized in that it is configured as follows. (2) First. Second. Third. The switching timing of the fourth switch and the switching timing of the first switch. Second. Third. The video signal processing device according to claim 1, characterized in that the input and output switching timing of the fourth memory circuit is based on a horizontal synchronizing signal.