JPH01137464A - Video and audio reproducing device - Google Patents

Abstract

PURPOSE:To conform with various kinds of user's objects by providing a read/ write control circuit having the functions of a control means, a write means, and a read means and a variable setting part. CONSTITUTION:When an audio output operation button is operated in a fast reproducing mode, a memory 17 is controlled to the write state for a prescribed time by a read/write control circuit 16 and a fast reproduced audio signal is written in the memory 17 set to the write state, and thereafter, the memory 17 is controlled to the read state by the read/write control circuit 16. Audio signal data written in the memory 17 is reproduced from the memory to recognize the contents of the reproduced audio signal during fast reproducing. At this time, data is written in and read from the memory 17 by read and write clocks variably set by a variable setting part 35. Thus, certain-speed or double- speed reproduced sound are obtained in accordance with the double speed of fast reproducing by the control of the variable setting part 35.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video disc player having a normal playback function and a high-speed playback function of video signals and audio signals recorded on recording media such as video discs and video tapes. , relates to video and audio playback devices such as video tape recorders.

[Conventional technology]

In general, video and audio playback devices such as video disc players and video tape recorders have normal playback functions as well as
Although a high-speed playback function called a picture search is provided, the audio output is usually muted so that a high-speed playback audio signal that is difficult to identify is not output during a picture search.

However, with the recent diversification of user needs regarding video and audio playback equipment, depending on the purpose of use, there may be times when users want to listen to the content of high-speed playback audio signals during search mode.
Conventional configurations cannot meet such demands.

Therefore, as described in Japanese Patent Application Laid-Open No. 58-8898.4 (CHO4B 1106), a digital signal obtained by A/D converting the output of a receiving circuit is stored in a random access memory while being sequentially and repeatedly updated. There is a system that allows you to repeatedly listen to the received content that you could not fully hear.In this way, a memory is used to temporarily store the high-speed playback audio signal in the search mode in the memory. , it is conceivable to read this out so that the content of the high-speed reproduction audio signal can be heard.

[Problem that the invention seeks to solve]

However, when applying the method in the above publication, it is not possible to change the writing speed when writing to memory and the reading speed when reading from memory in search mode, so it cannot be applied to devices with high-speed playback functions. However, there is a problem in that the content of the audio signal during high-speed playback cannot be recognized, and the intended use cannot be satisfactorily met.

Therefore, the technical object of the present invention is to make it possible to recognize the content of an audio signal reproduced at high speed during high-speed reproduction mode, and to also be able to hear it as a constant-speed or double-speed reproduction sound.

[Means for solving problems]

Means for solving the problems of the prior art described above will be explained using FIG. 1 corresponding to an embodiment.

That is, a normal playback function for video and audio signals recorded on a recording medium such as a videotape.

In a video/audio playback device such as a video tape recorder having a high-speed playback function, the present invention provides a method in which, in the high-speed playback mode, after controlling the audio signal storage memory αη to a writing state for a predetermined period of time by operating an audio output operation button, It functions as a control means to control the memory Q″i) to a read state, and synchronizes a high-speed reproduction audio signal of a predetermined time with a write clock by a clock generation circuit a9 to the memory αη controlled to a write state. function as a writing means for writing data from the memory αη controlled to the read state;
a write/read control circuit ai19 having functions as a read means for reading out the audio signal written in η in synchronization with a read clock by a clock generation circuit α; and a pitch of the write clock and the read clock. A variable setting section (3' IJ and capacitor (to), (31), 關, and @41 is provided for variable setting of each switch.

[Effect]

Therefore, according to the present invention, in the high-speed playback mode, by operating the audio output operation button, the memory αη is controlled to be in the write state for a predetermined period of time by the write/read control circuit Qli, and the high-speed playback audio After the signal is written to the memory αη in the write state, the write/read control circuit αe writes the memo! J
Q7) is controlled to the read state, the audio signal data written to the memory αη is reproduced from the memory αη, and the contents of the reproduced audio signal during high-speed reproduction can be recognized.

At this time, the variable setting section writes the memory alpha power using the variably set write and read clocks.

Since reading is performed, the variable setting section @Unit's controller/
With L/, a constant speed or double speed reproduction sound can be obtained corresponding to the double speed of high speed reproduction.

〔Example〕

Next, the present invention will be explained in detail with reference to the left side of the drawing showing an embodiment thereof.

First, a description will be given of FIG. 1, which shows an embodiment in which the present invention is applied to a video tape recorder for recording and reproducing linear audio tracks.

In Figure 1, (1) is an antenna, C2 is a tuner to which the output of antenna (1) is input, (31 is a tuner (21) to which a video signal selected and received is input, A demodulating video circuit (4) records the video signal modulated by the video circuit 131 on a video tape (not shown) which is a recording medium in the recording mode.

In the playback mode, the videotape is played back and the video circuit (
31 is a recording and reproducing unit having a rotating video head that outputs a reproduced video signal; (51 is an RF converter; in the reproduction mode, the reproduced video signal demodulated by the video circuit (3) is inputted and is used for television broadcasting; It is converted into a frequency and output to the antenna terminal of the subsequent television receiver.

+61 is a fixed audio recording/reproducing head, r7) is a recording contact (r
).

The first recording/reproducing switch, C8, whose reproduction contacts (p) were connected to the audio output terminal of the tuner (21) and the audio recording/reproducing head (6), respectively, was connected to the switching piece of the first switch (7). The first amplifier (9) performs AC bias processing on the audio signal from the tuner (2) that is input through the switch C7) and the first amplifier 181 when in recording mode, and outputs it to the audio recording/reproducing head (6). The bias circuit, aO is the second switch for switching, and the system controller described later.
Accordingly, the contact is switched to an on contact (10a) and an off contact (10b) in the still mode, search mode, and other modes, respectively.

0] J is the second amplifier into which the audio signal via the second switch aO is input, (2) is the audio signal from the second amplifier αD that is output to the RF converter (61) and the RF converter r5.
1 is a mute circuit, C3 is an operation unit having operation buttons such as playback, recording 9 rewind, search, and still, and an audio output operation button that is operated when the search button is operated, and α is a control means. This is a system controller (hereinafter referred to as a system controller) which is a system controller (hereinafter referred to as a system controller), and the above-mentioned recording/reproducing unit (4) responds to button operations on the operation unit r13.

1st. 2nd switch C7), αO, mute circuit (6)
control some parts of each.

C9 is a 10th bus filter (hereinafter referred to as 1st LPF) to which the audio signal is input via the first amplifier (8), Q
f9 is a write/read control circuit consisting of A/D, D/A conversion IC, etc. It has functions as a writing means and a reading means, and receives control signals from the system controller α4, AM, etc. A sound memory αη for storing audio signals consisting of
The built-in ADM conversion circuit a81 generates an analog audio signal from the first LPF l'l$ in synchronization with the write clock generated by the built-in clock generation circuit Ill. is A/D converted and differentially encoded, and is written to the memory aη controlled in the write state in synchronization with the write clock, and from the memory αη controlled in the read state, the clock generation circuit a
The stored data is read out in synchronization with the readout clock by the ADM conversion circuit (to), and the differential data is combined and D/A converted by the ADM conversion circuit (to) to form and output a readout audio signal.

(1) is the third switch for specifying the number of repetitions of the write/read control circuit αQ in the still mode. Second
A contact (20b) and a third contact for specifying 0 times (20e,
), each contact (20a) to (20c) is connected to the system controller α chrysanthemum, the switching piece is grounded, and according to the switching of the 8th switch (e), writing/reading in the still mode by the system controller α4 is performed. The number of repetitions of writing and reading by the control circuit αQ is controlled.

The penalty is the fourth switch for specifying the write time of the write/read control circuit aOO in still mode, and the first contact for specifying 6 seconds (
21&) and a second contact (21b) for specifying 3 seconds, both contacts (21&) and (21b) are connected to the system controller aO, the switching piece is grounded, and the fourth switch (to) is switched. Accordingly, switching control of the write time of the write/read control circuit α0 in the still mode is performed by the system controller α4.

The wire is a 20th bus filter (hereinafter referred to as No. 2LPF), the switching piece of the wire is connected to the clock frequency setting terminal of the clock generation circuit, and the still contact (2
: (a) is the 6th switch for switching which switches to the search contact (23b), (c) is the 6th switch for setting the pitch of the writing and reading clock in the still mode, and the switching piece is the still contact (23b). 23B), and the on contact (24B
), switches to the off contact (24b).

(to) is the seventh switch for changing the pitch of the read clock in still mode, the switching piece is connected to the on contact (24a), and the high speed, constant speed, and low speed contacts (25R).

(25b) and (25c) are eight capacitors (e) with different capacities for the oscillation time constant of the clock generation circuit α, @
, (to) are connected, and by the switching operation of the seventh switch (to), one of the capacitors (e) to (to) is selected and the oscillation frequency of the clock generation circuit Q'J is set. is selected and the pitch of the read clock of the memory Q7) in the still mode is variably set.

Note that the capacitor @ is connected to the off contact (24b), and the oscillation frequency of the clock generation circuit α during memory writing in the still mode is fixed.

The wire is used to switch between writing and reading in search mode.

At the 8th switch for changing the pitch of the write clock, connect the open 1st contact (29a) and the capacitor with a different capacity (
7) and @l), respectively. Third contact (2
9b) and (29c), and when the sound output operation button of the operation unit αJ is operated in the search mode, the second
Alternatively, the writing clock is set by switching to the third contact (29b) or (29c), and then the first contact (29c)
Switch to a).

At this time, the 8th switch 4, the 2nd. 8th contact (29b)
, (290) shall be made by the control output of the system controller Q4) depending on the speed of high-speed reproduction, and the switching of the clock generating circuit QIJ shall be performed by selecting the capacitor (to), 01). The oscillation frequency is switched and selected, and the pitch of the write clock of the memory αη in the search mode is variably set. (Company) is the 9th switch for pitch switching of the read clock in search mode, and capacitors (T) with different capacities.
, @4, respectively. Second contact (32B'
), (S2h), and depending on the speed of high-speed playback, the ninth switch connected to the control output of the system controller A4 is switched, and the capacitors (331, (34
1 is selected, the oscillation frequency of the clock generating circuit σ9 is switched, and the pitch of the read clock of the memory αη in the search mode is variably set. 9th switch wire, 02 and each capacitor (
to), (311, (331, H) allows the variable setting section (
) is configured.

Note that the audio circuit (AD) is constituted by the circuit surrounded by the one-dot chain line in FIG.

Next, the operation of the embodiment will be explained.

First, in the recording mode, the video signal tuned by the tuner (2) which inputs the output of the antenna (1-) is
After being inputted to the video circuit +31 and subjected to FM modulation, it is recorded on a videotape by the recording and reproducing section (41).

At the same time, the audio signal tuned by the tuner (2) is input to the audio circuit (AD), and the input audio signal is input to the first amplifier r81 via the first switch (7) and amplified. Thereafter, the bias circuit (93) applies an alternating current bias, and the signal is supplied to a fixed audio recording/reproducing head (61) to record the audio signal on the video tape.

Next, in the normal playback mode, the playback signal played back by the recording and playback section (41) is demodulated by the video circuit (3) and inputted to the RF converter (5) as a playback video signal, and the R
By F converter 15+! It is converted into l'V broadcast radio waves and supplied to the antenna terminal of the television receiver.

At the same time, the output reproduced by the audio recording/reproducing head (6) is inputted to the first amplifier (8) via the first switch (7), and the off contact of the second switch αO is input as an amplified reproduced audio signal. (10b) is input to the F converter 15) via the second amplifier α and the mute circuit @, and is input to the F converter r5).
1, the signal is supplied to the antenna terminal of the television receiver together with the above-mentioned reproduced video signal.

Next, the audio circuit (AD) writes to the memory aη.

The read operation will be explained.

First, when the normal playback mode is set by operating the operation unit 11, the write/read control circuit aQ is controlled by the control output of the system controller a4, the memory αη is controlled to the write state, and the audio recording/reproducing head (6) is set to the normal playback mode. The reproduced audio signal is input to the ADM converter (to) of the write/read control circuit OQ via the first LPtJ5, and is subjected to AID conversion and differential encoding in synchronization with the write clock generated by the clock generation circuit. , a memo that is controlled to be in the write state by the write/read control circuit aS! J (1?) and stored cyclically in synchronization with the write clock. Note that the capacity to be stored in the memory aη is determined by inputting the control output of the system controller α4 to the write/read control circuit α, depending on the selection of the write time of 6 seconds or 3 seconds by the fourth switch @. It is determined based on the control output of the control circuit QllG.

Next, when the operation section (to) is operated to set the still mode, the write/read control circuit 0119 transfers the memory αη
is controlled to the read state, and the stored data is read from the memory αη by the write/read control circuit Qe in synchronization with a read clock having a frequency corresponding to the selection of the capacitor by the switching selection of the seventh switch (to). After the read data is combined with the difference data by the ADM converter (to), it is converted to 1)/A and is output as a read audio signal via the second Lrp (22).
It is input to switch α1. In addition, the mute circuit @ is
Each time the mode is switched, it opens for about 1 second to prevent the output of audio signals.

Also, if you set the search mode, that is, high-speed playback (double speed or multiple speed) mode by operating the operation unit G, and operate the audio output operation button of the operation unit α3 during the high-speed playback mode, the system controller α4 will output The write/read control circuit a6 is controlled by the controller μ output, and the write/read control circuit α0 first controls the memory αη to be in the writing state for 5 seconds. The audio signal is sent to the write/read control circuit QQOA via the first LPF (to).
A/D conversion and differential encoding are performed in synchronization with the write clock that is input to the DM converter (to) and generates a clock generation circuit a, and is controlled to the write state by the write/read control circuit Qft. A memo ')Q7)K is input, and the high-speed reproduction audio signal is written into the memory αη in synchronization with the write clock.

At this time, the pitch of the write clock is changed according to the speed of the high-speed playback by switching the eighth switch t22hg of the variable setting section (to) of the system controller α4,
It is set by selecting either the capacitor (on or till), and the pit rate is higher than the pit rate in still mode for a short period of time (for example, memory Q
If η is 256 Kbitg, the pit rate is 256 K.
Writing is performed in BF4 (1 second).

Next, after writing to the memory Q7), the controller output from the system controller α4 controls the write/read control circuit OQ and the eighth switch 4, and the write/read control circuit (l) controls the memory αη. At the same time, the eighth switch 4 switches to the first contact (29a), and the capacitor (3, ) The storage data is read from the memory αη by the write/read control circuit Q6 in synchronization with the read clock having a frequency corresponding to the selection of After that, it is D/A converted and sent as a read audio signal to the 21st PF@, the 2nd switch aO9, the 2nd ang aD, and the mute circuit (to).
The signal is input to the RF converter tS> via the RF converter tS>, and the reproduced sound during high-speed reproduction is output from the receiver.

Note that at the beginning of reading, the mute circuit α operates for one second.

At this time, as mentioned above, the pitch of the read clock is
For controller/I' output of Cisco α4! ! The 9th switch → of the ljJ change setting section is switched, and the capacitor (
The pit rate (for example, if the memory αη is 255 Kbits, the pit rate) is set by selecting either 8K bits or 255 Kbits.
BPS), reading is performed for 5 seconds, and depending on the read clock pitch, for example, a constant speed playback sound or a double speed playback sound can be heard.

Therefore, according to the embodiment, the audio signal reproduced at high speed during the high-speed reproduction mode can be easily heard by operating the audio output operation button. Although the playback was only possible at double speed, it is now possible to play back and listen to audio at about five times the speed, and it can also be used for cueing and fast listening, and can meet the various purposes of use by users.

Note that in order to prevent the mute circuit from operating when reading the memory in the high-speed playback mode, for example, as shown in FIG. AT and sound memory αi are provided, and two-contact changeover switches (381, (37)) are provided between the first LPF (to), the second LPF @ and the ADM conversion circuit (to) 1 ml, respectively, to switch these alternately. Alternatively, while writing to one memory αη, the other memory αi may be read, and while writing to the other memory αi, one memory αη may be read, so that continuous playback sound can be obtained. However, in Fig. 2, like the variable setting section (g), the variable setting section variably sets the pitch of the write clock and read clock by the clock generation circuit σ4 during high-speed reproduction of the write/read control circuit a4. This is the settings section.

Note that the present invention is not limited to the above embodiments.

Furthermore, it goes without saying that the present invention can be applied to video/audio playback devices other than video tape recorders.

〔Effect of the invention〕

As described above, according to the video and audio playback device of the present invention,
Audio signals played at high speed during high-speed playback mode can be easily heard by operating the audio output operation button, and can be easily played back at double speed by switching the variable setting section. However, it is also possible to play back and listen to audio at about 5x speed, and it can also be used for cueing and fast listening, and can be used for a variety of purposes by users.

[Brief explanation of the drawing]

1 and 2 each show an embodiment of the video/audio playback device of the present invention, FIG. 1 is a block diagram of the first embodiment, and FIG. 2 is a block diagram of a part of another embodiment. . target...operation unit, QQ, ad...write/read control circuit, αη. αi...Memory, rm, at;i...Clock generation circuit, mra, ad...Variable setting section.

Claims (1)

[Claims] (1) In a video and audio playback device that has a normal playback function and a high-speed playback function for video and audio signals recorded on a recording medium, when in high-speed playback mode, the audio signal storage memory is set to a specified value by operating an audio output operation button. After controlling to time writing state,
control means for controlling the memory to be in a read state; writing means for writing a high-speed playback audio signal for a predetermined period of time into the memory controlled to be in a write state in synchronization with a write clock; A reading device for reading out the audio signal written in the memory from the memory in synchronization with a read clock; and a variable setting section for variably setting the pitch of the write clock and the read clock, respectively. A video and audio playback device.