JPH0548928A - Video signal processor - Google Patents

Abstract

PURPOSE:To reduce the capacity of a use memory, to suppress the processing delay and to convert a video signal to a desired frequency characteristic. CONSTITUTION:An input video signal from an input terminal 1 is supplied to signal processing blocks 2 and 3. At a signal processing block 2, the video signal is classified for a prescribed section sufficiently shorter than 1H by a time base inverting circuit 4 and the time base is inverted for the section. After for the output signal of the time base inverting circuit 4, the prescribed processing is performed by a transmitting circuit 6, the time base is inverted again for the same section by a time base inverting circuit 5. Even at a signal processing block 3, the same processing is performed by the time base inverting circuit 5, the transmitting circuit 6 and a time base inverting circuit 9, and the section to be classified is hourly dislocated more than the section at the signal processing block 2. A switching circuit 10 selects the output signal of the signal processing blocks 2 and 3 alternatively with the time length of the section as a cycle and supplies it to a transmitting circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for recording / reproducing or transmitting a video signal, and more particularly,
The present invention relates to a video signal processing device that converts a frequency characteristic of a video signal into a desired characteristic.

[0002]

2. Description of the Related Art When a video signal is recorded / reproduced on a magnetic recording medium or transmitted, a method of frequency-modulating the video signal is widely used. In general, noise generated in a transmission system that performs frequency modulation / demodulation has a so-called triangular noise characteristic in which the noise level increases as the frequency increases. Therefore, the input video signal is usually subjected to pre-emphasis processing in which high frequency components (high frequency components) are level-enhanced, and then frequency-modulated for recording or transmission, and after frequency demodulation, de-emphasis. A method of reducing the level of the high frequency component emphasized by the pre-emphasis processing by the processing is used.

In contrast to the pre-emphasis characteristic, the de-emphasis characteristic needs to be completely opposite. However, there are variations in the elements that realize the circuits of the respective characteristics, and the de-emphasis characteristic is different from the pre-emphasis characteristic. Therefore, the de-emphasis characteristic may not be completely opposite and mismatch may occur. In addition, in order to prevent the extreme increase of the peak value caused by the emphasis process, it may be difficult to always realize the complete inverse characteristic when the nonlinear characteristic that changes the emphasis amount according to the signal level is applied. is there. When the pre-emphasis characteristic and the de-emphasis characteristic are mismatched as described above, distortion remains in the demodulated video signal, which is a major factor of image quality deterioration.

Therefore, it is desirable to realize the pre-emphasis circuit and the de-emphasis circuit with a circuit having a linear phase characteristic. According to this, distortion such as pre-shoot and post-shot caused in the video signal due to the mismatch of the pre-emphasis characteristic and the de-emphasis characteristic is added symmetrically on the screen. Become less noticeable. Even when the non-linear characteristic that changes the emphasis amount according to the signal level is not applied, even if the pre-emphasis circuit and the de-emphasis circuit are realized by a circuit having a linear phase characteristic, even if the same emphasis amount is used. Since the pre-shot and the post-shot are added symmetrically, it is possible to prevent an extreme increase in the peak value after pre-emphasis.

Conventionally, in order to realize a circuit having a linear phase characteristic in which such pre-shot and post-shot are symmetrically added, for example, Japanese Patent Laid-Open No. 60-72 is used.
As described in Japanese Patent Publication No. 79, by using two sets of transmission circuits having the same characteristics and two sets of time axis inversion circuits, a video signal processed by the first transmission circuit is processed by the first time axis inversion circuit. , The time axis reverse processing is performed for each section of the horizontal scanning cycle (line), and the pre-shoot and the post-shoot are performed by the second transmission circuit.
In this case, the second time axis reversing circuit is used to re-add the time axis reversal processing to the original time axis video signal again by the second time axis reversing circuit.

[0006]

By the way, in the above-mentioned prior art, in order to reverse the time axis of the video signal, the video signal is sequentially written to the memory line by line and read out in the reverse order of the writing. Therefore, at least two systems of memories are required to continuously perform such time axis inversion processing. Therefore, when two time axis inversion processing circuits are used, there is a problem that a memory capacity corresponding to at least four lines of data is required. Further, since the processing delay of one horizontal scanning period (H) occurs due to one time axis reversal processing, there is a problem that the processing delay of at least 2H occurs according to the above-mentioned conventional technique.

An object of the present invention is to solve the above problems and provide a video signal processing apparatus capable of processing a video signal with a smaller memory capacity and a smaller processing delay.

[0008]

In order to achieve the above object, the present invention provides a first section in which an input video signal is sequentially divided into first sections having a predetermined time width and signal processing is performed for each of the first sections. Signal processing means and second signal processing for sequentially dividing the input video signal into a second section having a time width equal to and different from that of the first section and performing signal processing for each of the second sections. Means and each of the first of the output signals of the first signal processing means
And a synthesizing means for synthesizing a signal in a part of a period of the section and a signal in a part of a period of each of the second sections of the output signals of the second signal processing means to form a continuous video signal. , Third signal processing means for processing the output video signal of the synthesizing means.

[0009]

In the first and second signal processing means, the same input video signal is processed at the same time, but the signal processing in these is performed for each section of a predetermined time width, and such section is the first signal processing. The timing is different between the means and the second signal processing means. When the processing is performed for each section in this way, a signal discontinuity or a discontinuity of the signal is processed immediately after the section boundary, so that a transient corresponding to the impulse response occurs. Therefore, according to the present invention, the synthesizing means allows the first signal of each of the first sections in the output signal of the first signal processing means.
The signal of the partial period and the signal of the partial period of each second section in the output signal of the second signal processing means are combined. It can be set so as to avoid a portion where a transient occurs. Therefore, a video signal without signal discontinuity or transient can be obtained from the synthesizing means.

Therefore, the time widths of the first and second sections are set shorter than one horizontal scanning period of the video signal unless the output video signal of the synthesizing means includes signal discontinuity or transient. It will be possible. These first,
The time width of the second section may be about twice as long as the time required for the impulse response of the signal processing to sufficiently converge. From this, the time widths of the first and second sections are the same as those of the video. It can be shortened to the length of several tens of sample data of the signal. Therefore, the delay time of the video signal due to the signal processing by the first and second signal processing means becomes very short, and
It is possible to reduce the capacity of the memory used when the time axis reverse processing is performed by the first and second signal processing means.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a video signal processing device according to the present invention, in which 1 is an input terminal of a video signal,
2, 3 are signal processing blocks, 4 and 5 are time axis inversion circuits,
Reference numerals 6 and 7 are transmission circuits having a transfer function G, 8 and 9 are time axis inversion circuits, 10 is a switching circuit, 11 is a transmission circuit having a transfer function G equal to that of the transmission circuits 6 and 7, and 12 is an output terminal of a video signal. Is.

In the figure, a video signal is input from the input terminal 1 and supplied to the signal blocks 2 and 3. In the signal processing block 2, the input video signal shown in FIG. 2 (a) is divided by the time axis reversing circuit 4 into sections of a predetermined time width t, and each section is shown in FIG. 2 (b). As shown, processing for reversing the time axis is performed. The time-axis inversion signal output from the time-axis inversion circuit 4 is pre-emphasized by the transmission circuit 6 and becomes a signal in which a high-frequency component is emphasized and post-shot is added, as shown in FIG. The output signal of this transmission circuit 6
It is divided into the same sections as in the time axis reversing circuit 4, and the time axis is reversed again for each section to obtain the video signal of the original time axis as shown in FIG. 2 (d). The output signal of the time axis reversing circuit 8 is supplied to the a side of the switching circuit 10 as the output signal of the signal processing block 2.

The post-shoot added by the high-frequency component enhancement processing of the transmission circuit 6 becomes a pre-shoot as shown in FIG. 2D by the time-axis inversion processing by the time-axis inversion circuit 8. .. Further, as shown in FIG. 2D, due to the division and combination in the time axis inversion processing by the time axis inversion circuits 4 and 8, a signal discontinuity or this discontinuity is generated in the vicinity of the boundary between adjacent sections. Transient generated by being processed by the transmission circuit 6 occurs. However, in the signal shown in FIG. 2 (c), discontinuity or transient of these signals occurs from the start point of the section. Therefore, in the signal shown in FIG. It will occur just before the end point.

In the signal processing block 3, the input video signal (having the same waveform as that in FIG. 2A) shown in FIG. 3A from the input terminal 1 is supplied to the time axis inversion circuit 5 and the time axis inversion circuit 4. Although they have the same predetermined time width t, they are divided into sections different from the time axis reversing circuit 4, and the processing of reversing the time axis is performed for each section as shown in FIG. 3B. The time-axis inversion signal output from the time-axis inversion circuit 5 is pre-emphasized by the transmission circuit 7 and becomes a signal in which a high frequency component is emphasized and post-shot is added, as shown in FIG. The output signal of the transmission circuit 7 is the time axis reversal circuit 9
3, the time axis reversing circuit 5 is divided into the same sections, and the time axis is reversed again for each section.
As shown in (d), the original time-axis video signal is obtained.
The output signal of the time axis reversing circuit 9 is supplied to the b side of the switching circuit 10 as the output signal of the signal processing block 3.

Here, the post-shoot added by the high-frequency component emphasis processing of the transmission circuit 7 becomes a pre-shoot as shown in FIG. 3 (d) by the time-axis inversion processing by the time-axis inversion circuit 9. .. Further, as shown in FIG. 3D, due to the division and combination in the time axis inversion processing by the time axis inversion circuits 5 and 9, as in FIG. 2D, the signal discontinuity and the transient are adjacent to each other. However, since the section in the time axis reversing circuits 5 and 9 is different from the section in the time axis reversing circuits 4 and 8 of the signal processing block 2, the discontinuity of these signals and the transient generation position are shown in the figure. Two
Different from (d).

The switching circuit 10 is closed to the side a and the output signal of the signal processing block 2 is selected during the periods a1, a2, a3, ... Of the sequential sections shown in FIG.
In the period of b1, b2, b3, ... Of the sequential sections shown in (d), the output signal of the signal processing block 3 is selected by closing to the b side. Here, the b1 period is between the a1 period and the a2 period, and similarly, hereinafter, the bi period (i = 1, 2, 3, ...
...) is between the ai period and the a (i + 1) period. Further, the period a1, a2, a3, ... Starts from the start point of the section, and the same applies to the period b1, b2, b3 ,. And signal discontinuities and transients, as described above,
Since it exists near the end point of each section, a continuous video signal without signal discontinuity or transient is obtained from the switching circuit 10 as shown in FIG. 4A. Switching circuit 1
In the output signal of 0, the high frequency component is emphasized in the transmission circuit 11 and post-shot is added, and as shown in FIG.
The output signal is output from the output terminal 12 as a video signal to which pre-shot and post-shoot are added symmetrically.

As described above, the two systems of the signal processing block 2 and the signal processing block 3 divide the same video signal into the same time width t and the time-shifted sections to perform the time axis reversal processing. , The division due to the time axis reversal processing, the signal discontinuity caused by the synthesis, or the transient caused by the processing of this discontinuity by the transmission circuit does not occur at the same timing in the signal processing blocks 2 and 3, , Signal processing blocks 2, 3
It is possible to obtain a signal to which a preshoot and a postshoot have been added from the output signal of 1 without the influence of signal discontinuity and transient.

At this time, the transients generated in the output signals of the signal processing blocks 2 and 3 affect the output signals of the transmission circuits 6 and 7 for a predetermined period of time.
It suffices to set the time width t of the sectioned section to at least twice the time required for the impulse responses of the transmission circuits 6 and 7 to sufficiently converge. Furthermore, by setting the time lag of the sections in the signal processing blocks 2 and 3 to t / 2, the signal processing blocks 2 and
It is possible to select and combine the video signals from the output signals of No. 3 without the influence of discontinuity and transients. For example, when the impulse responses of the transmission circuits 6 and 7 are sufficiently converged by about 12 samples, the time width t of the section to be divided is set to 32 samples, which is twice or more that time, and the signal processing block 2 The time lag in the section 3 may be 16 samples.

FIG. 5 shows the time axis inversion circuit 4 in FIG.
5 is a block diagram showing a specific example of 5, 8, and 9;
3 is an input terminal of a digitized video signal (hereinafter referred to as a digital video signal), 14 is an output terminal of a digital video signal, 15 is an input terminal of a control signal TR, 16 is a switching circuit, 17 and 18 are memories, 19 Is a switching circuit, and 20 is an inverting circuit.

In the figure, it is assumed here that digital signal processing is performed. Therefore, the digitized video signal is input from the input terminal 13. The input video signal is supplied to the switching circuit 16 controlled by the control signal TR input from the input terminal 15. This control signal TR
Irrespective of the input video signal, for example, "L" in units of 32 sample data of the digitalized input video signal.
(Low level) and "H" (high level) are alternately inverted, and the switching circuits 16 and 19 are switched in response to this.

When the control signal TR is "H", the switching circuits 16 and 19 are closed to the side a, and the TR signal 17 is set to the write operation mode by the control signal TR, and the level is inverted by the inverting circuit 20. The TR memory 18 is set to the read operation mode by the generated control signal. Therefore, the video signal from the input terminal 13 is supplied to the memory 17 via the switching circuit 16, and the sample data is sequentially written to a predetermined address in the memory 17. During this period, the sample data is sequentially read from the memory 18 and output from the output terminal 14 via the switching circuit 19.

After that, when the control signal TR becomes "L" after the lapse of a predetermined 32 sample data period, the switching circuit 1
6, 6 and 19 are switched to the b side, the memory 17 is set to the read operation mode, and the memory 18 is set to the write operation mode. Therefore, the video signal input from the input terminal 13 is supplied to the memory 18 via the switching circuit 16, and the sample data is sequentially written to a predetermined address in the memory 18. Further, from the memory 17, the control signal TR
When 32 is "H", the 32 sample data written are read out in the reverse order to the written order,
It is output from the output terminal 14 via the switching circuit 19.

Then, the period of "L" of the control signal TR is 3
When the control signal TR becomes "H" again after two sample data periods have elapsed, the switching circuits 16 and 19 are closed to the side a, the memory 17 is set to the write operation mode, and the memory 18 is set to the read operation mode. Therefore, as described above, the video signal input from the input terminal 13 is written in the memory 17, and the 32 samples written when the control signal TR is "L" is written in the memory 18 first. Data is read out in the order reverse to the order in which the data is written, and the switching circuit 19
Is output from the output terminal 14 via.

As described above, the control signal TR is "L",
Every time the level is inverted to “H”, the memories 17 and 18 alternately read and write, and the input video signal is sequentially set to 3
It is divided into two sample data units and the time axis is reversed for each interval. According to this, one time axis reversing circuit only needs to have two memories each having a capacity corresponding to 32 sample data, so that the time axis reversing circuit can be configured with a small capacity memory.

When the time axis reversing circuit having the above configuration is used in the signal processing blocks 2 and 3 in FIG. 1, the control signal TR input to the time axis reversing circuits 4 and 8 in the signal processing block 2 (FIG. 5). The control signal TR input to the time axis inversion circuits 5 and 9 in the signal processing block 3 has the same period but different level inversion timings. For example, any control signal TR is inverted to “L” and “H” for every 32 sample data of the video signal, but with respect to the control signal TR supplied to the time axis inversion circuits 4 and 8 in the signal processing block 2, The level of the control signal TR supplied to the time axis inversion circuits 5 and 9 in the signal processing block 3 is inverted with a delay of, for example, 16 sample data.

Further, in FIG. 1, the signal processing block 2
In the time axis reversing circuits 4 and 8 in FIG.
The sections divided by 19 must be equal. Therefore, the level inversion timing of the control signal TR in the time axis inversion circuit 8 is delayed from the level inversion timing of the control signal TR in the time axis inversion circuit 4 by the time required for the signal processing in the transmission circuit 6. It For example, assuming that the signal processing time of the transmission circuit 6 is a time corresponding to two sample data, the level inversion timing of the control signal TR in the time axis inversion circuit 8 is higher than the level inversion timing of the control signal TR in the time axis inversion circuit 4. Delayed by two samples. This means that the time axis inversion circuits 5 and 9 in the signal processing block 3 are
The same is true for.

As described above, in this embodiment, the number of time axis inversion circuits is increased because two signal processing blocks are required as compared with the prior art, but the memory required for one time axis inversion circuit. The capacity can be reduced to a few tenths of the conventional one, and therefore, the memory capacity of the entire video signal processing device can be significantly reduced, and the circuit scale and cost can be reduced.

Further, in the prior art, the time required for the time axis inversion processing is delayed by several H because writing and reading are performed in the memory in units of H (horizontal scanning period). In the embodiment, since writing / reading in the memory is performed in units of several tens of sample data, it is possible to suppress the delay of about several tens to hundreds of tens of sample data,
It is possible to reduce the scale of the control circuit by simplifying the signal processing system.

FIG. 6 is a block diagram showing a specific example of the transmission circuits 6 and 7 in FIG. 1, in which 21 is an input terminal of a digital video signal, 22 is an output terminal of a digital video signal subjected to transmission processing, and 23 is. Adder circuit, 24 is subtraction circuit, 2
Reference numeral 5 is a delay circuit, and 26, 27 and 35 are coefficient multipliers.

In the figure, the digital video signal input from the input terminal 21 is subjected to a predetermined coefficient k3 by the coefficient unit 35.
After being multiplied by
Is added to the output signal and is supplied to the subtraction circuit 24. The output signal of the adder 23 is delayed by one sample data by the delay circuit 25, weighted by the predetermined coefficient k1 by the coefficient unit 26 and supplied to the adder 23, and the predetermined coefficient k2 by the coefficient unit 27. Are weighted according to the above and are supplied to the subtraction circuit 24. The subtractor 24 subtracts the output signal of the coefficient unit 27 from the output signal of the adder 23.

Transfer function G (z) of the transmission circuit having such a configuration
Is represented by the equation shown in FIG. Such transfer function G
In (z), for example, k1 = 0.3, k2 = 0.
By setting 5 and k3 = 1.4, a high-frequency emphasis characteristic suitable for pre-emphasis can be realized.

The transmission circuits 6 and 7 are formed by the cyclic digital filter having the originally non-linear phase characteristic as described above.
As described above, the linear phase characteristic in which the pre-shot and the post-shot are symmetrically added can be realized by using the time axis reversal processing as described above.

In this embodiment, the linear phase characteristic as described above can be realized even if a transmission circuit having an arbitrary configuration such as a cyclic type or a non-cyclic type other than the specific example shown in FIG. 6 is used. it can. Therefore, the circuit scale can be reduced and the cost can be reduced by realizing the transmission circuit with the configuration of the recursive digital filter that can realize a desired amplitude characteristic with a relatively small-scale circuit.

FIG. 8 is a block diagram showing another embodiment of the video signal processing apparatus according to the present invention, in which 28 is a time axis reverse synthesizing circuit 28, and the portions corresponding to those in FIG. A duplicate description will be omitted.

In the figure, the time axis reversal synthesizing circuit 28 selects the output signals of the transmission circuits 6 and 7 to invert the time axis, and the time axis inversion circuit 8 in the embodiment shown in FIG.
9 and switching circuit 11 are provided instead of
Other parts are similar to those of the embodiment shown in FIG. That is, in FIG. 1, the switching circuit 11 avoids the signal discontinuity and the transient caused by the time-axis inversion processing and synthesis of the video signal returned to the original time axis by the time-axis inversion circuits 8 and 9. It was a composite of a series of video signals,
In this embodiment shown in FIG. 7, the time axis reversal synthesizing circuit 28 avoids signal discontinuities and transients caused by the processing of the time axis inversion circuits 4 and 5 and the transmission circuits 6 and 7, and selectively selects only effective portions. The time axis reverse processing is performed and output.

The operation of this embodiment will be described in detail below with reference to the waveform diagrams of FIGS. 2, 3 and 4. The input video signal from the input terminal 1 is processed by the time axis inversion circuit 4 and the time axis inversion circuit 5, respectively, as described above, and further processed by the transmission circuit 6 and the transmission circuit 7. It The process up to this point is exactly the same as that of the embodiment shown in FIG. 1, and the signal of the waveform shown in FIG. Further, the transmission circuit 7 outputs signals of the same waveform shown in FIG. The output signals of these transmission circuits 6 and 7 are both supplied to the time axis inversion synthesis circuit 28.

In the time axis inversion synthesis circuit 28, the transmission circuit 6
2 (c), the output signal of
c3, c4, ... Periods are selected and time axis inversion processing is performed respectively, and the output signal of the transmission circuit 7 is d1, d2, d3 ,. Then, the time axis reverse processing is performed. Such processing is performed using a memory provided inside the time-axis reverse synthesis circuit 28, and when reading out from this memory in the reverse order, these periods c2, c3, c4, ..., And period d1, d2, d3. ,
... These are combined by alternately reading out the periods. That is, c2, c3, c4, ... In FIG.
The periods are a1, a2, a3, ... Periods, and the periods d1, d2, d3, ... In FIG. 3 (c) are b1, b2, b3 ,.
.., the output signal of the time axis inversion combining circuit 28 becomes as shown in FIG.

The output signal of the time-axis reversal synthesizing circuit 28 is supplied to the transmission circuit 11, and as in the embodiment shown in FIG. 1, the post-shoot is added by emphasizing the high frequency component, and the result is shown in FIG. Pre-shoot and post-shu as shown
A video signal with symmetrically added video is obtained.

FIG. 9 is a time axis inversion synthesis circuit 2 in FIG.
8 is a block diagram showing a specific example of No. 8 of FIG.
b, 28c are input terminals, 28d are output terminals, 28e, 2
8f is a memory, 28g is a switching circuit, and 28i is an inverting circuit.

In the figure, the control signal TRS input from the input terminal 28c is a half of the time width t of the section set for the time axis inversion processing in the time axis inversion circuits 4 and 5 in FIG. That is, "L" and "H" at every time t / 2
And the level shall be reversed. For example, as shown in the previous embodiment, assuming that the time width t is the time corresponding to 32 sample data of the digital video signal, "L" and "H" are set every 16 (= 32/2) sample data. And the level is reversed. Here, the time axis reversing circuits 4 and 5 have the configuration shown in FIG. 5, and the control signal TRS input from the input terminal 15 thereof has the timing relationship shown in FIGS. 10A and 10B, respectively. Then, in contrast, the control signal TRS input from the input terminal 28c of FIG. 9 has the timing shown in FIG. 10 (c).

When the control signal TRS is "H", the control signal TRS causes the switching circuit 28g to close to the c side.
Further, the memory 28e is set to the write operation mode and the memory 28e
f is set to the read operation mode, respectively. Input terminal 28
The signal input from a is supplied to the memory 28e, and its sample data is sequentially written into a predetermined address of the memory 28e. During this time, the sample data is sequentially read from the memory 28f in the reverse order of the writing, and is output from the output terminal 28d via the switching circuit 28g.
Note that during this period, the signal input from the input terminal 28b is supplied to the memory 28f, but is not written.

Next, when the time for 16 sample data has elapsed, the control signal TRS is level-inverted to "L", the switching circuit 28g is closed to the d side, the memory 28e is in the read operation mode, and the memory 28f is in the write operation. It is set to each mode. The signal input from the input terminal 28b is stored in the memory 28
f and the sample data is sequentially stored in the memory 28f.
Is written to a predetermined address of. During this time, the memory 28
From e, 16 sample data written when the control signal TRS is "H" is read out in the reverse order of the writing order, and is output through the switching circuit 28g to the output terminal 28d. Is output from. During this period, input terminal 2
The signal input from 8c is supplied to the memory 28e, but is not written.

Next, after the "L" period of the control signal TR continues for 16 sample data, when the control signal TRS becomes "H" again, the switching circuit 28g is closed to the c side and the memory 28e performs the write operation. Mode, the memory 28f is set to the read operation mode. Then, as described above, the signal input from the input terminal 28a is supplied to the memory 28e, and its sample data is sequentially written. Also,
The 16 sample data written when the control signal TRS was "L" is read from the memory 28f in the reverse order of the write order, and is output via the switching circuit 28g. It is output from 28d.

As described above, the control signal TRS of "L",
By "H", from the output signals of the transmission circuits 6 and 7, avoiding the discontinuous portions and transients of the signals, select only the effective portion, and write them in the memories 28e and 28f alternately and alternately while performing the time axis reverse processing. Read out, switching circuit 2
Synthesized by 8 g. In this case, it is possible to make a section which is a processing unit in the time axis reversal synthesizing circuit 28, the time axis reversal circuits 4, 5, and the transmission circuits 6, 7 a short section less than 1H (horizontal scanning period). The same effect as the embodiment can be obtained.

When a signal delay is caused by the processing in the transmission circuits 6 and 7, only the time corresponding to this processing delay,
The control signal TRS supplied to the time axis reverse rotation synthesizing circuit 28 may be delayed from the timing shown in FIG.

In the embodiment shown in FIG. 1, an unnecessary signal portion which is not selected by the switching circuit 10 including a discontinuous portion or a transient portion of the signal is also included in the time axis reversing circuit 8.
9, the time axis reversal processing was performed. In this embodiment shown in FIG. 8, only the effective signal components are written in advance in the memories 28e and 28f in FIG. 9 while avoiding these unnecessary portions, and the time axis inversion processing is performed. The required memory capacity can be further reduced as compared with the embodiment. That is, in the embodiment shown in FIG. 1, as described with reference to FIG. 5, four time axis reversing circuits having two memories each having a capacity of 32 sample data are required, and a total of 256 (= 32 × 2). X4) Although the memory capacity for the sample data is required, in the embodiment shown in FIG.
Since the above time axis reversing circuit has two memories and the memory having two memories having the capacity of 16 sample data shown in FIG.
A memory capacity of (= 32 × 2 × 2 + 16 × 2) sample data is sufficient, and the circuit scale and cost can be further reduced as compared with the embodiment shown in FIG.

The operation of the embodiment shown in FIG. 9 and FIG.
As is clear from the timing relationship between the control signals TR and TRS at 0, in FIG. 9, only the first half signal of each section output from the time axis reversal circuit 4 is written in the memory 28e, and the memory 28f is written in the memory 28f. Is the time axis inversion circuit 5
Only the first half signal of each section output from is written. From this, the time axis reversing circuits 4 and 5 may be provided with a memory having a capacity of ½ of the time width of each section set, and in this case, the entire memory capacity becomes smaller, The memory capacity is 64 (= 16 × 4) sample data.

By the way, in each of the above-described embodiments, the signal processing is performed twice, that is, the input signal is inverted in the time axis and processed by the transmission circuits 6 and 7, and the time axis is inverted again and processed by the transmission circuit 11. It was a thing. According to this, at least the first time axis reversal processing is not affected by the increase in amplitude due to the first signal processing. That is, in general, in signal processing by a transmission circuit, an overshoot and an undershoot are added depending on the processing content, so that the signal processing is performed after the signal processing in comparison with the input signal. The amplitude of the signal becomes larger. Therefore, when such signal processing is realized by a digital circuit, it is necessary to increase the number of signal processing bits in response to an increase in the dynamic range after signal processing. For example, if the input signal is 8 bits and an overshoot or undershoot is added by signal processing by the transmission circuit, the output signal of this transmission circuit becomes a 9-bit signal. Can be considered. A memory corresponding to the number of signal processing bits is required to reverse-process such a signal on the time axis, which increases the memory capacity.

In the embodiment shown in FIGS. 1 and 7, the signal input from the input terminal 1 is inverted by the time axis inversion circuits 4 and 5 before the number of bits is increased by the signal processing by the transmission circuit. Since the processing is performed, it is not necessary to consider the increase in the number of bits in the memory capacity of the time axis inversion circuits 4 and 5, and the time axis inversion circuits 8 and 9 and the time axis inversion synthesis circuit 28 are transmitted. Since they are arranged between the circuits 6 and 7 and the transmission circuit 11, the capacities of these memories need only take into account the increase in the number of bits in the transmission circuits 6 and 7, and therefore the memory due to the increase in the number of signal processing bits The increase in capacity can be minimized and the increase in circuit scale can be prevented.

In each of the above-mentioned embodiments, the input signal is inverted in the time axis to perform the first signal processing, and the original signal is returned to the original time axis to perform the second signal processing. The first signal processing may be performed on the input signal as it is, and then the time axis may be reversed to perform the second signal processing, and then the original time axis may be restored. In this case, in FIG. 1, the transmission circuit 11 may be arranged between the input terminal 1 and the time axis reversing circuits 4 and 5 so that the output signal of the switching circuit 10 is directly output from the output terminal 12. .. Also in FIG. 8, similarly, the transmission circuit 11 is connected to the input terminal 1 and the time axis reversing circuits 4, 5 in the same manner.
The output signal of the time axis reversal synthesizing circuit 28 may be directly output from the output terminal 12. That is, in any case, the signal input from the input terminal 1 is supplied to the transmission circuit 11 and subjected to predetermined signal processing,
Then, it is supplied to the time axis reversing circuit 4 and the time axis reversing circuit 5. The subsequent processing is the same as that of the embodiment shown in FIGS.

Further, in these cases, there is no effect of reducing the influence of the increase in the amplitude due to the signal processing by the transmission circuit, but in the case where this embodiment emphasizes the high frequency component of the signal such as pre-emphasis. Since the output signal of the switching circuit 10 or the time axis reversal synthesizing circuit 28 is not processed by the transmission circuit, a slight signal discontinuity that may occur in these signals does not increase, and the signal processing thereafter is performed. There is a side effect of stabilizing the operation.

FIG. 11 is a block diagram showing still another embodiment of the video signal processing apparatus according to the present invention, which is a pre-emphasis circuit using the embodiment shown in FIG. 1 or FIG. An input terminal, 30 is an output terminal of a video signal, 31 is a high-pass filter realized by the embodiment shown in FIG. 1 or 8, 32 is a coefficient unit, 33 is a delay circuit,
Reference numeral 34 is an adder circuit.

In the figure, the video signal input from the input terminal 29 is supplied to the delay circuit 33 and the high pass filter 31. The high-pass filter 31 has the configuration shown in FIG. 1 or 7, and the transmission circuits 6, 7,
11 is a high-pass filter. This can be realized, for example, by setting the coefficient value k2 of the coefficient unit 27 to 1 and the coefficient value k3 of the coefficient unit 35 to 1 in FIG. 6 constituting the cyclic digital filter. The high frequency component of the input video signal extracted by the high-pass filter 31 is processed by the coefficient unit 32 to a predetermined coefficient, for example, 0.4.
Is multiplied and supplied to the adder circuit 34. In the adder circuit 34, the output signal of the coefficient unit 32 is added to the video signal delayed by the delay circuit 33 by the time corresponding to the signal delay by the high-pass filter 31 and the coefficient unit 32, and the added signal is output from the output terminal 30. To be done.

The high-pass filter 31 is shown in FIG.
Since the pre-shoot and the post-shoot are generated symmetrically, the pre-shoot and the post-shoot are symmetrically added from the output terminal 30 and pre-emphasized. A video signal is obtained.
By using the pre-emphasis circuit having the linear phase characteristic in which the pre-shot and the post-shot are added symmetrically, it is possible to suppress the increase in the amplitude even with the same emphasis amount. When the amplitude or peak value is the same, pre-shoot and post-shot are added symmetrically, so pre-emphasis can be applied more strongly, and the effect of noise generated during recording / reproduction or transmission is affected. The effect that can reduce more. Furthermore, the distortion that occurs when the pre-emphasis and the de-emphasis are mismatched becomes bilaterally symmetric on the screen and is visually inconspicuous, so that the image quality deterioration can be reduced.

It is also possible to obtain a de-emphasis circuit having a configuration substantially similar to that shown in FIG. That is,
In FIG. 11, a subtracting circuit may be used instead of the adding circuit 34, and the output signal of the coefficient unit 32 may be subtracted from the video signal from the delay circuit 33. Therefore, the pre-emphasis circuit and the de-emphasis circuit can be realized with substantially the same circuit configuration, and the common parts of both can be shared, and the effect of reducing the cost of the device can be obtained.

Further, by configuring the high-pass filter 31 as shown in FIG. 1 or 7, it is possible to reduce the delay time due to the signal processing in the high-pass filter 31. As a result, the delay time of the delay circuit 33 can be reduced, and the circuit scale can be reduced and the cost can be reduced.

In the embodiment shown in FIG. 11, the coefficient unit 32 is a linear circuit whose output signal is determined by a linear operation with respect to the input signal. However, this may be replaced with a circuit having a nonlinear input / output characteristic. Good. For example, a limiter circuit that limits the output signal so that it does not exceed a certain amplitude value can be used. In this case, the amount of emphasis is large when the amplitude of the input signal is small, and the amount of emphasis is small when the amplitude of the input is large. Such a dynamic pre-emphasis circuit can be realized. By doing so, pre-emphasis can be effectively applied without greatly increasing the amplitude of the recording signal or the transmission signal, and the influence of noise generated during the recording / reproduction or transmission process can be significantly reduced.

On the other hand, the de-emphasis circuit has the same configuration as that of FIG. 11, but may be configured to subtract the output signal of the coefficient unit having the non-linear characteristic equal to the pre-emphasis from the video signal from the delay circuit 33. ..

As a result, the common part of the pre-emphasis circuit and the de-emphasis circuit can be shared, resulting in low loss, and the delay time of the delay circuit 33 can be shortened to reduce the circuit scale. In this case, the de-emphasis circuit characteristic is not always completely opposite to the pre-emphasis circuit characteristic by using the non-linear characteristic, and a partial mismatch occurs. Distortion becomes symmetric on the screen and becomes visually inconspicuous, so that image quality deterioration can be reduced.

FIG. 12 is a block diagram showing still another embodiment of the video signal processing device according to the present invention, which is a 36 adder circuit, and the portions corresponding to those in FIG. Omit it.

In each of the embodiments described above, the first transmission circuit for processing the input signal whose time axis has been inverted and the second transmission circuit for processing the signal which has been processed by this first transmission circuit and whose time axis has been inverted again. By connecting the transmission circuit in cascade, a circuit having a linear phase characteristic was realized so that the pre-shot and the post-shot are symmetrically added to the video signal.
In this embodiment shown in (1), the first and second transmission circuits are connected in parallel.

In FIG. 12, the video signal input from the input terminal 1 has its time axis reversed by the time axis inversion circuits 4 and 5, and is transmitted by the transmission circuits 6 and 7, and then transmitted to the time axis inversion synthesis circuit 28. Supplied, time axis inversion circuit 4,
5, the discontinuity and transient of the signal generated by the transmission circuit 5 and the transmission circuits 6 and 7 are avoided, and only the effective part is selectively time-axis-reversed and returned to the original time-axis for output. Such operation is similar to that of the embodiment shown in FIG.

On the other hand, the video signal input from the input terminal 1 is also delayed by the delay circuit 36 by the time axis inversion circuits 4 and 5.
Then, the signal is delayed by a time corresponding to the processing time in the time axis inversion synthesizing circuit 28, is supplied to the transmission circuit 11, and is transmitted as it is. The original time axis signal output from the time axis reversal synthesis circuit 28 and the output signal of the transmission circuit 11 are added by the adder circuit 37 and output from the output terminal 12.

As described with reference to FIG. 8, a preshoot is added to the output signal of the time-axis reverse synthesizing circuit 28,
A post shoot is added to the output signal of the transmission circuit 11. Therefore, by adding these output signals by the adder circuit 37, the video signal to which the preshoot and the postshoot are symmetrically added can be obtained from the output terminal 12.

In the embodiment shown in FIGS. 1 and 8, the first transmission circuit for processing the video signal whose time axis is reversed and the second transmission circuit for processing the video signal which has been returned to the original time axis. Since and are connected in cascade, the input video signal is
Signal processing is performed twice by the second transmission circuit. On the other hand, in the embodiment shown in FIG. 12, the input video signal is
The second transmission circuit 11 and the second transmission circuit 11 perform parallel processing, which allows input from the input terminal 1 and output terminal 1
The delay time due to the signal processing required for the output from 2 is reduced as compared with the embodiment shown in FIGS. 1 and 8, and the effect of reducing the scale of the control circuit by the simplification of the signal processing system can be obtained.

Further, in the embodiment shown in FIG. 12, unlike the embodiment shown in FIGS. 1 and 7, the time axis reverse synthesizing circuit 2 is different.
The output signal 8 is output from the output terminal 12 via the adder circuit 37 without being subjected to the second transmission processing. Therefore, when a high frequency component of a signal such as pre-emphasis is emphasized, a slight signal discontinuity that may occur in the time axis reversal synthesis circuit 28 is increased by the high frequency emphasis processing by the second transmission circuit. In this case, the effect of stabilizing the subsequent signal processing operation can be obtained.

Further, similarly to the embodiment shown in FIGS. 1 and 8, since the linear phase characteristic in which the preshoot and the postshoot are symmetrically added can be realized, the embodiment shown in FIG. When used as an emphasis circuit, even if the amount of emphasis is the same, the increase in amplitude is suppressed, the amount of emphasis at the same amplitude or peak value is increased, and noise is reduced, and pre-emphasis and de-emphasis occur. It is possible to obtain excellent effects such as reduction in image quality deterioration due to the mismatching of.

Although each of the above embodiments is applied to the pre-emphasis circuit, the present invention is not limited to this.
By using an arbitrary transmission circuit, it can be applied to a de-emphasis circuit, a transmission line characteristic compensation circuit, a noise removal circuit, or the like.

Further, although each of the above embodiments is constructed by using the signal processing blocks of two systems, the signal processing blocks of more than two N systems may be used. In this case, N
In the signal processing block of the system, the input signals are divided and processed at intervals of different timings, and the effective components of the output signals of these signal processing blocks are combined with each other. By doing so, even when the impulse responses of the first and second transmission circuits converge slowly, it is possible to reduce the signal delay due to the processing of the circuits.

By the way, in each of the embodiments described above, the signal in the redundant period such as the horizontal blanking included in the video signal is simultaneously processed. However, only the effective period of the video signal excluding such a redundant period may be expanded or compressed on the time axis and a predetermined synchronization signal may be applied to perform the same process. FIG. 13 shows an example of such a video signal.

That is, in FIG. 13, this video signal is formed by time-division-multiplexing the color signal C and the bright signal Y in each horizontal period, or the time axis reference is performed by the reproduction signal processing in the period ts immediately before the color signal C. A negative sync signal and a burst signal are added, and a guard period tg provided to prevent interference between the color signal C and the luminance signal Y is added. The color signal C
The luminance signal Y and the luminance signal Y are time-axis converted according to their respective maximum frequencies in an effective period excluding a redundant period such as horizontal blanking. For example, the maximum frequency of the color signal C is 7M
When the maximum frequency of Hz and the luminance signal Y is 21 MHz, the ratio of the multiplexing period of the color signal C and the luminance signal Y is 1: 3.
Each is time-axis converted and multiplexed so that (= 7: 21).

When such a video signal is subjected to pre-emphasis or de-emphasis processing by the video signal processing apparatus shown in the previous embodiment, the color signal C and the luminance signal Y which are adjacent to each other across the guard period tg. Occurs due to the pre-shot and post-shut caused by the emphasis processing. Therefore, the gart period tg may be widened to a range where such interference does not occur, but the redundant period increases and the recording density decreases.

For example, assuming that the impulse response of the emphasis circuit of the linear phase characteristic realized by the present invention has 12 samples including pre-shoot and post-shoot, if the guard period tg is 12 samples or more, Good. In addition, at this time, in the period corresponding to the guard period tg, 6 samples of data corresponding to the blanking of the color signal and 6 samples of data corresponding to the blanking of the luminance signal are output for a time period. Axial multiplexing may be performed, and after processing by the emphasis circuit of the present invention, predetermined data may be exchanged. Also,
Even when the guard period tg is shorter than 12 samples, t
By performing time-axis multiplexing so that the data corresponding to the blanking of the color signal and the data corresponding to the blanking of the luminance signal are output in the period corresponding to the period g, the influence of the transient can be reduced. Even if such interference exists, it is possible to reproduce a video signal without distortion by performing de-emphasis processing while receiving interference (in a state of time axis multiplexing) in reproduction signal processing. When the color signal C and the luminance signal Y are divided and each of them is subjected to de-emphasis processing independently, distortion remains.

Therefore, in the case where processing such as pre-emphasis or de-emphasis according to the above-described embodiment is performed on the video signal in which the redundancy period such as horizontal blanking is reduced, the transmission having the configuration shown in FIG. 6 is performed. Circuit 6,
The output signals of the delay circuits 25 in 7 and 11 are given predetermined data.
However, the influence from the adjacent sample data may be removed.

FIG. 14 is a block diagram showing a specific example of the transmission circuits 6, 7 and 11 having such a function.
8 is a switching circuit 39, 40 is a data generating circuit,
The same reference numerals are given to the portions corresponding to, and redundant description will be omitted.

In FIG. 14, this concrete example is the same as the concrete example shown in FIG. 6 with a switching circuit 38 and data generating circuits 39, 40.
Is added. The switching circuit 38 has the output signal of the adder circuit 23 on the a side, the data CA from the data generation circuit 39 on the b side, and the data Y from the data generation circuit 40 on the C side.
A is supplied respectively, and the side a is usually selected. The operation of the transmission circuit in this case is exactly the same as that of the transmission circuit shown in FIG. Here, the data generation circuit 39 outputs a data value CA equal to the value of the output signal of the delay circuit 25 when the level (achromatic level) representing the achromatic color of the color signal is continuously input. Further, the data generation circuit 40 has a data value Y equal to the value of the output signal of the delay circuit 25 when the level (0 level) representing black of the color signal is continuously input.
Output B respectively.

Next, the switching operation timing of the switching circuit 38 will be described. When the circuit shown in FIG. 14 is applied to the transmission circuits 6 and 7 in the above-described embodiment and the video signal shown in FIG. 13 is used as the input video signal, the color signal C whose time axis is reversed is generated. When the first sample data of valid data (which corresponds to the last sample data in the original color signal C on the time axis) is input from the input terminal 21, the switching circuit 38 is closed to the b side and delayed. Data CA is supplied to the circuit 25 from the data generating circuit 37. By this operation, regardless of the value of this actual sample data, the same output signal as when the achromatic level is continuously input before the first sample data of the valid data of the color signal C is obtained. Obtainable. Further, the first sample data of the valid data of the luminance signal Y whose time axis is reversed (this also corresponds to the last sample data in the original luminance signal Y of the time axis) is input from the input terminal 21. When
The switching circuit 38 is closed on the c side, and the data YB is supplied from the data generating circuit 40 to the delay circuit 25. By this operation, an output signal similar to that when the black level is continuously input is obtained before the first sample data of the effective data of the luminance signal Y, irrespective of the value of this actual sample data. Therefore, mutual interference between the color signal C and the luminance signal Y can be prevented.

When the circuit shown in FIG. 14 is applied to the transmission circuit 11 in the above-described embodiment, the input terminal 21
The video signal input to is converted to the original time axis,
When the first sample data of the valid data of the color signal C is input from the input terminal 21, the switching circuit 38 is closed to the side b, the data CA is supplied to the delay circuit 25, and the luminance signal Y is also supplied. When the first sample data of the valid data is input from the input terminal 21, the switching circuit 38 is closed to the c side and the delay circuit 25 is supplied with the data YB.
An output signal equivalent to that when the achromatic color level or the black level is input to the data before each effective sample data is obtained, and the color signal C and the luminance signal Y are added without adding a new redundant period. Mutual interference can be prevented.

Further, by performing the de-emphasis processing in the same manner, the signal processing can be performed while the color signal C and the luminance signal Y are time-multiplexed. Furthermore, the color signal C
Since there is no mutual interference between the luminance signal Y and the luminance signal Y, the color signal C and the luminance signal Y may be separated and de-emphasis processed independently, which has the effect of increasing the flexibility of the configuration of the reproduction signal processing device.

In the above description, the transmission circuits 6, 7,
Although all 11 are configured as shown in FIG. 14, the transmission circuits 6 and 7 may be configured as shown in FIG. 6 and only the transmission circuit 11 may be configured as shown in FIG. The transmission circuit 11 may have the configuration shown in FIG. 6, and the transmission circuits 6 and 7 may have the configuration shown in FIG.

Further, the transmission circuits 6, 7, 11 may be provided with only one of the data generation circuits 39, 40. For example, the transmission circuits 6, 7 are provided with the data generation circuit 3.
It is possible to prevent the data interference of the rear part of the effective area of the color signal C by 9 and prevent the first data interference of the luminance signal Y by the data generation circuit 40 in the transmission circuit 11.

[0082]

As described above, according to the present invention,
The same video signal is divided into predetermined sections and time axis reverse processing is performed.
Two signal processing blocks having a function of reversing the time axis perform predetermined signal processing by transmission circuits having predetermined characteristics, and the predetermined sections in the respective signal processing blocks are mutually shifted in time. , The time axis reversal processing, the division into the sections performed in the time axis re-reversal processing, the signal discontinuity caused by the synthesis, or the discontinuity caused by the signal processing of the transmission circuit, the signal processing of two systems Even if the section which is excluded when selecting and synthesizing the output signal of the block and is divided during the time axis inversion processing is less than 1H (horizontal scanning period), discontinuity of the signal or transient It is possible to obtain a video signal that has no influence.

Further, according to the present invention, the number of time axis inversion circuits is increased because two signal processing blocks are required as compared with the prior art, but the interval is sufficiently shorter than 1H. Therefore, the memory capacity required for the time axis inversion circuit can be reduced to, for example, about several tenths of the prior art, and therefore the memory capacity of the entire device can be significantly reduced. As a result, the circuit scale and cost can be reduced.

Furthermore, according to the present invention, the signal delay associated with the time axis inversion processing is H (horizontal scanning period) in the prior art.
Since writing and reading in the memory are performed in units, a delay of several H occurs, whereas writing and reading in the memory can be performed in units of several tens of sample data, and for example, several tens to several hundreds. The signal delay can be suppressed to a very small value of about 10 sample data, and the scale of the control circuit can be reduced by simplifying the signal processing system.

Furthermore, according to the present invention, it is possible to construct a video signal processing device having a linear phase characteristic by using a transmission circuit having an arbitrary configuration such as a cyclic type or a non-cyclic type. Therefore, by making the transmission circuit a cyclic digital filter capable of realizing a desired amplitude characteristic with a relatively small-scale circuit, the circuit scale can be reduced and the cost can be reduced.

Furthermore, according to the present invention, the increase in the memory capacity due to the increase in the number of signal processing bits is minimized by performing the time-axis reverse processing before the input signal is transmitted and the number of bits increases. Can be
It is possible to prevent an increase in circuit scale.

Furthermore, according to the present invention,
By using it as an emphasis circuit with a linear phase characteristic in which a to-post shot is added symmetrically, it is possible to increase the amplitude even with the same emphasis amount.
At the same amplitude or crest value, pre-shoot and post-shot are added symmetrically, so that more emphasis can be applied and the effect of noise generated during recording / reproduction or transmission can be further reduced. it can. Furthermore, the distortion that occurs when the pre-emphasis and the de-emphasis are mismatched becomes bilaterally symmetric on the screen and becomes visually inconspicuous, so that the image quality deterioration can be reduced.

Furthermore, according to the present invention, by introducing a coefficient unit having a non-linear input / output characteristic, the emphasis amount becomes large when the amplitude of the input signal is small, and the emphasis amount becomes large when the amplitude of the input is large. It is possible to realize a dynamic emphasis circuit that is reduced in number. By doing this, it is possible to effectively apply emphasis without significantly increasing the amplitude of the recording signal or the transmission signal,
It is possible to reduce the influence of noise generated during recording / reproduction or transmission. Furthermore, if the nonlinear characteristic is applied to such a dynamic emphasis circuit, the de-emphasis circuit does not always have the perfect inverse characteristic of the pre-emphasis circuit,
Although there is a partial mismatch, the distortion that occurs when the mismatch occurs is bilaterally symmetric on the screen and is visually inconspicuous, so that deterioration in image quality can be reduced.

Furthermore, according to the present invention, for a video signal in which a redundancy period such as horizontal blanking is reduced,
By allowing the output signal of the delay circuit in the transmission circuit to be set to a predetermined data value and removing the influence from the adjacent sample data, the data before the effective sample data is achromatic level. Alternatively, an output equal to that when the black level is input is obtained, and mutual interference between the color signal and the luminance signal can be prevented without adding a new redundant period. By performing the de-emphasis processing of the reproduction signal processing in the same manner, the signal processing can be performed while the color signal and the luminance signal are time-axis multiplexed. Furthermore, since mutual interference between the color signal and the luminance signal does not occur, the color signal and the luminance signal may be separated and each may be de-emphasized independently, which has the effect of increasing the flexibility of the configuration of the reproduction signal processing device. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal processing device according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the first signal processing block in FIG.

FIG. 3 is a waveform diagram for explaining the operation of the second signal processing block in FIG.

4 is a waveform diagram showing an output signal of the switching circuit in FIG. 1 and an output signal at an output terminal.

5 is a block diagram showing a specific example of the time axis reversing circuit in FIG. 1. FIG.

6 is a block diagram showing a specific example of the transmission circuit in FIG.

7 is a diagram showing a transfer function of the transmission circuit shown in FIG.

FIG. 8 is a block diagram showing another embodiment of the video signal processing device according to the present invention.

9 is a block diagram showing a specific example of the time axis inversion synthesis circuit in FIG.

FIG. 10 is a waveform diagram explaining the operation of the embodiment shown in FIG.

FIG. 11 is a block diagram showing still another embodiment of the video signal processing device according to the present invention.

FIG. 12 is a block diagram showing still another embodiment of the video signal processing device according to the present invention.

FIG. 13 is a waveform diagram showing an example of an input video signal in each embodiment of the present invention.

FIG. 14 is a block diagram showing another specific example of the transmission circuit in each embodiment of the present invention.

[Explanation of symbols]

 1 Video signal input terminal 2,3 Signal processing block 4,5 Time axis reversing circuit 6,7 Transmission circuit 8,9 Time axis reversing circuit 10 Switching circuit 11 Transmission circuit 12 Video signal output terminal 15 Control signal input terminal 16 Switching circuit 17, 18 Memory 19 Switching circuit 28 Time axis reverse synthesizing circuit 28c Control signal input terminal 28e, 28f Memory 28g Switching circuit 31 High-pass filter 32 Coefficient unit 33 Delay circuit 34 Adder circuit 36 Delay circuit 37 Adder circuit

Claims (13)

[Claims] 1. A first signal processing means for sequentially dividing an input video signal into first sections having a predetermined time width, and processing the signal for each of the first sections; and the input video signal for the first section. And a second signal processing means for sequentially performing signal processing in each of the second sections by sequentially dividing into second sections having the same time width and different timings, and the output signal of the first signal processing means. A signal in a part of each first section and a signal in a part of each second section of the output signals of the second signal processing means are combined to form a continuous video signal. And a third signal processing means for processing the output video signal of the synthesizing means, the video signal processing device. 2. The first signal processing means according to claim 1, wherein the input video signal is sequentially divided into the first sections, and the time axis of the signal is reversed for each of the first sections. The time axis reversing means, the first signal converting means having the transfer function G for converting the frequency characteristic of the output signal of the first time axis reversing means into a predetermined characteristic, and the output of the first signal converting means. A second time axis reversing means for reversing the time axis of the signal for each of the first sections to restore the video signal of the original time axis, wherein the second signal processing means includes the input video signal Third time axis reversing means for sequentially dividing the time axis of the signal into second sections, and frequency characteristics of the output signal of the third time axis reversing means for the first section. Second signal converter having a transfer function G for converting to the same predetermined characteristic as by the signal converter of And a fourth time axis reversing means for reversing the output signal of the second signal converting means by the time axis for each of the second sections to restore the original time axis video signal. Video signal processing device. 3. The video signal processing device according to claim 1, wherein the time widths of the first and second sections are shorter than one horizontal scanning period of the video signal. 4. The third signal processing means according to claim 1, further comprising a third signal conversion means having a transfer function G for converting a frequency characteristic of the output video signal of the synthesizing means into a predetermined characteristic. Characteristic video signal processing device. 5. A first signal processing means for sequentially dividing an input video signal into first sections having a predetermined time width and performing signal processing for each of the first sections; and the input video signal for the first section. A second signal processing means for sequentially performing signal processing for each of the second intervals by sequentially dividing the second interval into a second interval having the same time axis and different timing, and an output signal of the first signal processing means A signal of a part of the period of each of the first sections and a signal of a part of the period of each of the second sections of the output signals of the second signal processing means are combined to form a continuous video signal. And a third signal processing means for processing the input video signal, and an adding means for adding the output video signal of the combining means and the output video signal of the third signal processing means. A video signal processing device characterized by the above. 6. The first signal processing means according to claim 5, wherein the first signal processing unit sequentially divides the input video signal into the first sections, and reverses the time axis of the signal for each of the first sections. The time axis reversing means, the first signal converting means having the transfer function G for converting the frequency characteristic of the output signal of the first time axis reversing means into a predetermined characteristic, and the output of the first signal converting means. A second time axis reversing means for reversing the signal on a time axis basis for each of the first sections and returning to a video signal of the original time axis. Third time axis reversing means for sequentially dividing the time axis of the signal into second sections, and frequency characteristics of the output signal of the third time axis reversing means for the first section Second signal converter having a transfer function G for converting to the same predetermined characteristic as by the signal converter of And a fourth time axis reversing means for reversing the output signal of the second signal converting means by the time axis for each of the second sections and returning the video signal to the original time axis video signal. Video signal processing device. 7. The video signal processing device according to claim 5, wherein the time widths of the first and second sections are shorter than one horizontal scanning period of the video signal. 8. The signal processing unit according to claim 5, wherein the third signal processing unit delays the input video signal by a predetermined time and a frequency characteristic of an output signal of the signal delaying unit is converted into a predetermined characteristic. And a third signal converting means having a transfer function G for controlling the video signal processing device. 9. A first signal processing means for sequentially dividing an input video signal into a first section having a predetermined time width and performing signal processing for each of the first sections, and the input video signal for the first section. And a second signal processing means for sequentially performing signal processing in each of the second sections by sequentially dividing into second sections having the same time width and different timings, and the output signal of the first signal processing means. A signal in a part of each first section and a signal in a part of each second section of the output signals of the second signal processing means are combined to form a continuous video signal. Synthesizing means, a third signal processing means for processing the output video signal of the synthesizing means, a signal delay means for delaying the input video signal for a predetermined time, an output video signal of the signal delay means and the third 3 is provided with an arithmetic means for arithmetically processing the output video signal output from the signal processing means. A video signal processing apparatus according to. 10. The first signal processing unit according to claim 9, wherein the input video signal is sequentially divided into the first section, and the time axis of the signal is reversed for each of the first sections. The time axis reversing means, the first signal converting means having the transfer function G for converting the frequency characteristic of the output signal of the first time axis reversing means into a predetermined characteristic, and the output of the first signal converting means. A second time axis reversing means for reversing the signal on a time axis basis for each of the first sections and returning to a video signal of the original time axis. Third time axis reversing means for sequentially dividing the time axis of the signal into second sections, and frequency characteristics of the output signal of the third time axis reversing means for the first section Second signal conversion having a transfer function G for converting to the same predetermined characteristic as by the signal conversion means of Means, and fourth time axis reversing means for reversing the output signal of the second signal converting means on a time axis basis for each of the second sections to restore the original time axis video signal. Video signal processing device. 11. The video signal processing device according to claim 9, wherein the time widths of the first and second sections are shorter than one horizontal scanning period of the video signal. 12. The third signal processing means according to claim 9, further comprising a third signal conversion means having a transfer function G for converting the frequency characteristic of the output video signal of the synthesizing means into a predetermined characteristic. A video signal processing device characterized by: 13. The third signal converting means according to claim 9, wherein the third signal processing means has a transfer function G for converting the frequency characteristic of the output video signal of the synthesizing means into a predetermined characteristic. A video signal processing device, comprising: a non-linear conversion means for limiting an output video signal of the third signal conversion means to a predetermined amplitude.