JP2551113B2 - Noise reduction device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit for reducing noise in a noisy video signal such as a home VTR.

[Prior Art] A home VTR does not need to faithfully record and reproduce a television signal like a broadcast VTR, and a sufficient S / N ratio cannot be obtained. Therefore, it is called an electrical noise canceller. A circuit is used to reduce noise. Figure 11 shows 102 by Katsuya Yokoyama, “NHK Home Video Technology” edited by the Japan Broadcasting Corporation.
The H-correlation noise reduction circuit described on pages 104 to 104. In the figure, (1) is an amplifier, (21) is a 1H delay device for delaying one horizontal scanning period (hereinafter referred to as "1H"), (22) and (24) are subtractors, and (23) is an amplitude. It is a limiter that limits.

Next, the operation will be described. The video signal has a strong vertical correlation. Due to the difference between the reproduction luminance signal and the 1H delay signal of the reproduction luminance signal delayed by the 1H delay unit (21) by the subtractor (22), a noise component having no line correlation is generated. can get.
However, even a signal component has a portion having no line correlation, and the signal component having no line correlation is also obtained as a difference output. However, since the noise component is generally smaller than the signal component, only the noise component of the output of the subtractor (22) can be passed through the limiter (23) that does not pass the large amplitude signal. That is, a signal component having no line correlation cannot pass through the limiter (23). Therefore, the output of the limiter (23) is a noise component having no line correlation and a small amplitude. This component is subtracted from the original signal by subtractor (2
By subtracting by 4), the noise component contained in the original signal can be reduced.

[Problems to be Solved by the Invention] Since the conventional noise reduction device is configured as described above, for example, when a signal B with a luminance change as shown in FIG. The output of (22) becomes a signal of the waveform shown in FIG. 12 (b), which is limited in amplitude by the limiter (23) and becomes a signal of the waveform shown in FIG. 12 (c). Therefore, the output signal of the subtractor (24) has the waveform shown in FIG. 12 (d). In other words, the conventional H-correlation noise reducing device has a problem that the transient characteristic in the vertical direction is deteriorated.

The present invention has been made to solve the above problems, and an object thereof is to obtain a noise reduction device that does not deteriorate the transient characteristics in the vertical direction.

[Means for Solving the Problems] In the noise reduction device according to the present invention, the unit delay time is any one of n horizontal scanning periods (n is an integer of 1 or more), n field periods, or n frame periods. τ
When, the low frequency component of the input video signal is removed, and the signal from which the low frequency component is removed is delayed by the unit delay time τ, or the input video signal is delayed by the unit delay time τ, A means for creating three signals at time (i−τ), time (i), and time (i + τ) by removing the low frequency component from the delayed input video signal, and a means for creating the three signals Among them, a phase inverting means for inverting the phase of the signal at the time center (i) in comparison with the phase of the signal at the time (i-τ) and the time (i + τ), and the signal whose phase has been changed. Three signals f (i−τ), f (i), and f (i + τ) (including time (i−τ), time (i), and time (i +), respectively.
The signal at τ) is shown. ) Line correlation, field correlation or frame correlation, the following characteristic expression MAX [MIN {f (i-τ), f (i)}, MIN {f (i), f (i + τ)}] + MIN [ MAX {f (i-τ), f (i)}, MAX {f (i), f (i + τ)}] (MAX indicates a function for selecting the maximum value, and MIN indicates a function for selecting the minimum value.) Correlation detection means for outputting a correlation detection signal, an amplitude control means for limiting the amplitude of the correlation detection signal and outputting an amplitude control signal, the phase of the input video signal at time (i) and the amplitude. It comprises a phase adjusting means for matching the phase of the limit signal and a means for subtracting the amplitude control signal from the input video signal at the time (i) where the phase is adjusted.

[Operation] The correlator configured by the non-linear circuit according to the present invention is
Since the correlation signal of the transient part of the input signal is not output at all, the characteristics of the transient part are not deteriorated even if the output signal of the correlator is subtracted from the input signal.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, (1) is an amplifier, (2), (3), (4)
Is a low-frequency component removing circuit, which is a high-pass filter HPF in this embodiment, but may be a band-pass filter.
(5) and (6) are 1H delay devices, (7) is a correlator composed of a non-linear circuit, (8) is a limiter that limits the amplitude,
(9) is an adder, (18) is an inverter, and (19) is a delay correction circuit.

FIG. 2 is a block circuit diagram showing an embodiment of the correlation detector (7). (10), (11) and (15) are maximum value selection circuits,
(12), (13) and (14) are minimum value selection circuits, (16) is an adder, and (17) is an amplifier having a gain of 1/2.

FIG. 3 shows an embodiment of the maximum value selection circuits (10), (11), (15), and FIG. 4 shows the minimum value selection circuits (12), (1).
It is a figure which shows the Example of 3) and (14).

Next, the operation of this embodiment will be described. Considering the case of a video signal as shown in FIG. 5 (a) as an input signal, the waveforms passing through the low frequency component removing circuits (2), (3) and (4) are shown in FIG. 5 (b). It becomes a waveform. Considering only the portion indicated by the dotted line A in FIG. 5 (b), the second input signal D of the correlator (7) has the waveform shown in FIG. 5 (c).
The output signal of the correlator (7) is the fifth signal for the reason described later.
The waveform is as shown in FIG. Therefore, the output signal of the subtractor (9) has the waveform shown in FIG. 5 (e), and does not deteriorate the transient characteristic in the vertical direction.

The delay correction circuit (19) is for matching the phase of the signal C input to the subtractor (9) with the phase of the signal H.

Further, when the second input signal D of the phase shifter (7) has a waveform as shown in FIG. 6 (a), the second output signal of the correlator (7) becomes the sixth shift signal for the reason described later. The waveform shown in FIG. 6 (b) is obtained, and the output signal H of the limiter (8) is subjected to amplitude limitation, so that the waveform shown in FIG. 6 (c) is obtained. Therefore, the output signal of the subtractor (9) has the waveform shown in FIG. 6 (e). If there is no limiter (8) that limits the amplitude here,
The output signal of the subtractor (9) has the waveform shown in FIG. 6 (d). That is, the limiter (8) is an indispensable circuit because it does not erase a specific pattern, and performs an important operation.

Next, the reason why the relationship between the input signal and the output signal of the correlator (7) is as described above will be explained.

If the signal level of input 1 in FIG. 2 is S1, the signal level of input 2 is S2, and the signal level of input 3 is S3, then
From the configuration shown in the figure, if S1 = S2 = S3, correlator output is S2 (or S1 or S3) S1> S2 = S3, correlator output is S2 (or S3) If S1>S2> S3, correlator output When the output is S2 S2> S1 = S3, the correlator output is When S2>S1> S3, the correlator output is When S2>S3> S1, the correlator output is If S3> S2 = S1, the correlator output is S2 (or S1). If S3>S2> S1, the correlator output is S2. If S3>S1> S2, the correlator output is If S1>S3> S2, the correlator output is There are 10 patterns. When this output pattern is applied to FIG. 5 (c), the input waveforms of inputs 1, 2, and 3 are the waveforms shown in FIGS. 7 (a), (b), and (c), respectively. When the above output pattern is applied to this input, the output waveform of the correlator (7) becomes the waveform shown in FIG. 7 (d). That is, the step-like signal is not output from the correlator (7).

On the other hand, if the input signal of the correlator (7) is the waveform shown in FIG. 6 (a), the three input waveforms of the correlator (7) are shown in FIGS. 8 (a), (b), ( The waveform is as shown in c). When the above-mentioned output pattern is applied to this input, the output signal of the correlator (7) has the waveform shown in FIG. This is equivalent to the waveform in Figure 6 (b). In the waveform pattern shown in FIG. 6 (a), the one having a small amplitude is a noise component having no vertical correlation. Therefore, the noise component passes through the limiter (8) for limiting the amplitude, and since the signal component generally has a large signal amplitude, it hardly passes through the limiter (8). Therefore, the output signal of the subtractor (9) is shown in FIG. A signal component is secured as shown in (e).

The HPF (3) and the inverter (1
The connection of 8) may be reversed.

In the embodiment of FIG. 1, when the adder (9) is to be a subtractor, the input of the correlator (7) is compared with the input of the correlator (7) of FIG. The configuration example is shown in FIG. In the figure, (2
5) and (26) are inverters, and (27) is a subtractor.

Further, although the low frequency component removing means shown in FIG. 1 is located after the 1H delay device, it may be arranged before the 1H delay device. An example of the configuration is shown in FIG. In the figure,
(28) is a 1H delay line.

Further, the maximum value selection circuit and the minimum value selection circuit shown in FIGS. 3 and 4 are not limited to the configurations shown in FIGS. 3 and 4, and in the case of a digital signal, an AND element and an OR element. Can be easily configured.

In the above embodiment, the delay time τ of the delay device is set to 1H, but it may be 2H or nH (N> 2, where n is an integer), 1 field or n field or 1 frame. Alternatively, the same effect can be obtained with n frames.

Further, in the above embodiment, the signals of three delay time differences τ are input to the correlation detector (7), and the following expressions MAX [MIN {f (i-τ), f (i)}, MIN {f (i ), F (i + τ)}] + MIN [MAX {f (i-τ), f (i)}, MAX {f (i), f (i + τ)}] However, the number of input signals is not limited to three, and it is expressed by the following equation using an odd number k of 3 or more signals shifted by unit delay time τ as input. The same effect can be obtained by using one having a correlation detection characteristic.

Then, for example, f (i−S) indicates a signal delayed by S from the signal fi, and f (i−S + τ) indicates the signal f (i−
A signal advanced by τ from S) is shown.

[Effects of the Invention] As described above, according to the present invention, the input signal from which the low-frequency component has been removed is delayed by nH, n fields or n frames by at least three signals, and the Since the signal component without line correlation of each input signal is extracted and the extracted signal is subtracted from the input signal, the correlator does not output the signal in the transient part for the step-like signal input. There is an effect of obtaining a noise reducing device having an excellent effect that the transient characteristic is not deteriorated even if the output of the correlator is subtracted from the input signal to reduce the noise component.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a block circuit diagram showing an example of the configuration of a correlator of this embodiment, and FIG. 3 is a maximum value selection circuit diagram of this correlator. FIG. 4 is a minimum value selection circuit diagram of this correlator, FIGS. 5 and 6 are signal waveform diagrams of respective parts for explaining the operation of this embodiment,
7 and 8 are waveform diagrams of input / output signals of the correlator shown in FIG. 2, FIGS. 9 and 10 are block circuit diagrams of another embodiment of the present invention, and FIG. 11 is a conventional circuit diagram. FIG. 12 is a block circuit diagram of the H correlation noise reducing circuit, and FIG. 12 is a signal waveform diagram of each part of this conventional example. (2), (3), (4) ... Low frequency component removal circuit,
(5), (6), (28) ... 1H delay device, (7) ... correlator, (8) ... limiter, (9), (16) ... adder,
(18), (25), (26) ... Inverter, (27) ... Subtractor, (10), (11), (15) ... Maximum value selection circuit, (1
2), (13), (14) …… Minimum value selection circuit, (28) ……
Delay correction circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A low frequency component of an input video signal when a unit delay time τ is n horizontal scanning period (n is an integer of 1 or more), n field period or n frame period. Is removed and the signal from which the low frequency component is removed is delayed by a unit delay time τ,
Alternatively, by delaying the input video signal by a unit delay time τ and removing the low-frequency component from the delayed input video signal, the time (i−τ), the time (i), and the time (i
+ Τ) means for creating three signals, and among the above three signals, the phase of the signal at time (i), which is the center in time, is the phase of the signal at time (i-τ) and time (i + τ). Phase inversion means that inverts the signal and three signals f (i-
Either line correlation, field correlation or frame correlation of τ), f (i), and f (i + τ) (representing signals at time (i−τ), time (i), and time (i + τ), respectively). The following characteristic expression MAX [MIN {f (i-τ), f (i)}, MIN {f (i), f (i + τ)}] + MIN [MAX {f (i-τ), f (i )}, MAX {f (i), f (i + τ)}] (MAX is a function that selects the maximum value, MIN is a function that selects the minimum value), and outputs the correlation detection signal. Detection means, amplitude control means for limiting the amplitude of the correlation detection signal and outputting an amplitude control signal, and phase adjustment means for matching the phase of the input video signal and the phase of the amplitude limit signal at time (i). , Means for subtracting the amplitude control signal from the input video signal at the phase adjusted time (i). 'S reduction device.