JPS60208175A - Noise reduction circuit - Google Patents

Abstract

PURPOSE:To minimize the deterioration of a picture by making noise reduction capability variable in a way that the noise reduction capability is made small when amount of noise is less and the noise reduction capability is increased when much noise exists. CONSTITUTION:A video signal Vin inputted to an input terminal 1 is amplified by a video amplifier 13 and inputted to a delay line 2 and also fed to AND circuits 4, 6. The signal delayed by a time tau at the delay line 2 is fed to a delay line 3 and AND circuits 4, 5, and a signal delayed by a time tau at a delay line 3 is fed to AND circuits 5, 6. After the output of the AND circuits 4, 5, 6 is added by an OR circuit 7, the result is attenuated by an attenuator 14, and a video output is obtained from an output terminal 8. A controlled DC voltage from a variable resistor 15 is fed to the attenuator 14, and the attenuation rate is changed depending on the amount of noise.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is directed to, for example, a video processing circuit of a color television receiver, which minimizes image deterioration and removes noise mixed into a video signal. The present invention relates to the configured noise reduction circuit.

[Technical background of the invention and its problems]

Generally, in a video processing circuit of a color television receiver, noise components mixed into a video signal greatly impair a reproduced image, causing image deterioration and information loss.

For this reason, attempts have been made to reproduce high-quality images by removing noise components from video signals mixed with noise. For example, the following methods can be cited.

(1) This is improved by changing the transmission band of the video processing circuit according to the electric field strength and lowering the band with many noise components.

(2) Since the power overlapping tram of the video signal of television broadcasting has a peak in each horizontal period, a filter that passes only the band in which the video signal/gwer sictrum is present is called a "cross-band". Noise components are reduced by passing the signal through a "C-shaped filter".

(3) A process of replacing the gray level of a pixel with the average value of gray levels in the vicinity of that pixel, that is, a smoothing process is performed.

(4) Using the correlation between adjacent pixels on the television screen, the prominent pulse-like signal is determined to be noise and removed.

The methods (1) to (3) above each have the following problems. First, in method (1), noise reduction is performed mainly by blocking high bands of the video signal, which causes blurring of fine patterns and edges of the reproduced image, resulting in image deterioration.

Still, noise reduction by the comb filter in (2) and (
Noise reduction by method 3) basically follows the same principle, and both methods have the problem of causing fraying at the edges.

Here, the method (4) above will be briefly explained. FIG. 1 is a waveform diagram showing an example of a video signal, FIG. 2 is a waveform diagram showing an example of a step waveform, and FIG. 3 is an explanatory diagram of noise reduction operation by method (4).

In television transmission and reception systems, the image transmitting side converts the gray level of pixels into temporally continuous electrical signals by scanning the image, and the receiver side synchronizes with the resolution scanning of the image on the transmitting side. By assembling and scanning the image, it is reconstructed into a two-dimensional image.

An example of a video signal converted into an electrical signal is the signal υ shown in FIG. 1, where the video signal X is expressed as a function of time t.

x = f(t) Now, let the video signal
1),! (1+1). Here, the following function P
fixed amount.

If P is the set of p(+ -), P(1), P(1+1), then p = (p(+-t), p(os
P(1+1)).

In this way, the video signal can be expressed by the formula P. For example, the step signal shown in FIG. 2 is pg(o, l, t). The relationship between P and video pattern is shown in Table 1 below.

<Table 1> By the way, in general, noise components mixed into video signals often have a matrix-like shape. Therefore, by setting P for the video signal by an appropriate time τ and removing this pulse signal when it is a 2-pulse signal shown in PyyPm in Table 1, the noise component can be reduced without deteriorating the image. can do.

For example, for the video signal shown in FIG. 3(a), the video signal shown in FIG. 3(b)
The signal additively mixed with the noise signal shown in Figure 3 (e
) shows the waveform. In addition, in Fig. 3(e), PI + p
g) The symbol P7 r ps indicates P of the signal pattern corresponding to Table 1. This signal is P7 +P8 in Table 1.
The output is shown in Figure 3(d).
The waveform shown in is obtained, and the noise is reduced. At this time, since the rising edge and falling edge 9 of the step signal are not blocked, the edge portion is not filled.

Next, a specific circuit configuration of the noise reduction circuit according to method (4) will be explained.・In order to block the pulse signals P7 and P8, for the Nors signal P-d, P(i) should be replaced with O and P=(0,0,0)=P+, and the pulse signal For P8, P(i) is rlJ
Replaced with P = (1, 1, 1) = P! And it is sufficient.

As this method, P(amount-1) y P(D , P (
By taking a majority vote of i+1), the cells signal Pt
It constitutes a noise filter circuit for blocking yPs. After passing through the filter circuit, let p(g be Q(1)
Then, Q(1)=(p(t-t)xp(+)) +(p(ox
The characteristics of the filter circuit can be expressed by the following equation: p(++x))+(p(s-1)xp(t+t)). However, "x" and "+" in the above formula represent logical product and logical sum. Further, the filter characteristic shown in the above equation is equivalent to the characteristic shown in the following equation.

Q(i) = (P(1-1)+P(+))X(P(1)
10P(j+1))

FIG. 4 (1) is a circuit diagram showing an example of an AND circuit.
The emitters and ri of the two PNP type transistors T1zT2 are made common, each collector is grounded, and the common emitter and ri are connected to a resistor R1.
Each transistor TI, T! Inputs A and B are added to the pace of , and output C is taken out from the common emitter.

FIG. 4(b) is a circuit diagram showing an example of an OR circuit.
The emitters of two IPN type transistors T3) T4 are common, this common emitter is grounded via a resistor R1, and each collector is connected to a DC power supply.The input A is connected to the base of each transistor T3) T4. , B are added, and an output d is taken out from the common emitter.

Further, in addition to the circuit shown in FIG. 4, a 7' relay line (delay line) is used to construct a noise filter circuit. An example of a noise filter circuit according to the above method is shown in FIGS. 5 and 6.

In FIG. 5, the filter circuit connects a delay line 2 having a delay time τ to an input terminal 1 to which the long signal v1n is applied, and connects a delay line 2 having a delay time τ in series with this delay line 2.
connect the delay line 3 of the delay line 2, connect the AND circuit 4 between the output terminals of the delay line 2, connect the AND circuit 5 between the output terminals of the delay line 2, and connect the input terminal of the delay line 2 and the delay line An AND circuit 6 is connected between the output terminal of 3 and the output terminal of 3. A logical sum circuit 7 is connected to calculate the logical sum of the respective outputs of the logical product circuits 4, 5.6.

The output of the OR circuit 7 is taken out from the output terminal 8.

FIG. 6 also shows the AND circuit 4°5.6 shown in FIG. 5 as OR circuits 9, 10, . The circuit configuration is such that the OR circuit 7 is replaced with the AND circuit 12.

Although the noise reduction circuit (4) configured as described above has a noise reduction effect, it is desirable to have knowledge of the points listed below.

(1) Since this method does not judge and remove only noise, fine pulse-like patterns are also removed in the same way as noise, causing image deterioration.

Since the noise reduction ability is constant regardless of the presence or absence of noise,
Image deterioration is noticeable when there is little noise.

(2) The noise detection and reduction capabilities of OR circuits and AND circuits are limited, and they do not operate effectively as noise reduction circuits for noise below a certain level.

For example, the OR circuit shown in FIG. 4(b) has an input A of "
0'', when a signal rlJ is input to input B, transistor T4 turns on, increases the emitter potential of transistor T3, turns off transistor T3, and outputs C.
outputs a signal called rlJ of input B. Figure 10 (
Figure a) shows the transfer characteristics of this OR circuit.

According to FIG. 10(a), the potential difference between input A and input B is O
There is a section that changes linearly around this point. This range is approximately ±50mV, and the OR circuit does not operate properly and the transistor T is closed.

does not turn on completely and operates as an adder circuit.

Further, the AND circuit operates as a subtraction circuit.

FIG. 10(b) is an explanatory diagram of the operation of the OR circuit.

Noise included in the linear transfer characteristic range as shown in (1) of Figure io (b) is input to the OR circuit input A,
When a flat signal (2) is input to input B, the OR circuit only works as an adder, noise reduction cannot be performed by half of the input (approximately 6 dll), and the output is (3).
It becomes as shown in .

[Purpose of the invention]

In view of the above-mentioned points, the present invention provides a noise reduction circuit that can vary the noise reduction ability so that when there is little noise, the noise reduction ability is reduced to prevent image deterioration, and when there is a lot of noise, a large noise reduction ability is obtained. The purpose is to provide.

[Summary of the invention]

The noise reduction circuit of this invention amplifies an input signal with an amplifier, delays it for a predetermined time, outputs at least three or more output signals, generates them with a delay means, and uses a logic means from the output of the delay means and the output of the amplifier. A logic operation is performed to remove the protruding noise signal, and the output of this logic means is attenuated by an attenuator. The gain between the input side and the output side of the attenuator is kept constant.

[Embodiments of the invention]

Embodiments of the noise reduction circuit of the present invention will be described below with reference to the drawings. FIG. 7 is a block diagram showing the configuration of one embodiment. The embodiment shown in FIG. 7 corresponds to the conventional noise reduction circuit shown in FIG. 5, and the same parts as in FIG. 5 will be described with the same reference numerals.

The input terminal 1 to which the video input signal V1n is applied is connected via a video amplifier 13 to the input side of a delay line 2 having a delay time τ, and the output side of this delay line 2 is connected to a delay line 3 having a delay time τ as well. connected to the input side of the

An AND circuit 4 is connected between the input and output terminals of the delay line 2, and an AND circuit 5 is connected between the input and output terminals of the delay line 3.
is connected. An AND circuit 6 is connected between the input terminal of the delay line 2 and the output terminal of the delay line 3. The outputs of the AND circuits 4, 5, and 6 are connected to an OR circuit 7, and the output of the OR circuit 7 is connected to an output terminal 8 via an attenuator 14.

The gain and attenuation of the Eirin amplifier 13 and the attenuator 14 are controlled by the control DC voltage supplied from the variable resistor 15, so that the gain between the input terminal 1 and the output terminal 8 of the noise reduction circuit is always kept constant. It has become.

Next, the operation of the noise reduction circuit of the present invention configured as described above will be described. The video input signal vln input to the input terminal 1 is amplified by the video amplifier 13, and is input to the delay line 2 and simultaneously applied to the AND circuits 4 and 6.

The signal input to the delay line 2 is delayed by a time τ and is applied to the AND circuits 4 and 5 and the delay line 3. The AND circuit 4 ANDs the output signal of the video amplifier 13 and the output signal of the delay line 2, and outputs the result to the OR circuit 7.

Also, the output signal of delay line 2 is
The signal is delayed by the delay time τ and added to the AND circuits 5 and 6. As a result, the AND circuit 5 connects the delay line 2,
The logical product of the output signals of 3 and 3 is outputted to the logical sum circuit 7.

Further, the AND circuit 6 performs the AND of the output signal of the video amplifier 13 and the output signal of the delay line 3, and outputs the result to the OR circuit 7. The OR circuit 7 is composed of these OR circuits 4.
.

At this time, a control DC voltage is applied to the video amplifier 13 and the attenuator 14 from the variable resistor 15. Therefore, the gain of the video amplifier 13 is controlled by this control DC voltage, and the attenuation amount of the output signal of the OR circuit 7 is controlled by the control DC voltage of the attenuator 14. In this way, the gain between input terminal 1 and output terminal 8 is always kept constant.

For example, when the control voltage output from the variable resistor 15 increases, the gain of the video amplifier 13 increases, and the control voltage is applied to the delay lines 2 and 3, the AND circuits 4, 5, and 6, and the OR circuit 7. Before rising, a significantly amplified signal is input.

As a result, the noise is small as shown in (1) in Figure 10 (b), so the noise reduction is not effective and the noise cannot be reduced by 6 dBl, as shown in Figure 10 (b).
(4).

Therefore, in the output of the logic circuit, noise reduction is performed as shown in (6) of FIG. 10 (1)).

Further, the amount of attenuation of the attenuator 14 also increases as the control voltage increases, and the output terminal 8 outputs a video signal with the same gain as before the increase in the control voltage. Therefore, the noise shown in (6) in Figures 10-) also occurs in Figure 1O (b
As shown in (7) of ), a large noise reduction ability can be obtained with a small size.

As described above, according to the above embodiment, the noise reduction ability of the noise reduction circuit can be varied; when there is little noise, the noise reduction ability is reduced to suppress image deterioration, and when there is a lot of noise, the noise reduction ability is increased. Noise can be effectively reduced.

In addition, in the description of the above embodiment, the variable resistor 15 was used to control the gain of the video amplifier 13 and the attenuation amount of the attenuator 14, and the noise reduction ability was manually changed.
As shown in the block diagram of FIG. 8, a signal level detection circuit 16 extracts a video signal in a synchronizing signal period and outputs a DC voltage depending on the amount of AC components contained in this period, or a signal level detection circuit 16 that outputs a noisy weak electric field. It is also possible to include a signal level detection circuit (so-called AGC circuit) 16 that detects and outputs a DC voltage according to the level, and to automatically change the noise reduction ability according to the amount of noise contained in the video signal. It is possible. The rest of the configuration in FIG. 8 is the same as that in FIG. 7.

Further, in the noise reduction circuit of the present invention, as shown in FIG. 9, the AND circuits 4 and 5.6 in FIG.
0.11 and the OR circuit 7 in FIG. 7 may be replaced with the AND circuit 12.

Furthermore, although the above embodiment has been described with reference to the case in which the noise reduction circuit is applied in the horizontal direction, a similar noise reduction circuit can be constructed even if it is applied in the vertical direction or in both the horizontal and vertical directions.

〔Effect of the invention〕

As described above, according to the noise reduction circuit of the present invention, the input signal amplified by the amplifier is delayed by the predetermined delay means to output at least three output signals, and the logic between the output of the delay means and the output of the amplifier is After the calculation is performed using logic means to remove the prominent signal, it is attenuated by an attenuator, and the attenuation amount of this attenuator and the gain of the amplifier are controlled by the control means, and the input side of the amplifier and the attenuator are controlled. Since the gain between the output sides is kept constant, the noise reduction ability can be reduced when there is little noise, and the noise reduction ability can be increased when there is a lot of noise. Accordingly, when applied to a video processing circuit of a color television receiver, image deterioration can be suppressed to a minimum.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a video signal, Fig. 2 is a diagram showing a step signal waveform and its samples, Fig. 3 is an operation explanatory diagram of a method for noise reduction using the correlation of momentary contact pixels, Figure 4 (&) is a circuit diagram showing a conventional AND circuit applied as a filter circuit that uses the correlation between adjacent pixels on a television screen to determine a prominent noise signal as noise. b) is a circuit diagram showing a conventional OR circuit applied as a filter circuit that uses the correlation between adjacent pixels on a television screen to determine a prominent/slight signal as noise, FIGS. 5 and 6. Each figure is a block diagram of a conventional noise reduction circuit, FIG. 7 is a block diagram of one embodiment of the noise reduction circuit of the present invention, and FIGS. 8 and 9 are respectively other embodiments of the noise reduction circuit of the present invention. 10(a) is a diagram showing the transfer characteristics of the OR circuit of FIG. 4(b), and FIG. 10(b) is a circuit diagram of the OR circuit of FIG. 4(a) and of the OR circuit of FIG. FIG. 3 is a diagram for explaining the state of noise reduction in the noise reduction circuit of the present invention in comparison with that of the OR circuit. 1...Input terminal, 2, 3...r relay line, 4~
6, 12... AND circuit, 7, 9-11... OR circuit, 8... Output terminal, 13... Video amplifier, 14
...attenuator, 15...variable resistor, 16...signal level detection circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 1 Figure 4 (a) Figure 3 Figure 9 Figure 10 [1 Exit (b)

Claims (1)

[Claims] an amplifier for amplifying an input signal; a delay means for outputting at least three or more signals by delaying the output of the amplifier by a predetermined delay time; Logic means for performing calculations and removing protruding/slightly wave-like signals; an attenuator for attenuating the output of the logic means; and maintaining a constant gain between the input of the amplifier and the output of the attenuator. A noise reduction circuit comprising means for varying the gain of the amplifier and the attenuation l of the attenuator so as to.