JPS5844874A - Afc circuit - Google Patents

Abstract

PURPOSE:To decrease the effect of a ghost signal component and other noise components, by controlling an oscillator with a burst signal in assuming as a reference phase signal. CONSTITUTION:A burst signal is detected from a video signal from an input terminal IN at a band pass filter 31 and a detector 32 and applied to a switch circuit 35. A signal of the synchronizing signal part through a synchronizing separation circuit 33 and a pulse stretcher circuit 34 is inputted to the switch circuit 35 and a detected output of the burst signal only is outputted from the switch circuit 35. This output is inputted to a phase detector 37 and an AFC loop consisting of the phase detector 37, a low pass filter 38, a voltage controlled oscillator 39 and a frequency divider 40 is controlled with this output.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AFC (automatic frequency control) circuit that controls the oscillation frequency in a television receiver or the like, and particularly relates to an AFC (automatic frequency control) circuit that stably performs an oscillation operation using a burst signal of a television signal. Regarding circuits.

A so-called AFC circuit is used in a horizontal oscillation circuit of a television receiver or the like to control its oscillation frequency. In this case, the AFC circuit compares the phase of the horizontal synchronizing signal separated from the television signal with the phase of the output of the oscillation circuit, and controls the oscillation frequency based on the comparison result.

In this case, since the phase of the synchronization signal is used as the reference phase, means for separating the synchronization signal is important.

FIG. 1 shows a conventional AFC circuit, in which a horizontal synchronization signal SH is separated from a video signal Sp by a synchronization separation circuit 1. This separated horizontal synchronizing signal SR is supplied to one input terminal of the phase detector 12. The other input terminal of the phase detector 12 is supplied with a signal obtained by frequency-dividing the output of the voltage-controlled tokenizer vCO13 by a frequency divider 14. and,
The phase detector 12 compares the phase of the synchronization signal Sll and the output of the frequency divider 14. A voltage based on the result of this phase comparison is supplied to VOO7J, and AFC operation is performed.

The synchronous separation circuit 11 of this conventional AFC circuit has two transistors Q+t+Q+t, and has a video signal 8. is supplied to the pace of transistor Q11 via capacitor Ctt. Suppose now that a video signal of negative polarity arrives. At this time, the transistor Q1 clamps the tip of the horizontal synchronizing signal SH at a predetermined voltage, and the transistor Q+t
It functions to turn off when the collector current of t+ decreases.

FIG. 2 shows the video signal Sp in the AFC circuit of FIG.
(See Figure 2(, )).
(see Figure 2(b)) is the output terminal O in the AIi”C roots.
This shows a state in which synchronization is achieved with the UT signal So. in this case,
Noise components superimposed on the horizontal synchronization signal SH and ghost signal components due to transmission distortion are not considered, but knocking actually occurs due to these influences.

That is, if we explain this by assuming that a positive ghost signal component is superimposed on a synchronization signal part as shown in FIG. 3(a), the superimposed ghost signal part is separated as a horizontal synchronization signal (a third (see figure (b)), output signal So
The phase of is shifted by Δψ from the normal phase ψ0. Similarly, when a negative goth signal component is superimposed, a narrow synchronization separation output is obtained, and the phase of the output signal So is the normal phase ψ. It deviates from the.

Note that such a shift becomes a problem particularly when the delay time of the ghost signal component up to the width of the horizontal synchronizing signal SH is multiplied by m.

In this way, in the conventional AFC circuit, the horizontal synchronizing signal SR is separated while the leading end of the incoming horizontal synchronizing signal SH is clamped, so that the horizontal synchronizing signal SH is free from noise such as cost signal components. If a component is mixed in, an AFC operation is performed at a phase different from the original phase. This results in
VCo 13 in the AFC loop will have a constant phase error, or when separating the horizontal synchronization signal S++, the picture signal part will also be separated, causing jitter. There are problems such as disorder.

Of course, even if an AFC circuit having such drawbacks is used in a horizontal oscillation circuit, the desired operation cannot be obtained. Further, such a drawback becomes a big problem in a system in which a predetermined circuit is operated using a signal obtained by an AFC operation as a reference pulse.

Here, for reference, an example of the above-mentioned system will be explained using FIG. 4. Not shown in Figure 4, the system is C0.
This ghost removal device uses a transformer 9-monkey filter having an analog delay line with a tag formed by a charge-coupled device (D), an LC circuit, etc., and removes a ghost signal component from a television signal.

In the figure, IN is a video signal input terminal, and OUT is a video signal output terminal. The video signal P input from the input terminal IN undergoes ghost signal component elimination in the transpersal filter 21, and is led to the output terminal OUT. Trance 9
- The monkey filter 2 has a function of eliminating a ghost signal component by adding a signal having a polarity opposite to that of the ghost signal component to the video signal SP including the ghost signal component. That is, transpersal filter 2
1 has a tagged analog delay line, and each tap of the tagged analog delay line is provided with a weighting circuit for generating a data erase signal. An analog memory is provided corresponding to each weighting circuit.

Digital data stored in each storage section (corresponding to each tag) of the tap-din memory section 28 (described later) is converted into an analog signal and written into each analog memory. This analog quantity serves as a weighting coefficient in the weighting circuit. 1 In order to eliminate the ghost signal component in this way, it is necessary to separate the ghost signal component and the normal video signal SP.
It is necessary to know the phase difference between the two signals and the amplitude of the ghost signal component. This is detected as follows.

The output video signal of the transpersal filter 21 is input to a subtractor 22. This subtractor 22 uses the video signal Sp
It has the function of differentiating . The output of this differentiator 22 is applied to one input terminal of the converter 2S and compared with a reference level.

The output (Oorl) of the commutator 23 is input to the buffer register 24. Here, buffer register 2
4 introduces and stores the output of the comparator 24 for a predetermined period from the leading edge of the vertical synchronizing signal. In this case, differentiator 2
In No. 2, a differential signal occurs at the leading edge of the vertical synchronization signal of the original television signal and the ghost signal component.

Therefore, the data d stored in the buffer register 24
: Indicates the phase difference between the cost signal component and the regular video signal SP. The data stored in the buffer register 24 is
It is read out cyclically within the vertical synchronization signal period and applied to one input terminal of the correlator 25. The output of the digital differentiator 27 is input to the other input terminal of the correlator 25 . The video signal SP is input to a waveform integrator 26, where the leading edge portion of the vertical synchronization signal is waveform integrated, and its digital data is stored in the waveform integrator 26. The digital data from the waveform integrator 26 is input to the correlator 25 via the differencer 27 in synchronization with the data read timing of the buffer register 24 .

The correlator 25 has a function of detecting a distortion signal, and detects the digital difference device 27 according to the output of the buffer register 27.
Cumulatively add the outputs of . Then, the polarity of the cumulatively added result is determined and 0 or 1 is output. The output of the correlator 25 is written into a corresponding storage section of the tap-din memory section 28 in accordance with the phase difference between the leading edge of the vertical synchronization signal and the ghost signal component. This calculation is performed, for example, by adding "■#" in the case of a positive polarity ghost, and subtracting "1#" in the case of a negative polarity ghost. Note that the data in each storage section of the tap-din memory section 28 is rewritten every vertical scanning period.

The tap-din memory section 28 has a storage section corresponding to a plurality of taps of the transpersal filter 21. The data in each storage section is incremented by -1 or +1 depending on the output (0 or 1) of the correlator 25. Tatsu7°r
The data in each storage section of the in-memory section 28 is transferred via a digital-to-analog converter (hereinafter referred to as a D/A converter) 29.
and is input to the corresponding analog memory of the transversal filter 21. At this time, polarity data for identifying data for removing positive polarity ghosts and data for removing negative polarity ghosts is also read out from the tap-din memory section 28, and the transversal filter 28 is applied to the control terminal of Note that the data in each analog memory of the transpersal filter 21 is rewritten every horizontal scanning period.

The above operations are repeated, and when the data in each storage section of the fly'in-memory section 28 converges to a certain value, a value that can sufficiently erase the boost signal, the correlator 28
The output of will be either ``bi'' or 0#, and the data in the tap-dyne memory will oscillate across the least significant bit or several bits.

Reference numeral 30 denotes a timing pulse generator, which generates timing pulses for obtaining the data read timing of the buffer register 24 and the data read timing of the tap-din memory section 28, etc. mentioned above. This timing noise generator 30 is generally of the type A2 described above.
0 circuit is used to generate a signal synchronized with a synchronization signal separated from the input video signal, and this signal is used as a reference) to obtain the timing and pulse as described above. Therefore, if the A20 circuit ceases to operate normally due to the incorporation of ghost signal components as described above, problems such as the inability to remove the ghost signal components from the video signal P arise.

SUMMARY OF THE INVENTION In view of the above points, it is an object of the present invention to provide an A20 circuit that is less affected by the Gorse H-number component and other noise components.

Hereinafter, a typical embodiment of the present invention will be described with reference to the drawings. 3. Figure 5 is a circuit diagram showing a typical embodiment of the present invention. The reference phase signal is obtained by a synchronization signal and a burst signal.

In the figure, a part of the video signal SP (FIG. 6(a)) supplied to the input terminal IN is a pantono of 3.58 Mllz. The color signal component that is supplied to a band filter (BPF) Jl and passed through this band filter 31 is detected by a detector 32 (see FIG. 6(d)). This detector 32 is 3.5
8 This is for detecting the burst signal component of MIlz, and the phase is 1 with the envelope detection circuit or the burst signal signal.
．． ' It may be a multiplication detection circuit that detects a burst signal by multiplying it by 800 different subcarriers. - Also, the video signal SP (see FIG. 6(,)) is also supplied to the synchronization separation circuit 33, where the horizontal synchronization signal SH (see FIG. 6(,)
b) Reference) is separated. Separated horizontal synchronization signal Sn
The pulse width is expanded by a pulse expansion circuit 13 composed of, for example, a monostable multivibrator (see FIG. 6(c)). The expansion width of this pulse width is set to be a time width sufficient to include the burst signal inserted into the pack pouch of the horizontal synchronizing signal SH. The output signal Po (see FIG. 6(, )) of the main signal expansion circuit 34 is extracted and supplied as signal to the r-) control terminal of the switch circuit 35 composed of an analog dart. That is, The switch circuit 35 opens the dart only during the period when the extraction/main pulse PO is supplied, and allows the detected output of the detector 32 to pass through.Therefore, only the detected output of the burst signal is taken out to the output terminal of the switch circuit 35. The output of this switch circuit 35 is compared with a predetermined threshold level vT in a commutator 36. As a result, the output terminal of the commutator 36 receives a signal corresponding to the strike signal period. Yarus P (see FIG. 6(e)) is obtained.

The pulse P1 of 15.75 Ktlz thus obtained becomes a phase reference signal for the phase detector 37 forming the AFC loop. And the phase detector 37 is
Low-pass filter s s , vc.

39, AFC Luzo is completely formed in exchange with the frequency divider 40.

To explain the above AFC Luso, the above VCO39
The output of is divided by the frequency divider 40, and as shown in FIG.
g) The signal is converted into a pulse P2+PA as shown in (g)) and is supplied to the phase detector 37. The detection output of this phase detector 37 is smoothed by the low-pass filter 38, and the VC
It is supplied to O39 as a control voltage.

The phase detector 37 is configured as shown in FIG. 7, for example. In the figure, Q, ~Q, are Tran Zosta, and R8-
R3 is a resistor, CI+02 is a capacitor, and E
1+E2 is a constant voltage source, and 10B is a power supply. Transistor Q5.

Pulse Po for Q4 and Q2 pace.

Input terminal IN, , IN2゜IN to which Pl+P2 is applied
, is provided.

In the above configuration, the transistor Q is turned on only during the period of the pulse P1, and furthermore, at that time, the mother pulse PI is
If it exists during the period of the mother pulse P, the transistor Q3 is also turned on during the period of the god pulse P1. And transistor Q
The detection output appearing on the collector side of Q2 is shown in Figure 6 (h
). Since the AIi'C Luzo is a phase-locked Luer'PLL having the phase detector 37 with the characteristics described above, the pulse P2
The rising edge of is located at the center of the pulse P, and the pulse P is at a low level in and around the pulse P0 period, and is at a high level during other periods.
When the phase is locked to o, the detection characteristics of the phase detector 37 t,
) Approximately back 1? - The slope is rich during period t1, and it is flat during pattern period t2, with a center voltage of 1 ox. Therefore, even if the pulse P occurs during the picture period t2, no detection output is obtained due to the phase error between the pulse P and the pulse P. That is, during the period t2, the phase detector 37 becomes a dead zone. From the explanation in E below, the sync separation circuit 33 is activated during the picture period T2 due to the superposition of the ghost signal component.
A synchronized separated output is obtained, and the extraction pulse P is obtained. occurs, and even if the switch circuit 35 obtains the burst ghost signal component or the color signal component, the phase detector 37 becomes a dead zone during this picture period t, so the above-mentioned There is no possibility that a phase shift will occur between the video signal Sp and the arms p, , p, due to malfunction.

Furthermore, even if a narrow synchronization separation output is obtained at the leading edge or trailing edge of the horizontal synchronizing signal SH due to the superposition of ghost signal components as in the conventional example described above, the pulse expansion circuit 34 In the switch circuit 35, the circuits for deriving the pulse width of
It is possible to reliably extract the detection output (.P) of the burst signal.

``Depending on the delay amount of the ghost signal component, the ghost signal component of the color signal in the picture may be applied to the burst signal, but in this case, if a multiplication detection circuit is used as the detector 32, Ghost signal components of color signals are hardly detected. This is because the multiplicative detection circuit detects the burst signal using a subcarrier whose phase is 180° different from that of the burst signal, so unless the ghost signal component of the color signal matches the phase of the burst signal, it will not be detected. This is because no detection output can be obtained.

Ushida, Gurus P obtained by detecting the burst signal.

If the width of S is shifted and narrowed due to the superimposition of a ghost signal component, etc., a steady error etc. will occur as explained earlier in the case where a ghost signal component is superimposed on the horizontal synchronization signal S using Fig. 3. However, even if a ghost signal component is added, if the distortion does not become thinner, no phase shift will occur due to the control action of the AF'C roots.

Here, the reason why the Luz PI is not biased even when the cost signal component is added will be explained. In Figure 8, B
This BPFJJ is 3.58 M for the signal passing through PFJJ.
Because it has a narrow band pass characteristic of Hz, it becomes as shown in Fig. 8 (,), and its °0'' level does not change even with A P L , ghost signal components, etc. The burst signal is
stone ωt, signal gold (2) ωt obtained by shifting the phase of the carrier signal locked to the burst signal by automatic phase control APC means
Then, both signals are processed by a detector 32 using a multiplicative detector, for example.
The output multiplied by . It becomes 1,000 Rus. Comparator 3 using all appropriate threshold levels Vt.
6, the comparison result is a pulse P1 shown in FIG. 6 (,).

Next, when a ghost signal component with a short delay time is included, B
PF,? The output of 1 is a signal obtained by adding the burst ghost signal of FIG. 9(b) to the ghost signal of FIG. 9(,). In this case, depending on the phase of the burst ghost signal, the output of the detector 32 is as shown in FIG. 9(c), (d),
It will look like the one shown in (,). FIG. 9(c) shows when the burst ghost signal is in opposite phase to the burst signal, FIG. 9(d) shows when the burst ghost signal is in the same phase as the burst signal, and FIG. This shows when the ghost signal has a phase difference of +2 from the burst signal. Here, if the amplitude level of the burst ghost signal is set to m ((1) times the amplitude level (A) of the burst signal, the detected burst ghost signal will be +Am at maximum, but
Since it is a multiplication output, the amplitude level of the detected burst ghost signal is as small as +Am except when it is in the opposite phase and in the same phase, and the amplitude level is usually larger.

Furthermore, in this case, since the '()' level does not change, there is no need to clamp and separate it like the horizontal synchronizing signal, and the converter/quantizer 36 can set the threshold level V as appropriate.
By cutting at T, if m is an appropriately small value, for example 10 or less, the width will not be narrowed to one side.

As detailed above, according to this embodiment, the base pulse obtained by detecting the Gust signal is used as a reference phase signal of the horizontal period, and a PLL is formed to phase-synchronize the oscillation output with this reference phase signal. Because of this configuration, even if other noise components are mixed into the cost signal component, a horizontal or vertical reference signal with an accurate phase can always be obtained.

As described above, according to the present invention, it is possible to provide an entire AFC circuit that is less affected by the signal component and other noise components.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional AFCN path, and Figure 2 is a circuit diagram showing a conventional AFCN path.
Figure 3 is a signal waveform diagram used to explain the operation of Figure 1. Figure 4 is a signal waveform diagram used to explain the shortcomings of Figure 1. Figure 4 is a signal obtained by AFC operation that operates a predetermined circuit as a total reference signal. FIG. 5 is a circuit diagram showing an example of the AFCl path according to the present invention, FIG. 6 is a signal waveform diagram for explaining the operation of FIG. 5, and FIG. Fifth
Circuit diagram showing the specific circuit configuration of the phase detector in the figure, No. 8
9 and 9 are signal waveform diagrams for explaining the operation of FIG. 5. 31... Pantono? Filter, 32...Detector,
33... Synchronization separation circuit, 34... Pulse expansion circuit,
35...Switch circuit 1.96...Connograph regulator, 37...Phase detector, 38...Low pass filter, 39...VCO, 40...Frequency divider.

Claims (1)

[Claims] a burst signal detection means for detecting a burst signal from a human-powered video signal; and a phase lock druso for synchronizing the phase of the output of one output with the reference phase signal using the burst signal detected by the burst signal detection means as a reference phase signal. AFC circuit equipped with.