JPH0477070A - Discrimination circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for free-running frequency adjustment of a VCO by employing a 1st frequency divider circuit, a 2nd frequency divider circuit and a comparator receiving an output of a subtractor circuit via a detection circuit for the discrimination circuit. CONSTITUTION:An input terminal 1 connects to an input of an AM-DET 3 and an input of a limiter amplifier 10. An output of the AM-DET 3 is inputted to a 1st input terminal of a phi-FET 4 and inputted to a loop filter 5 and the output of the loop filter 5 is inputted to a VCO 8. Moreover, the output of the VCO 8 is inputted to a 1/n frequency divider circuit 9 and connected to a 2nd input terminal of the phi-DET 4 to form a PLL circuit. An output of the limiter amplifier 10 is inputted to an m/n frequency divider circuit 11 and inputted to a 1st input terminal of a subtractor circuit 12. An output of the VCO 8 is inputted to a 2nd input terminal of the subtractor circuit 12. An output of the VCO 8 is inputted to the 2nd input terminal of the subtractor circuit 12 and the output of the subtractor circuit 12 is connected to an input of a comparator 6 via a detection circuit 3. Thus, the adjustment of a free-running frequency for the VCO is not required and a defect of deviation of setting due to a secular change or much adjustment man-hour are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a discrimination circuit, and more particularly to a discrimination circuit used to discriminate between stereo broadcasting and bilingual Japanese broadcasting during Japanese television audio multiplex broadcasting.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional discrimination circuit. As shown in the figure, an input terminal 1 is connected to the first input of a phase comparator circuit (hereinafter referred to as φ-DET) 4 via an amplitude demodulation circuit (hereinafter referred to as AM-DET) 3.
From the output of this φ-DET 4, φ
- A PLL circuit is configured by connecting to the second input of DET4. Furthermore, the output of the loop filter 5 is LP
It is connected to the input of the comparator 6 via E14, and the output of the comparator 6 is connected to the output end 2.

Next, the operation of the conventional example will be explained. At input terminal 1, carrier frequency 55.1kHz <3.5fo), 922.5H
z or a discrimination signal AM modulated (60% DEV) at 982.5 Hz is input.

After demodulating this discrimination signal by AM-DET, φ-D
The free run frequency of the VCO 15 is compared with the free run frequency of the VCO 15 in the ET4, and the difference is extracted as a change in DC voltage through the loop filter 5, and the demodulated signal (922, 5
VC○1 to match Hz or982.5Hz)
Configure a PLL loop to control 5.

At this time, by removing ripples from the output of the loop filter 5 and inputting it to the comparator 6 via the LPF 14, the 922.5Hz or 98Hz of the demodulated signal of the AM-DET3 is
The comparator 6 outputs which of the 2.5 Hz is input as DC voltage low or high, and can be identified.

The threshold value of comparator 6 is the same frequency as the free run frequency (952,5Hz>) of VCO 15, and φ-DET4
The output DC voltage of the loop filter 5 is set to be the same as the output DC voltage when the first input voltage is applied.

Oscillation of the VCO 15 is performed by passing a charging/discharging current through the capacitor 17, and the charging/discharging current is made to vary (±10%) the capacitance value of the capacitor 17 using the variable resistor 16.
Adjust to 5Hz.

In addition, the free run frequency of VCO15 is 952°5Hz.
The accuracy must be within ±6.3% in order to discriminate between 922.5Hz and 982.5Hz.

[Problem to be solved by the invention]

The conventional discrimination circuit described above uses a variable resistor 16 to adjust the free-run frequency of the VCO 15 to 952.5 Hz. However, since the variable resistor is used, the settings may become incorrect due to changes over time, and the adjustment man-hours are increased. There are such drawbacks.

An object of the present invention is to provide a discriminating circuit that does not require free-run frequency adjustment of CO.

[Means to solve the problem]

The discrimination circuit of the present invention includes a phase comparison circuit whose first input is the input signal demodulated by the amplitude demodulation circuit, a loop filter whose input is the output of the phase comparison circuit, and whose input is the output of the loop filter. a voltage-controlled oscillator circuit,
a first frequency divider circuit which receives the output of the voltage-controlled oscillator circuit and supplies the output to a second input of the phase comparison circuit; a second frequency divider circuit that uses the output of the oscillation circuit as a reset signal;
The present invention is characterized in that it has a subtraction circuit that receives as input the output of the frequency dividing circuit, and a comparator that receives as input the output of the subtraction circuit via the detection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the discrimination circuit of the present invention. As shown in the figure, the input terminal 1 is connected to the input of the AM-DET 3 and the input of the limiter amplifier 10. AM-D
The output of ET3 is input to the first input terminal of φ-DET4,
The output of this φ-DET4 is used as the input of the loop filter 5, and the output of the loop filter is used as the input of vcos,
Further, the output of the VCO 8 is input to an n frequency divider circuit 9, and the output of the n frequency divider circuit 9 is connected to the second input terminal of the φ-DET 4, thereby forming a PLL circuit.

The output of the limiter amplifier 10 is input to the m/n frequency divider circuit 11, and the output of this m/n frequency divider circuit 11 is input to the subtraction circuit 1.
2, and the output of CO8 is input to the second input terminal of the subtraction circuit 12, and this subtraction port R12
The output is connected to the input of the comparator 6 via the detection circuit 13. In addition, the VCO is connected to the reset input of the m/n frequency divider circuit.
8 outputs are connected. Note that the threshold value of the comparator 6 is determined by the bias source 7.

Next, the operation of the present invention will be explained with reference to FIGS. 3(a) and 3(b). Carrier frequency 55.1kHz at input end 1
(3,5fu), 922.5Hz or 982.5H
When a discrimination signal subjected to AM modulation (60% DE■) with z is input, the discrimination signal is demodulated to 922.5 Hz or 982.5 Hz by AM-DET and output. AM-DET
922.5Hz or 982.5Hz demodulated by
The phase is compared with the signal that is input to φ-DET4 and the free run frequency of vcos is divided by the n frequency divider 9, and the difference is fed back to the control input of the VCO 8 via the loop filter 5 to determine the free run frequency. 922.5Hz or 982
．． Configure a PLL circuit to match 5Hz.

Further, from the discrimination signal inputted from the input terminal 1, only the carrier frequency is extracted by the limiter amplifier 10, and the AM modulated signal (922.5Hz or 982.5Hz>) is removed.The carrier frequency signal is sent to the m/n frequency dividing circuit 11. The frequency is divided by , and the negative input is input to the subtraction circuit 12.The positive input of the subtraction circuit 12 inputs the output signal of vcos.Note that the positive and negative inputs of the subtraction circuit 12 may be reversed here.

Further, the output signal of the vcos is inputted to the reset input of the m/n frequency divider circuit, and operates only during the high level period or the low level period of the vcos output signal.

First, the frequency of the n frequency divider 9 is divided by 2 (n=2), and the frequency of the m/n frequency divider 11 is divided by 29 (m=58.n-2m/n=29).
) and the modulation frequency of the discrimination signal is set to 922.5 Hz will be described with reference to FIG. 2(a).

First, the PLL circuit locks and the oscillation frequency of VCO8 becomes 1.
845Hz (922.5Hz x 2), the high level period is 271μs, the high level period of the m/n frequency dividing circuit is 263μs, and the output of the subtraction circuit 12 has a positive value of 8μ5 (271μL - 263μS - 8μs). A pulse output signal is output.

This pulse output signal is integrated by the detection circuit 13 and outputted as the amount of change in DC voltage (increased from the reference level in the initial state), and inputted to the comparator 6.

The bias source 7 for the threshold value of the comparator 6 is used by the detection circuit 13 when there is no pulse output signal at the output of the subtraction circuit 12.
Set it slightly higher than the output voltage. Therefore, when the modulation frequency of the discrimination signal is 922.5 Hz (during bilingual Japanese broadcasting), a High DC voltage signal is output to the output (output end 2) of the comparator 6.

Next, when the modulation frequency of the discrimination signal is 982.5Hz,
The PLL circuit is locked and the oscillation frequency of VCO8 is 1965.
Hz (982,5Hz x 2), the high level period is 254μs, and the high level period of the m/n frequency divider circuit is 254μs, that is, it was scheduled to be reset in the middle of frequency division and become 263μs, but it falls at 254μs. , vcos and the output of the m/n frequency dividing circuit 11 have the same waveform.

The output of the subtraction circuit 12 only generates a pulse-like whisker due to the delay, and there is no change in the DC voltage even when integrated by the detection circuit 13, and the output of the comparator 6 is a low-level DC voltage signal. .

In the above operation, the frequencies of 922.5Hz and 982°5Hz are identified using the carrier frequency signal (55, IXHz
= 3.5fH) is used as the standard, so vcos
The free run frequency does not need to be 952.5Hz as in the conventional case, but must be within the capture range at 922.5H.
The capture range should be wide enough to include z and 982°5Hz.

〔Effect of the invention〕

As explained above, the present invention is applicable to 922.5Hz and 982Hz.
．． Since the carrier frequency is divided and used as a reference for frequency identification of 5 Hz, there is no need to adjust the CO8 free run frequency to 952.5 Hz as in the past, and the capture range can be adjusted to vary the free run frequency of VCOS (resistance). ±5%, capacitor; ±10%) ±15% (approximately 143
Hz), 922.5Hd, and 982.5Hz, 2
If the frequency is set to 10 Hz or more (143 Hz+60 Hz≦210 Hz), free-run frequency adjustment of ■CO becomes unnecessary, and the drawback that the setting becomes deviated due to changes over time and that it takes a lot of adjustment man-hours can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) and (b) are operational waveform diagrams of FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 1...Input end, 2...Output end, 3...AM-DE
T, 4...φ-DET, 5... Loop filter, 6
... Comparator, 7... Bias source, 8, 15.
...V6O13...n frequency divider circuit, 10...limiter amplifier, 11...m/n frequency divider circuit, 12...subtraction circuit, 13...detection circuit, 14...LPE, 16
...Variable resistor, 17...Capacitor.

Claims (1)

[Claims] a phase comparison circuit whose first input is the input signal demodulated by the amplitude demodulation circuit; a loop filter whose input is the output of the phase comparison circuit; and a voltage-controlled oscillation circuit whose input is the output of the loop filter. , a first frequency divider circuit which receives the output of the voltage controlled oscillator circuit and supplies the output to a second input of the phase comparator circuit, and divides the input signal via the limiter amplifier to control the voltage. a second frequency divider circuit that uses the output of the voltage controlled oscillation circuit as a reset signal; a subtraction circuit that receives the output of the voltage controlled oscillator circuit and the output of the second frequency divider circuit; A discriminator circuit comprising: a comparator that receives the output of the subtraction circuit as an input.