JP2821248B2 - Discrimination circuit - Google Patents
Discrimination circuitInfo
- Publication number
- JP2821248B2 JP2821248B2 JP2187656A JP18765690A JP2821248B2 JP 2821248 B2 JP2821248 B2 JP 2821248B2 JP 2187656 A JP2187656 A JP 2187656A JP 18765690 A JP18765690 A JP 18765690A JP 2821248 B2 JP2821248 B2 JP 2821248B2
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- JP
- Japan
- Prior art keywords
- signal
- frequency
- circuit
- voltage
- discrimination
- Prior art date
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は判別回路に関し、特に日本国テレビ音声多重
放送時において、ステレオ放送から２カ国語放送かを識
別する為に用いる判別回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discriminating circuit, and more particularly to a discriminating circuit used to discriminate a stereo broadcast from a bilingual broadcast in Japanese TV audio multiplex broadcasting.
第３図は、従来の判別回路の一例を示すブロック図で
ある。同図に示すように、入力端１は振幅復調回路（以
下AM・DETと称す）３を介して、位相比較回路（以下φ
−DETと称す）４の第一入力に接続されており、このφ
−DET4の出力よりループフィルタ５及び電圧制御型発振
回路（以下VCOと称す）15を介して、φ−DET4の第二入
力に接続することによりPLL回路を構成している。更
に、ループフィルタ５の出力はLPF14を介してコンパレ
ータ６の正側入力端に接続され、負側入力端にはバイア
ス源７が接続され、コンパレータ６の出力が出力端２に
接続されている。FIG. 3 is a block diagram showing an example of a conventional discrimination circuit. As shown in FIG. 1, an input terminal 1 is connected to a phase comparator (hereinafter referred to as φ) through an amplitude demodulator (hereinafter referred to as AM / DET) 3.
−DET) is connected to the first input of
A PLL circuit is configured by connecting the output of -DET4 to the second input of φ-DET4 via a loop filter 5 and a voltage-controlled oscillation circuit (hereinafter referred to as VCO) 15. Further, the output of the loop filter 5 is connected to the positive input terminal of the comparator 6 via the LPF 14, the bias source 7 is connected to the negative input terminal, and the output of the comparator 6 is connected to the output terminal 2.
次に従来例の動作を説明する。入力端１にキャリア周
波数55.1KHz（3.5fH）が、922.5Hz又は、982.5HzでAM変
調（60％DEV）された判別信号を入力する。AM−DETによ
りこの判別信号を復調した後、φ−DET4にてVCO15のフ
リーラン周波数と比較し、その差分をループフィルタ５
を介して直流電圧の変化分として取り出し、AM−DET3の
復調信号（922.5Hz or 982.5Hz）に一致する様、VCO1
5を制御するPLLループを構成する。Next, the operation of the conventional example will be described. Carrier frequency 55.1KHz to the input terminal 1 (3.5f H) is, 922.5Hz or inputs AM modulation (60% DEV) discriminant signal 982.5Hz. After demodulating this discrimination signal by AM-DET, φ-DET4 compares it with the free-run frequency of VCO15, and compares the difference with the loop filter 5
, And as a change in the DC voltage, the VCO1 is adjusted to match the demodulated signal (922.5 Hz or 982.5 Hz) of the AM-DET3.
Construct a PLL loop that controls 5.
この時、ループフィルタ５の出力をLPF14を介して、
リップル分を取り除きコンパレータ６に入力する事で、
AM−DET3の復調信号の922.5Hz又は982.5Hzのいずれが入
力されたかを直流電圧のロウ又はハイとしてコンパレー
タ６へ出力し、識別する事ができる。At this time, the output of the loop filter 5 is passed through the LPF 14,
By removing the ripple and inputting it to the comparator 6,
Which of 922.5 Hz or 982.5 Hz of the demodulated signal of AM-DET3 has been input is output to the comparator 6 as a low or high DC voltage and can be identified.
コンパレータ６のしきい値はVCO15のフリーラン周波
数（952.5Hz）と同一周波数が、φ−DET4の第一入力に
入った時のループフィルタ５の出力直流電圧と同値に設
定を行う。The threshold value of the comparator 6 is set to the same frequency as the free-run frequency (952.5 Hz) of the VCO 15 and the same value as the output DC voltage of the loop filter 5 when the first input of the φ-DET 4 is input.
VCO15の発振は、コンデンサ17に充放電電流を流して
行なわれ、充放電電流は可変抵抗16にてコンデンサ17の
容量値のバラツキ（±10％）させ、952.5Hzに合わせ
る。The oscillation of the VCO 15 is performed by supplying a charge / discharge current to the capacitor 17, and the charge / discharge current is varied by the variable resistor 16 (± 10%) and adjusted to 952.5 Hz.
なお、VCO15のフリーラン周波数を952.5Hzに合わせる
精度は、922.5Hzや982.5Hzの判別を行う為、±6.3％以
内にしなければならない。Note that the accuracy of adjusting the free-run frequency of the VCO 15 to 952.5 Hz must be within ± 6.3% in order to determine 922.5 Hz or 982.5 Hz.
上述した従来の判別回路は、VCO15のフリーラン周波
数を952.5Hzに合わせる為、可変抵抗16による調整を行
っていたが、可変抵抗を使用する為経時変化により設定
がズレたり、調整工数がかかる欠点がある。The conventional discrimination circuit described above has been adjusted with the variable resistor 16 in order to adjust the free-run frequency of the VCO 15 to 952.5 Hz. There is.
本発明の目的はVCOのフリーラン周波数調整が不要な
判別回路を提供することにある。An object of the present invention is to provide a discrimination circuit that does not require VCO free-run frequency adjustment.
本発明の判別回路は、搬送波信号が第１の周波数また
は第２の周波数をとる変調信号で変調されて生成された
判別信号を受けて、当該判別信号を生成した変調信号は
第１の周波数および第２の周波数のどちらかを判別する
判別回路であって、判別信号を受けて当該判別信号から
変調信号を取り出す振幅復調回路と、振幅復調回路で取
り出した変調信号を受けて当該変調信号のｎ倍の周波数
をもつパルス状の発振信号を出力するPLL回路と、判別
信号を受けて当該判別信号から搬送波信号を取り出すリ
ミッタ増幅器と、リミッタ増幅器で取り出した搬送波信
号と発振信号とを受けて当該搬送波信号を分周してパル
ス状の分周信号を発生しかつ発振信号のハイレベルまた
はロウレベルの期間分周信号の出力がリセットされる分
周回路と、発振信号と分周信号とを受けて当該発振信号
と当該分周信号とのレベルが異なるとき第１のレベルを
とりレベルが同じとき第２のレベルをとるパルス出力信
号を出力する減算回路と、パルス出力信号を受けて当該
パルス出力信号を積分した検波信号を出力する検波回路
と、検波信号を受けて当該検波信号の電圧と基準電圧と
を比較して検波信号の電圧が基準電圧より高いとき判別
信号を生成した変調信号が第１の周波数であると判別
し、検波信号の電圧が基準電圧より低いとき判別信号を
生成した変調信号が第２の周波数であると判別するコン
パレータとを有することを特徴とする。The discrimination circuit of the present invention receives a discrimination signal generated by modulating a carrier signal with a modulation signal having a first frequency or a second frequency, and generates a discrimination signal having a first frequency and a A discriminating circuit for discriminating one of the second frequencies, an amplitude demodulation circuit for receiving a discrimination signal and extracting a modulation signal from the discrimination signal, and an n of the modulation signal receiving the modulation signal extracted by the amplitude demodulation circuit. A PLL circuit that outputs a pulsed oscillation signal having a double frequency, a limiter amplifier that receives a discrimination signal and extracts a carrier signal from the discrimination signal, and a carrier wave that receives the carrier signal and the oscillation signal extracted by the limiter amplifier. A frequency divider circuit for dividing the signal to generate a pulse-like frequency-divided signal and resetting the output of the frequency-divided signal during a period of high or low level of the oscillation signal; A subtraction circuit that receives a frequency signal and outputs a pulse output signal that takes a first level when the level of the oscillation signal and the frequency-divided signal are different and takes a second level when the level is the same; A detection circuit that receives the detection signal and outputs a detection signal obtained by integrating the pulse output signal; and generates a determination signal when the detection signal voltage is higher than the reference voltage by comparing the detection signal voltage with the reference voltage. A comparator that determines that the modulated signal has the first frequency, and that determines that the modulated signal that has generated the determination signal has the second frequency when the voltage of the detection signal is lower than the reference voltage. .
次に、本発明について図面を参照して説明する。第１
図は本発明の判別回路の一実施例を示すブロック図であ
る。同図に示すように入力端１はAM−DET3の入力とリミ
ッタ増幅器10の入力に接続されている。AM−DET3の出力
はφ−DET4の第１入力端に入力され、このφ−DET4の出
力をループフィルタ５の入力とし、そのループフィルタ
５の出力をVCO8の入力とし、更にVCO8の出力をｎ分周回
路９の入力とし、ｎ分周回路９の出力をφ−DET4の第二
入力端に接続することによりPLL回路を構成している。Next, the present invention will be described with reference to the drawings. First
FIG. 3 is a block diagram showing an embodiment of the discrimination circuit of the present invention. As shown in the figure, the input terminal 1 is connected to the input of the AM-DET3 and the input of the limiter amplifier 10. The output of AM-DET3 is input to the first input terminal of φ-DET4. The output of φ-DET4 is used as the input of loop filter 5, the output of loop filter 5 is used as the input of VCO8, and the output of VCO8 is n. A PLL circuit is formed by connecting the input of the frequency divider 9 and the output of the frequency divider 9 to the second input terminal of φ-DET4.
リミッタ増幅器10の出力はm/n分周回路11に入力さ
れ、このm/n分周回路11の出力を減算回路12の第１の入
力端に入力し、VCO8の出力を減算回路12の第２の入力端
に入力しており、この減算回路12の出力を被波回路13を
介してコンパレータ６の入力に接続する。又、m/n分周
回路のリセット入力にVCO8の出力が接続されている。な
お、コンパレータ６のしきい値は、バイアス源７にて決
定される。The output of the limiter amplifier 10 is input to an m / n frequency dividing circuit 11, the output of the m / n frequency dividing circuit 11 is input to a first input terminal of a subtracting circuit 12, and the output of the VCO 8 is The output of the subtraction circuit 12 is connected to the input of the comparator 6 via the wave receiving circuit 13. The output of the VCO 8 is connected to the reset input of the m / n frequency dividing circuit. Note that the threshold value of the comparator 6 is determined by the bias source 7.
次に、本発明の動作を第２図（ａ），（ｂ）を参照し
て説明する。入力端１にキャリア周波数55.1kHz（3.5
fH）が、922.5Hz又は982.5HzでAM変調（60％DEV）され
た判別信号を入力すると、判別信号はAM−DETにより92
2.5Hz又は982.5Hzに復調されて出力する。AM−DET3で復
調された922.5Hz又は982.5Hzは、φ−DET4に入力され、
VCO8のフリーラン周波数をｎ分周回路９で分周した信号
と位相比較を行い、差分をループフィルタ５を介してVC
O8の制御入力に帰還する事でフリーラン周波数を922.5H
z又は982.5Hzに一致させるPLL回路を構成する。Next, the operation of the present invention will be described with reference to FIGS. 2 (a) and 2 (b). Carrier frequency 55.1kHz (3.5
f H ) inputs a discrimination signal that is AM-modulated (60% DEV) at 922.5 Hz or 982.5 Hz, the discrimination signal is 92-Hz by AM-DET.
It is demodulated to 2.5 Hz or 982.5 Hz and output. 922.5 Hz or 982.5 Hz demodulated by AM-DET3 is input to φ-DET4,
The free-run frequency of the VCO 8 is compared with a signal obtained by dividing the frequency of the free-run frequency by the n-divider circuit 9, and the difference is calculated by the VC through the loop filter 5.
The free-run frequency is 922.5H by returning to the control input of O8.
Configure a PLL circuit that matches z or 982.5 Hz.
又、入力端１より入力した判別信号は、リミッタ増幅
器10によりキャリア周波数のみ取り出し、AM変調された
信号（922.5Hz又は982.5Hz）を取り除く、そのキャリア
周波数信号をm/n分周回路11で分周し、減算回路12に負
入力する。減算回路12の正入力は、VCO8の出力信号を入
力する。なお、ここで減算回路12の正，負入力が逆であ
ってもかまわない。From the discrimination signal input from the input terminal 1, only the carrier frequency is extracted by the limiter amplifier 10 and the AM-modulated signal (922.5 Hz or 982.5 Hz) is removed. The carrier frequency signal is divided by the m / n frequency dividing circuit 11. Then, a negative input is made to the subtraction circuit 12. The positive input of the subtraction circuit 12 receives the output signal of the VCO 8. Here, the positive and negative inputs of the subtraction circuit 12 may be reversed.
又、VCO8の出力信号はm/n分周回路のリセット入力に
入力し、VCO8の出力信号のハイレベルの期間又はロウレ
ベルの期間のみ動作する。The output signal of the VCO 8 is input to the reset input of the m / n frequency dividing circuit, and operates only during the high level period or the low level period of the VCO 8 output signal.
まず、ｎ分周回路９を２分周（ｎ＝２）とし、m/n分
周回路11を29分周（ｍ＝58,n＝２ m/n＝29）とした時
に判別信号の変調周波数を922.5Hzとした場合につい
て、第２図（ａ）を参照して説明する。まず、PLL回路
がロックしVCO8の発振周波数が1845Hz（922.5Hz×２
倍）となりハイレベルの期間は271μＳで、m/n分周回路
のハイレベルの期間は263μＳとなり、減算回路12の出
力には、８μＳ（271μＳ−263μＳ＝８μＳ）分の正パ
ルス出力信号が出力される。First, when the n-divider 9 is divided by 2 (n = 2) and the m / n divider 11 is divided by 29 (m = 58, n = 2 m / n = 29), the modulation of the discrimination signal is performed. The case where the frequency is 922.5 Hz will be described with reference to FIG. First, the PLL circuit is locked and the oscillation frequency of VCO8 is 1845 Hz (922.5 Hz × 2
Times), the high-level period is 271 μS, the high-level period of the m / n divider circuit is 263 μS, and the output of the subtraction circuit 12 outputs a positive pulse output signal of 8 μS (271 μS−263 μS = 8 μS). Is done.
このパルス出力信号を検波回路13で積分し直流電圧の
変化量（初期状態の基準レベルより増加）として出力
し、コンパレータ６に入力する。This pulse output signal is integrated by the detection circuit 13 and output as the amount of change in DC voltage (increased from the reference level in the initial state).
コンパレータ６のしきい値のバイアス源７は、減算回
路12の出力にパルス出力信号がない時の、検波回路13の
出力電圧よりわずかに高く設定する。その為、コンパレ
ータ６の出力（出力端２）に判別信号の変調周波数が92
2.5Hzの時（２カ国語放送時）はHigh直流電圧信号が出
力される。The bias source 7 of the threshold value of the comparator 6 sets the output voltage of the subtraction circuit 12 slightly higher than the output voltage of the detection circuit 13 when there is no pulse output signal. For this reason, the modulation frequency of the discrimination signal is 92
When the frequency is 2.5 Hz (during bilingual broadcasting), a High DC voltage signal is output.
次に、判別信号の変調周波数が982.5Hzの場合、PLL回
路がロックしVCO8の発振周波数が1965Hz（982.5Hz×２
倍）となり、ハイレベルの期間は254μＳで、m/n分周回
路のハイレベルの期間は254μＳ、すなわち分周途中で
リセットがかかり263μＳとなる予定が、254μＳで立下
るため、VCO8の出力とm/n分周回路11の出力とは同一波
形となる。Next, when the modulation frequency of the discrimination signal is 982.5 Hz, the PLL circuit locks and the oscillation frequency of the VCO 8 becomes 1965 Hz (982.5 Hz × 2).
Times), the high-level period is 254 μS, and the high-level period of the m / n divider circuit is 254 μS. That is, resetting is performed during the frequency division to become 263 μS. The output of the m / n frequency dividing circuit 11 has the same waveform.
減算回路12の出力には、遅延によるパルス状のひげが
発生する程度であり、検波回路13で積分しても直流電圧
の変化はなく、コンパレータ６の出力はロウレベルの直
流電圧信号が出力される。The output of the subtraction circuit 12 is such that a pulse-like whisker is generated due to the delay. Even if the integration is performed by the detection circuit 13, the DC voltage does not change, and the output of the comparator 6 outputs a low-level DC voltage signal. .
上記動作において、922.5Hzと982.5Hzの周波数の識別
は、キャリア周波数信号（55.1KHz＝3.5fH）を分周して
基準としている為、VCO8のフリーラン周波数は、従来の
様に952.5Hzにある必要はなく、キャプチャーレンジ以
内に922.5Hzや982.5Hzが入る様にキャプチャーレンジを
広く取れば良い。In the above operation, the identification of the frequency of 922.5Hz and 982.5Hz is, since the carrier frequency signal (55.1KHz = 3.5f H) as a dividing and reference, free-running frequency of VCO8 is, as conventionally 952.5Hz There is no need to have it, and a wide capture range may be set so that 922.5 Hz or 982.5 Hz falls within the capture range.
以上説明したように本発明は、922.5Hzと982.5Hzの周
波数識別にキャリア周波数を分周して基準としている
為、従来の様にVCO8のフリーラン周波数を952.5Hzに合
わせる必要がなく、キャプチャーレンジをVCO8のフリー
ラン周波数のバラツキ（抵抗；±５％，コンデンサ；±
10％）15％（約143Hz）と922.5Hzと982.5Hzが入る様、2
10Hz以上（143Hz＋60Hz≦210Hz）に設定すれば、VCOの
フリーラン周波数調整が不用となり、経時変化により設
定がズレたり、調整工数がかかる欠点が改善できる。As described above, in the present invention, since the carrier frequency is divided and used as a reference for discriminating the frequency between 922.5 Hz and 982.5 Hz, it is not necessary to adjust the free-run frequency of the VCO 8 to 952.5 Hz as in the past, and the capture range Is the variation in the free-run frequency of VCO8 (resistance: ± 5%, capacitor: ±
10%) 15% (about 143Hz), 922.5Hz and 982.5Hz, 2
If the frequency is set to 10 Hz or more (143 Hz + 60 Hz ≦ 210 Hz), it becomes unnecessary to adjust the free-run frequency of the VCO, and it is possible to improve the disadvantage that the setting is shifted due to aging and the adjustment man-hour is required.
第１図は本発明の一実施例を示すブロック図、第２図
（ａ），（ｂ）は第１図の動作波形図、第３図は従来例
を示すブロック図である。 １……入力端、２……出力端、３……AM−DET、４……
φ−DET、５……ループフィルタ、６……コンパレー
タ、７……バイアス源、8,15……VCO、９……ｎ分周回
路、10……リミッタ増幅器、11……m/n分周回路、12…
…減算回路、13……検波回路、14……LPE、16……可変
抵抗、17……コンデンサ。FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are operation waveform diagrams of FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 1 ... input terminal, 2 ... output terminal, 3 ... AM-DET, 4 ...
φ-DET, 5 ... Loop filter, 6 ... Comparator, 7 ... Bias source, 8,15 ... VCO, 9 ... N frequency divider circuit, 10 ... Limiter amplifier, 11 ... m / n frequency division Circuit, 12…
… Subtraction circuit, 13… Detector circuit, 14… LPE, 16… Variable resistor, 17… Capacitor.
Claims (1)
波数をとる変調信号で変調されて生成された判別信号を
受けて、当該判別信号を生成した変調信号は前記第１の
周波数および前記第２の周波数のどちらかを判別する判
別回路であって、 前記判別信号を受けて当該判別信号から前記変調信号を
取り出す振幅復調回路と、前記振幅復調回路で取り出し
た変調信号を受けて当該変調信号のｎ倍の周波数をもつ
パルス状の発振信号を出力するPLL回路と、前記判別信
号を受けて当該判別信号から前記搬送波信号を取り出す
リミッタ増幅器と、前記リミッタ増幅器で取り出した搬
送波信号と前記発振信号とを受けて当該搬送波信号を分
周してパルス状の分周信号を発生しかつ前記発振信号の
ハイレベルまたはロウレベルの期間前記分周信号の出力
がリセットされる分周回路と、前記発振信号と前記分周
信号とを受けて当該発振信号と当該分周信号とのレベル
が異なるとき第１のレベルをとりレベルが同じとき第２
のレベルをとるパルス出力信号を出力する減算回路と、
前記パルス出力信号を受けて当該パルス出力信号を積分
した検波信号を出力する検波回路と、前記検波信号を受
けて当該検波信号の電圧と基準電圧とを比較して前記検
波信号の電圧が前記基準電圧より高いとき前記判別信号
を生成した変調信号が前記第１の周波数であると判別
し、前記検波信号の電圧が前記基準電圧より低いとき前
記判別信号を生成した変調信号が前記第２の周波数であ
ると判別するコンパレータとを有することを特徴とする
判別回路。An identification signal generated by modulating a carrier signal with a modulation signal having a first frequency or a second frequency is received, and the modulation signal that generates the identification signal is a signal having the first frequency and the frequency. A discriminating circuit for discriminating any one of the second frequencies, comprising: an amplitude demodulation circuit for receiving the discrimination signal and extracting the modulation signal from the discrimination signal; A PLL circuit that outputs a pulsed oscillation signal having a frequency n times as high as the signal, a limiter amplifier that receives the discrimination signal and extracts the carrier signal from the discrimination signal, a carrier signal extracted by the limiter amplifier and the oscillation Receiving the signal and dividing the carrier signal to generate a pulse-like frequency-divided signal, and outputting the frequency-divided signal during the high or low level of the oscillation signal. A frequency divider circuit to be reset, receiving the oscillation signal and the frequency-divided signal, receiving a first level when the level of the oscillation signal and the frequency-divided signal are different, and a second level when the levels are the same.
A subtraction circuit that outputs a pulse output signal that takes the level of
A detection circuit that receives the pulse output signal and outputs a detection signal obtained by integrating the pulse output signal; and receives the detection signal, compares the voltage of the detection signal with a reference voltage, and adjusts the voltage of the detection signal to the reference voltage. When the voltage is higher than the voltage, the modulation signal that has generated the determination signal is determined to be the first frequency, and when the voltage of the detection signal is lower than the reference voltage, the modulation signal that generates the determination signal is the second frequency. And a comparator for determining that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2187656A JP2821248B2 (en) | 1990-07-16 | 1990-07-16 | Discrimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2187656A JP2821248B2 (en) | 1990-07-16 | 1990-07-16 | Discrimination circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0477070A JPH0477070A (en) | 1992-03-11 |
| JP2821248B2 true JP2821248B2 (en) | 1998-11-05 |
Family
ID=16209901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2187656A Expired - Lifetime JP2821248B2 (en) | 1990-07-16 | 1990-07-16 | Discrimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2821248B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7641575B2 (en) | 2004-04-09 | 2010-01-05 | Tsubakimoto Chain Co. | Hydraulic tensioner |
-
1990
- 1990-07-16 JP JP2187656A patent/JP2821248B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0477070A (en) | 1992-03-11 |
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