JP2000184230A - Horizontal synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize horizontal synchronization within a valid area. SOLUTION: This horizontal synchronizing circuit 10 includes a horizontal AFC circuit 16, and a horizontal synchronizing signal is given to the horizontal AFC circuit 16 from a synchronization separator circuit 12. The horizontal AFC circuit 16, an oscillation circuit (VCO) 20, a horizontal count-down circuit 22 form a PLL and the horizontal AFC circuit 16 generates a control voltage of the VCO 20. A low pass filter LPF 30 has a time constant of τ1, and an LPF 32 has a time constant of τ2 that is smaller than the time constant τ1. When the horizontal synchronization circuit 10 receives a composite video signal from a video cassette tape recorder VCR and a head is selected, an output voltage of a comparator 34 is at a high level but an output voltage of a comparator 36 goes to a low level. That is, a high level gain-up control signal is given to the horizontal AFC circuit 16 for the vertical blanking period, a loop gain of the PLL is increased. Thus, the control voltage is quickly converted and the phase synchronization is made stable within the vertical blanking period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronization circuit,
In particular, the present invention relates to a horizontal synchronizing circuit used for processing a video signal reproduced by, for example, a VCR and locking an oscillation frequency signal of a VCO to a horizontal synchronizing signal by a PLL method.

[0002]

2. Description of the Related Art In a conventional horizontal synchronizing circuit 1 of this type shown in FIG. 6, a horizontal synchronizing signal outputted from a synchronizing separation circuit 2 is applied to a horizontal AFC circuit 3, and a control voltage from the horizontal AFC circuit 3 is applied to an oscillator. (VCO) 4. VCO4
Is the frequency f _H of the horizontal synchronization signal based on the control voltage.
It is oscillated at twice the frequency. The oscillation frequency signal of VCO 4 is applied to horizontal countdown circuit 5 and horizontal output circuit 6. In the horizontal countdown circuit 5, the VCO 4
Is divided by 1/32 and the divided signal is
It is provided to the FC circuit 3. The horizontal AFC circuit 3 compares the phases of the horizontal synchronization signal and the frequency-divided signal from the synchronization separation circuit 2 and determines the control voltage of the VCO 4 based on the comparison result. As a result, the oscillation frequency signal of the VCO 4 is locked to the horizontal synchronization signal. The horizontal output circuit 6 amplifies the oscillation frequency signal of the VCO 4 and controls the horizontal deflection yoke 7 with the amplified signal.

[0003]

In such a conventional technique, a low-pass filter (L) included in the horizontal AFC circuit 3 is used.
The time constant of (PF) was set large. Therefore,
If the horizontal synchronizing signal shifts when switching the head of the VCR (when switching between fields), the shift of the oscillation frequency does not converge within the vertical retrace period, and a bend occurs at the start of the effective area (upper part of the screen). Was. On the other hand, LP
When the time constant of F is set to be small, the control voltage from the horizontal AFC circuit 3 is disturbed by noise included in the output of the synchronization separation circuit 2, and disturbance is generated on the screen.

[0004] Therefore, a main object of the present invention is to provide a horizontal synchronization circuit capable of stabilizing horizontal synchronization in an effective area.

[0005]

According to the present invention, there is provided a horizontal synchronizing circuit for locking an oscillation frequency signal to a horizontal synchronizing signal by a PLL, wherein a first detecting means for detecting a vertical blanking period and outputting a first detecting signal; A second detection unit that detects a lack of the horizontal synchronization signal and outputs a second detection signal, and an adjustment unit that adjusts a gain of the PLL based on the first detection signal and the second detection signal. This is a horizontal synchronization circuit.

[0006]

The horizontal synchronizing circuit locks the oscillation signal to the horizontal synchronizing signal by the PLL. The first detector detects a vertical blanking period and outputs a first detection signal, and the second detector detects a lack of a horizontal synchronizing signal and outputs a second detection signal. The adjusting means sets P based on the first detection signal and the second detection signal.
Adjust the LL gain.

According to one aspect of the present invention, a gate signal synchronized with the horizontal synchronizing signal is generated, and the first gate means gates the horizontal synchronizing signal in response to the gate signal. The second detecting means detects a lack of the horizontal synchronizing signal based on the output of the first gate means. In one embodiment of the present invention, the first gate means includes a first inverter and a first logical product. The first inverter inverts the horizontal synchronization signal, and the first logical product performs a logical product on the output of the first inverter and the gate signal.

[0008] In another embodiment of the present invention, the second detecting means includes a smoothing means and a comparing means. The smoothing means smoothes the output of the first gate means, and the comparing means compares the output of the smoothing means with a reference voltage to output a second detection signal. In another embodiment of the present invention, the comparing means includes a comparator and a second inverter. The comparator starts up when the output of the smoothing means is larger than the reference voltage, and the second inverter inverts the output of the comparator.

In still another embodiment of the present invention, the adjusting means includes second gating means, which gates the second detection signal in response to the first detection signal and outputs a gain adjustment signal. I do. In another embodiment of the present invention, the second gate means is a second AND means, and the second AND means performs an AND operation on the first detection signal and the second detection signal.

In another embodiment of the present invention, the adjusting means sets the gain of the PLL to a steady value when the second detection signal is not output, and sets the gain of the PLL to be smaller than the steady value when the second detection signal is output. To raise.

[0011]

According to the present invention, during the vertical blanking period, PL
Since the sensitivity of L is adjusted, horizontal synchronization can be stabilized in the effective area. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a horizontal synchronizing circuit 10 of this embodiment includes a sync separation circuit 12, and an input terminal 14 is connected to the sync separation circuit 12. A reproduction signal (composite video signal) or a video signal of a broadcast signal (composite video signal) from a video cassette tape recorder (VCR) not shown is input to the input terminal 14. The composite video signal is sync-separated by a sync separation circuit 12 into a vertical sync signal (V-SEP) and a horizontal sync signal (H-SEP). The horizontal synchronizing signal is supplied to a horizontal AFC circuit 16 and ANDed via a NOT circuit (inverter) 17
One input terminal of the circuit 18 is provided. Horizontal AFC circuit 1
In 6, the control voltage for controlling the oscillation circuit (VCO) 20 is generated. The control voltage from the horizontal AFC circuit 16 is applied to the VCO 20. VCO20 is oscillates at 32 times the frequency of the frequency f _H of the horizontal synchronizing signal (32f _H), the oscillation frequency of the VCO20 the control voltage is controlled.

Oscillation frequency signal output from VCO 20
(Output signal) is supplied to the horizontal countdown circuit 22.
At the same time, it is given to the horizontal output circuit 24. Horizontal cow
In the countdown circuit 22, the output signal of the VCO 20 is 1 /
N (N is a factorial of 2). Horizontal counsel
In the down-down circuit 22, the output signal of the VCO 20 becomes 1/3.
A signal divided by 2 (divided signal) is generated. In addition,
The frequency of the divided signal is f _HBecomes Also, horizontal counter
The gate signal synchronized with the horizontal synchronizing signal
Horizontal gate pulse (H-sync GATE) is generated
You. Divided signal and horizontal gate pulse (H-SYNC GATE)
From the horizontal countdown circuit 22 to the horizontal AFC circuit 1
6 given. The frequency-divided signal is supplied to the line counter 26.
And the horizontal gate pulse is applied to the other
Is given to the input end. In the horizontal output circuit 24, VCO2
0 is power-amplified, and the amplified output signal is
It is provided to a flat deflection yoke 28.

The output signal of AND circuit 18 is applied to low pass filters (LPFs) 30 and 32. LPF
The time constant τ1 of 30 and the time constant τ2 of LPF 32 are set to different values. The time constant τ1 is set to a value close to about one vertical cycle, and the LPF 30 holds an output state indicating that the apparatus is in a synchronized state even if the horizontal synchronization signal is partially lost in the vertical cycle. On the other hand, the time constant τ2 is set to a value smaller than the time constant τ1, and the LPF 32 is in an output state indicating an asynchronous state if there is no horizontal synchronization signal even in one line. That is, the LPF 32 is set to have higher sensitivity than the LPF 30.

The output voltage of the LPF 30 is
, And the negative input terminal of the comparator 34 is supplied with the constant voltage Vr1. The comparator 34 compares the two inputs and supplies a high-level or low-level signal to the input terminal of the AND circuit 38. Also, L
The output of the PF 32 is supplied to a positive input terminal of the comparator 36, and a constant voltage Vr2 is supplied to a negative input terminal of the comparator 36. The comparator 36 compares the two inputs, and inputs a high-level or low-level signal to the input terminal of the AND circuit 38 via the NOT circuit 37. Further, the input terminal of the AND circuit 38 has a line counter 2
6. A vertical retrace pulse from 6 is input. AND circuit 38
Performs an AND operation on each input and outputs a high-level or low-level signal (gain-up control signal).
High level gain up control signal is applied to horizontal AFC circuit 1
6, the PLL formed by the horizontal AFC circuit 16, the VCO 20, and the horizontal countdown circuit 22
(Phase Locked Loop) loop gain is increased.
On the other hand, the low-level gain-up control signal
When provided to the circuit 16, the loop gain of the PLL is reduced.

As shown in FIG. 2, the horizontal AFC circuit 16 includes input terminals 40, 42, 44 and 46, and the input terminal 40 is connected to a connection point between the base of the transistor T1 and the base of the transistor T2. The emitter of the transistor T1 is connected to the emitter of the transistor T3 and to the collector of the transistor T4. The base of the transistor T4 is connected to the input terminal 42.
The base of the transistor T3 is connected to the base of the transistor T5, and the node between the transistor T3 and the transistor T5 is connected to the constant voltage source V1. The collector of the transistor T3 is connected to the collector of the transistor T2 and to the collector of the transistor T6.

The collector of the transistor T6 is connected to the base of the transistor T6 and to the base of the transistor T7. The emitter of the transistor T6 is connected to the emitter of the transistor T7 and to the constant voltage source V4. The collector of the transistor T7 is connected to the collector of the transistor T5.
The emitter of the transistor T2 is connected to the emitter of the transistor T5 and to the collector of the transistor T8. The base of the transistor T8 is connected to the constant voltage source V2. The emitter of the transistor T8 is
Connected to the emitter of transistor T4 and to the collector of transistor T9. The base of the transistor T9 is connected to one end of the resistor R1, and a connection point between the transistor T9 and the resistor R1 is connected to one end of a resistor R2.

The other end of the resistor R1 is connected to the constant voltage source V3, and the other end of the resistor R2 is connected to the input terminal 46. The emitter of the transistor T9 is connected to the collector of the transistor T10 via the resistor R3.
Are connected to a ground plane. Transistor T10
Is connected to the input terminal 44 via the resistor R4. The collector of the transistor T1 is connected to the output terminal 48, and one end of the resistor _RL is connected to a connection point between the transistor T1 and the output terminal 48. The other end of the resistor R _L is connected to the ground plane through the electrolytic capacitor C _L. That is, the resistance R _L , the electrolytic capacitor C _L, and the ground plane are connected in series to form the LPF 50.

The horizontal synchronizing signal from the synchronizing separation circuit 12 is input to an input terminal 40, and the frequency-divided signal is input to an input terminal 42. The horizontal gate pulse from the horizontal countdown circuit 22 is input to the input terminal 44, and the AND gate 3
8 is input to an input terminal 46. This horizontal AFC circuit 16 is a multiplier of the frequency-divided signal and the horizontal synchronization signal. When the horizontal gate pulse goes high, the transistor T10 turns on, and the transistor 9 as a constant current source also turns on. At this time, LPF5
0 is applied to the VCO via the output terminal 50.
20 given. On the other hand, when the horizontal gate pulse goes low, the transistor T10 does not turn on. That is, the control voltage of the VCO 20 is not generated. As described above, only when the horizontal gate pulse is at the high level, the horizontal A
The FC circuit 16 is driven to generate a control voltage.

When the gain-up control signal goes high, the base voltage of the transistor T9 becomes constant
3 and thus the transistor T9
Has a larger current than usual. For this reason, the sensitivity of the multiplier increases. That is, the horizontal AFC circuit 16, the VCO
16 and the horizontal countdown circuit 22
The loop gain of LL is increased. On the other hand, when the gain-up control signal goes low, the constant voltage source V3 is applied to the base of the transistor T9. Therefore, PLL
Returns to the steady value.

As shown in FIG. 3, the horizontal countdown circuit 22 includes an input terminal 60, and the input terminal 60 is a clock terminal (C) of a DQ flip-flop (DQ-FF) 62.
LK). The Q terminal of DQ-FF62 is DQ
-Connected to 64 clock terminals of FF and
Connected to the input terminal of ND circuit 74. The Q / (/ means inversion) terminal of the DQ-FF 62 is connected to the DQ-FF 62
, And to the input terminal of the AND circuit 72.

The Q terminal of the DQ-FF 64 is connected to the DQ-FF 6
6 and the AND circuit 7
2 and 74 are connected to the inputs. The Q / terminal of the DQ-FF64 is connected to the D terminal of the DQ-FF64. D
The Q terminal of the Q-FF 66 is connected to the clock terminal of the DQ-FF 68 and to the input terminal of the AND circuit 72. The D terminal of the DQ-FF 66 is connected to an AND circuit 74.
Is connected to the input terminal of The Q terminal of DQ-FF68
While being connected to the clock terminal of the Q-FF 70,
Connected to the input terminal of ND circuit 72. The D terminal of the DQ-FF 68 is connected to the input terminal of the AND circuit 74.

The Q terminal of the DQ-FF 70 is connected to an AND circuit 7
2 and the output terminal 82. The Q / terminal of the DQ-FF 70 is
And to the input terminal of the AND circuit 74. The clear terminals of the DQ-FFs 62 to 70 are connected to the ground plane. The input terminal 60 is connected to an AND circuit 72
And an input terminal of an AND circuit 74 via a NOT circuit 76. AND circuit 7
2 is connected to the D terminal of the DQ-FF 78,
The output terminal of the D circuit 74 is reset (R) of the DQ-FF 78.
Connected to terminal. The Q terminal of the DQ-FF 78 is connected to the output terminal 80.

In the horizontal countdown circuit 22, the VCO
The 20 output signal (32f _H ) is input to the input terminal 60 and is applied to the clock terminal of the DQ-FF 62. VC
The signal obtained by dividing the output signal of O20 by が is DQ-
It is output from the Q terminal of the FF62. Similarly, VCO 20
Is divided by the DQ-FFs 64 to 70 into 1 / N. Then, an output signal of the Q terminal of the DQ-FF 70, that is, a frequency-divided signal obtained by dividing the output signal of the VCO 20 by 1/32 is output from the output terminal 82.

The output signal from the VCO 20 (32f
_H ) is high level (H), the output signal from the Q terminal of the DQ-FF 62 is low level (L), and DQ-F
The output signal from the Q terminal of F64 is H, and DQ-FF
66, the output signal from the Q terminal is H, and the DQ-FF6
8 is H, the DQ-FF70
Is high, the output signal of the AND circuit 72 goes high. The output signal of the AND circuit 72 is latched by the DQ-FF 78, and a high-level output signal (horizontal gate pulse) is output from the output terminal 80. Then, the output signal (32f _H ) and each DQ-FF 62 to
The output signal from the Q terminal 70 is (H, H, L, L, L,
L), the output signal of the AND circuit 74 becomes H,
DQ-FF 78 is reset. That is, the horizontal gate pulse becomes low level. Therefore, as shown in FIG. 3B, the horizontal gate pulse rises at the 30th count of the output signal of the VCO 20, and falls at the 34th count.

More specifically, in the horizontal AFC circuit 16, a period in which the horizontal gate pulse is at a high level (about 6 μs)
Only the phase of the frequency-divided signal is compared with the phase of the horizontal synchronization signal, and the control voltage of the VCO 20 is output based on the comparison result. The control voltage is generated by the LPF 50 provided in the horizontal AFC circuit 16. Here, charging and discharging of the electrolytic capacitor C _L provided LPF50 is switched on the falling edge of the divided signal. That is, as shown in FIG. 3B, the electrolytic capacitor _CL is charged when the frequency-divided signal is at a high level, and discharged when the frequency-divided signal is at a low level. Therefore, the value of the control signal fluctuates according to the phase of the frequency-divided signal, and when the frequency-divided signal is locked to the horizontal synchronization signal, the charge period and the discharge period become equal to each other. As a result, the control voltage is stabilized.

As shown in FIG. 4, line counter 26 includes input terminals 90 and 92, and input terminal 90 is connected to SR-
Connected to S terminal of FF104. The input terminal 92 is D
Connected to the clock terminal of the Q-FF 94,
Connected to the input terminal of ND circuit 102. DQ-FF94
Is connected to the D terminal of the DQ-FF94.
The Q terminal of the DQ-FF 94 is connected to the clock terminal of the DQ-FF 96 and to the input terminal of the AND circuit 102. The Q / terminal of DQ-FF96 is DQ-F
Connected to D terminal of F96. The Q terminal of the DQ-FF 96 is connected to the clock terminal of the DQ-FF 98 and to the input terminal of the AND circuit 102.

The Q / terminal of the DQ-FF 98 is a DQ-FF
98 D terminal. The Q terminal of the DQ-FF 98 is connected to the clock terminal of the DQ-FF 100 and to the input terminal of the AND circuit 102. DQ-
The Q / terminal of the FF 100 is connected to the D terminal of the DQ-FF 100. The Q terminal of the DQ-FF 100 is connected to the input terminal of the AND circuit 102. DQ-FF94-100
Is connected to the ground plane. AND circuit 102
Is connected to the R terminal of the SR-FF 104.
The Q terminal of the SR-FF 104 is connected to the output terminal 106.

In the line counter 26, the synchronization separation circuit 1
2 is input to the input terminal 90.
The signal is supplied to the S terminal of the SR-FF 104. FIG.
As shown in (B), the vertical synchronizing signal goes high.
And the high-level vertical synchronization signal is
High level output signal (vertical retrace pulse)
Output from the Q terminal of the SR-FF 104 to the output terminal 106
It is. Further, the frequency-divided signal is input to the input terminal 92, and DQ
-Given to the clock terminal of FF94. DQ-FF9
In 4, the frequency-divided signal is frequency-divided by half and is frequency-divided by half.
The output signal is output from the Q terminal. Q of DQ-FF94
The output signal from the terminal is applied to the input terminal of the AND circuit 102.
Select and apply to the clock terminal of DQ-FF96.
Can be Similarly, in the DQ-FFs 96 to 100,
The frequency signal is divided into 1/4, 1/8, 1/16, and
Output from the Q terminal. The AND circuit 102 outputs
Signal f _HAnd from the Q terminal of DQ-FF94-100
Outputs a high-level signal when the output signal is high
Then, the SR-FF 104 is reset. Therefore,
As shown in FIG. 4B, the vertical retrace pulse is set to low level.
It is. That is, the vertical retrace pulse is applied during the vertical retrace period.
Only high level. Note that the vertical retrace pulse is horizontal
Although it is 1/256 of the synchronization signal (divided signal), DQ-F
Since a large number of F's are required, the frequency is divided by an integral multiple of 1/256.
Operating in the same way.

In FIG. 1, when a reproduction signal (composite video signal) from a VCR is input to an input terminal 14, a horizontal gate pulse, an output of a NOT circuit 17,
The waveforms of the output of the circuit 18, the output voltage of the LPF 32, and the output of the NOT circuit 37 (gain-up control signal) change as shown in FIG. Since the time constant τ1 of the LPF 30 is set to be large, the output voltage of the LPF 30 does not change even when the head of the VCR is switched (when switching between fields). That is, a constant voltage value is output. Therefore, the output voltage of the comparator 34 does not change. However, since the time constant τ2 of the LPF 32 is set to be small, if the horizontal synchronization signal is lost due to the switching of the head, that is, if the output of the NOT circuit 17 becomes low level while the gate is applied by the horizontal gate pulse, The output voltage of the LPF 32 becomes lower than 0 V (becomes a low level). At this time, the output of the NOT circuit 37 is at a high level, and the AND circuit 38 outputs a high-level signal. That is, a high-level gain-up control signal is output. For this reason, the control voltage output from the horizontal AFC circuit 16 converges in a short time, and distortion at the top of the screen due to head switching can be prevented.

When a video signal of a weak electric field is input to the input terminal 14, the level of the horizontal synchronization signal is low, so that it may be determined that the horizontal synchronization signal is missing. Therefore, when the output voltage of the LPF 32 goes low as described above, the gain-up control signal goes high. For this reason, the control voltage from the horizontal AFC circuit 16 is changed based on the output voltage of the LPF 32, but changes only within the vertical flyback period, so that a large horizontal swing does not occur on the screen.

Further, when there is no video signal at the input terminal 14, the output voltage of the LPF 30 is always at a low level, so that the output voltage of the comparator 34 is also at a low level. Therefore, a low-level gain-up control signal is output from the AND circuit 38. Note that the case where there is no video signal refers to a case where there is no video signal in the broadcast signal or a case where a connection cable to the VCR is not connected to the input terminal 14. Further, the LPF 30 and the comparator 34 are provided so as not to cause a malfunction when there is no video signal. When the broadcast signal without a video signal has no noise, the output voltage of the LPF 32 becomes low level, and the output voltage of the comparator 36 also becomes low level. At this time,
The gain-up control voltage is always at a low level, and a constant control voltage is output. On the other hand, when there is noise in the broadcast signal, the control voltage is disturbed by the influence of the noise, but there is no problem because a so-called sandstorm is displayed on the screen.

According to this embodiment, since the gain of the horizontal AFC circuit 16 is increased only during the vertical retrace period, the phase synchronization is stabilized during the vertical retrace period, and no distortion occurs at the top of the screen. Therefore, horizontal synchronization can be stabilized in the effective area. In addition, when a weak electrolysis video signal is input, the phenomenon that the roll is increased does not appear on the screen.

In this embodiment, when the gain-up control signal goes high, the loop gain of the PLL is increased by increasing the gain of the horizontal AFC circuit 16. However, a resistor having a variable capacitance is used. with R _L and / or the electrolytic capacitor C _L, LP by varying the capacitance of the resistor R _L or electrolytic capacitor C _L
The time constant of F50 may be reduced and the loop gain of the PLL may be increased.

[Brief description of the drawings]

FIG. 1 is an illustrative view showing one embodiment of the present invention;

FIG. 2 is an illustrative view showing a horizontal AFC circuit shown in the embodiment in FIG. 1;

FIG. 3 is an illustrative view showing a horizontal countdown circuit and an output waveform shown in the embodiment in FIG. 1;

FIG. 4 is an illustrative view showing a line counter and an output waveform shown in the embodiment in FIG. 1;

FIG. 5 is an illustrative view showing a waveform of an output voltage of each circuit corresponding to a video signal;

FIG. 6 is an illustrative view showing a conventional horizontal synchronization circuit.

[Explanation of symbols]

 Reference Signs List 10 horizontal synchronization circuit 12 synchronization separation circuit 16 horizontal AFC circuit 20 VCO 22 horizontal countdown circuit 26 line counter

Claims (8)

[Claims] 1. A horizontal synchronizing circuit for locking an oscillation frequency signal to a horizontal synchronizing signal by a PLL, first detecting means for detecting a vertical blanking period and outputting a first detection signal, and detecting lack of the horizontal synchronizing signal. And a second detection means for outputting a second detection signal, and an adjustment means for adjusting a gain of the PLL based on the first detection signal and the second detection signal. 2. The apparatus according to claim 1, further comprising: generating means for generating a gate signal synchronized with the horizontal synchronizing signal; and first gate means for gating the horizontal synchronizing signal in response to the gate signal. 2. The horizontal synchronization circuit according to claim 1, wherein said lack is detected based on an output of said first gate means. 3. The first gate means includes a first inverter for inverting the horizontal synchronizing signal, and a first AND means for performing an AND operation on an output of the first inverter and the gate signal. Horizontal synchronization circuit as described. 4. The second detecting means includes a smoothing means for smoothing an output of the first gate means, and a comparing means for comparing the output of the smoothing means with a reference voltage and outputting the second detection signal. The horizontal synchronization circuit according to claim 2 or 3. 5. A comparator for raising an output when an output of the smoothing means is larger than the reference voltage, and a second means for inverting an output of the comparator.
The horizontal synchronization circuit according to claim 4, further comprising an inverter. 6. The apparatus according to claim 1, wherein said adjusting means includes a second gate means for applying a gate to said second detection signal in response to said first detection signal and outputting a gain adjustment signal. 2. The horizontal synchronization circuit according to 1. 7. The horizontal synchronizing circuit according to claim 6, wherein said second gate means is second AND means for performing an AND operation on said first detection signal and said second detection signal. 8. The horizontal control system according to claim 1, wherein said adjusting means sets said gain to a steady value when said second detection signal is not output, and increases said gain when said second detection signal is output. Synchronous circuit.